Ben Skeggs | 344e107 | 2012-10-08 14:11:35 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
| 25 | #include <core/device.h> |
| 26 | #include <core/gpuobj.h> |
| 27 | #include <core/class.h> |
| 28 | |
| 29 | #include <subdev/fb.h> |
Ben Skeggs | bc98540 | 2014-08-10 04:10:24 +1000 | [diff] [blame^] | 30 | |
| 31 | #include "priv.h" |
Ben Skeggs | 344e107 | 2012-10-08 14:11:35 +1000 | [diff] [blame] | 32 | |
| 33 | struct nvd0_dmaeng_priv { |
| 34 | struct nouveau_dmaeng base; |
| 35 | }; |
| 36 | |
| 37 | static int |
| 38 | nvd0_dmaobj_bind(struct nouveau_dmaeng *dmaeng, |
| 39 | struct nouveau_object *parent, |
| 40 | struct nouveau_dmaobj *dmaobj, |
| 41 | struct nouveau_gpuobj **pgpuobj) |
| 42 | { |
Ben Skeggs | 47a1e0f | 2012-10-08 14:44:00 +1000 | [diff] [blame] | 43 | u32 flags0 = 0x00000000; |
| 44 | int ret; |
Ben Skeggs | 344e107 | 2012-10-08 14:11:35 +1000 | [diff] [blame] | 45 | |
| 46 | if (!nv_iclass(parent, NV_ENGCTX_CLASS)) { |
| 47 | switch (nv_mclass(parent->parent)) { |
Ben Skeggs | 4665406 | 2012-08-28 14:10:39 +1000 | [diff] [blame] | 48 | case NVD0_DISP_MAST_CLASS: |
| 49 | case NVD0_DISP_SYNC_CLASS: |
| 50 | case NVD0_DISP_OVLY_CLASS: |
| 51 | case NVE0_DISP_MAST_CLASS: |
| 52 | case NVE0_DISP_SYNC_CLASS: |
| 53 | case NVE0_DISP_OVLY_CLASS: |
Ben Skeggs | e5398b2 | 2013-03-30 22:31:25 +1000 | [diff] [blame] | 54 | case NVF0_DISP_MAST_CLASS: |
| 55 | case NVF0_DISP_SYNC_CLASS: |
| 56 | case NVF0_DISP_OVLY_CLASS: |
Ben Skeggs | c68c29c | 2014-02-24 14:26:44 +1000 | [diff] [blame] | 57 | case GM107_DISP_MAST_CLASS: |
| 58 | case GM107_DISP_SYNC_CLASS: |
| 59 | case GM107_DISP_OVLY_CLASS: |
Ben Skeggs | 344e107 | 2012-10-08 14:11:35 +1000 | [diff] [blame] | 60 | break; |
| 61 | default: |
| 62 | return -EINVAL; |
| 63 | } |
| 64 | } else |
| 65 | return 0; |
| 66 | |
Ben Skeggs | 47a1e0f | 2012-10-08 14:44:00 +1000 | [diff] [blame] | 67 | if (!(dmaobj->conf0 & NVD0_DMA_CONF0_ENABLE)) { |
| 68 | if (dmaobj->target == NV_MEM_TARGET_VM) { |
| 69 | dmaobj->conf0 |= NVD0_DMA_CONF0_TYPE_VM; |
| 70 | dmaobj->conf0 |= NVD0_DMA_CONF0_PAGE_LP; |
| 71 | } else { |
| 72 | dmaobj->conf0 |= NVD0_DMA_CONF0_TYPE_LINEAR; |
| 73 | dmaobj->conf0 |= NVD0_DMA_CONF0_PAGE_SP; |
| 74 | } |
| 75 | } |
| 76 | |
| 77 | flags0 |= (dmaobj->conf0 & NVD0_DMA_CONF0_TYPE) << 20; |
| 78 | flags0 |= (dmaobj->conf0 & NVD0_DMA_CONF0_PAGE) >> 4; |
| 79 | |
| 80 | switch (dmaobj->target) { |
| 81 | case NV_MEM_TARGET_VRAM: |
| 82 | flags0 |= 0x00000009; |
| 83 | break; |
| 84 | default: |
| 85 | return -EINVAL; |
| 86 | break; |
| 87 | } |
| 88 | |
| 89 | ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj); |
| 90 | if (ret == 0) { |
| 91 | nv_wo32(*pgpuobj, 0x00, flags0); |
| 92 | nv_wo32(*pgpuobj, 0x04, dmaobj->start >> 8); |
| 93 | nv_wo32(*pgpuobj, 0x08, dmaobj->limit >> 8); |
| 94 | nv_wo32(*pgpuobj, 0x0c, 0x00000000); |
| 95 | nv_wo32(*pgpuobj, 0x10, 0x00000000); |
| 96 | nv_wo32(*pgpuobj, 0x14, 0x00000000); |
| 97 | } |
| 98 | |
Ben Skeggs | 344e107 | 2012-10-08 14:11:35 +1000 | [diff] [blame] | 99 | return ret; |
| 100 | } |
| 101 | |
Ben Skeggs | bc98540 | 2014-08-10 04:10:24 +1000 | [diff] [blame^] | 102 | struct nouveau_oclass * |
| 103 | nvd0_dmaeng_oclass = &(struct nvkm_dmaeng_impl) { |
| 104 | .base.handle = NV_ENGINE(DMAOBJ, 0xd0), |
| 105 | .base.ofuncs = &(struct nouveau_ofuncs) { |
| 106 | .ctor = _nvkm_dmaeng_ctor, |
| 107 | .dtor = _nvkm_dmaeng_dtor, |
| 108 | .init = _nvkm_dmaeng_init, |
| 109 | .fini = _nvkm_dmaeng_fini, |
Ben Skeggs | 344e107 | 2012-10-08 14:11:35 +1000 | [diff] [blame] | 110 | }, |
Ben Skeggs | bc98540 | 2014-08-10 04:10:24 +1000 | [diff] [blame^] | 111 | .bind = nvd0_dmaobj_bind, |
| 112 | }.base; |