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gerrit-public.fairphone.software / kernel / msm-4.9 / bca4a87f0131fa7fa3a81cf3e4bc4780da58f768 / . / drivers / clk / qcom / debugcc-sdm845.c
blob: 44c5b81869ad1e3b1b649f1f3310d7bd14eb090d [file] [log] [blame]
Deepak Katragaddac617c382017-02-28 11:06:06 -0800[diff] [blame]1/*
2 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/err.h>
16#include <linux/platform_device.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
20#include <linux/clk.h>
21#include <linux/clk-provider.h>
22#include <linux/regmap.h>
23#include <linux/mfd/syscon.h>
24
25#include "clk-debug.h"
26
27static struct measure_clk_data debug_mux_priv = {
28 .ctl_reg = 0x62024,
29 .status_reg = 0x62028,
30 .xo_div4_cbcr = 0x43008,
31};
32
33static const char *const debug_mux_parent_names[] = {
34 "cam_cc_bps_ahb_clk",
35 "cam_cc_bps_areg_clk",
36 "cam_cc_bps_axi_clk",
37 "cam_cc_bps_clk",
38 "cam_cc_camnoc_atb_clk",
39 "cam_cc_camnoc_axi_clk",
40 "cam_cc_cci_clk",
41 "cam_cc_cpas_ahb_clk",
42 "cam_cc_csi0phytimer_clk",
43 "cam_cc_csi1phytimer_clk",
44 "cam_cc_csi2phytimer_clk",
45 "cam_cc_csiphy0_clk",
46 "cam_cc_csiphy1_clk",
47 "cam_cc_csiphy2_clk",
48 "cam_cc_fd_core_clk",
49 "cam_cc_fd_core_uar_clk",
50 "cam_cc_icp_apb_clk",
51 "cam_cc_icp_atb_clk",
52 "cam_cc_icp_clk",
53 "cam_cc_icp_cti_clk",
54 "cam_cc_icp_ts_clk",
55 "cam_cc_ife_0_axi_clk",
56 "cam_cc_ife_0_clk",
57 "cam_cc_ife_0_cphy_rx_clk",
58 "cam_cc_ife_0_csid_clk",
59 "cam_cc_ife_0_dsp_clk",
60 "cam_cc_ife_1_axi_clk",
61 "cam_cc_ife_1_clk",
62 "cam_cc_ife_1_cphy_rx_clk",
63 "cam_cc_ife_1_csid_clk",
64 "cam_cc_ife_1_dsp_clk",
65 "cam_cc_ife_lite_clk",
66 "cam_cc_ife_lite_cphy_rx_clk",
67 "cam_cc_ife_lite_csid_clk",
68 "cam_cc_ipe_0_ahb_clk",
69 "cam_cc_ipe_0_areg_clk",
70 "cam_cc_ipe_0_axi_clk",
71 "cam_cc_ipe_0_clk",
72 "cam_cc_ipe_1_ahb_clk",
73 "cam_cc_ipe_1_areg_clk",
74 "cam_cc_ipe_1_axi_clk",
75 "cam_cc_ipe_1_clk",
76 "cam_cc_jpeg_clk",
77 "cam_cc_lrme_clk",
78 "cam_cc_mclk0_clk",
79 "cam_cc_mclk1_clk",
80 "cam_cc_mclk2_clk",
81 "cam_cc_mclk3_clk",
82 "cam_cc_soc_ahb_clk",
83 "cam_cc_sys_tmr_clk",
84 "disp_cc_mdss_ahb_clk",
85 "disp_cc_mdss_axi_clk",
86 "disp_cc_mdss_byte0_clk",
87 "disp_cc_mdss_byte0_intf_clk",
88 "disp_cc_mdss_byte1_clk",
89 "disp_cc_mdss_byte1_intf_clk",
90 "disp_cc_mdss_dp_aux_clk",
91 "disp_cc_mdss_dp_crypto_clk",
92 "disp_cc_mdss_dp_link_clk",
93 "disp_cc_mdss_dp_link_intf_clk",
94 "disp_cc_mdss_dp_pixel1_clk",
95 "disp_cc_mdss_dp_pixel_clk",
96 "disp_cc_mdss_esc0_clk",
97 "disp_cc_mdss_esc1_clk",
98 "disp_cc_mdss_mdp_clk",
99 "disp_cc_mdss_mdp_lut_clk",
100 "disp_cc_mdss_pclk0_clk",
101 "disp_cc_mdss_pclk1_clk",
102 "disp_cc_mdss_qdss_at_clk",
103 "disp_cc_mdss_qdss_tsctr_div8_clk",
104 "disp_cc_mdss_rot_clk",
105 "disp_cc_mdss_rscc_ahb_clk",
106 "disp_cc_mdss_rscc_vsync_clk",
107 "disp_cc_mdss_spdm_debug_clk",
108 "disp_cc_mdss_spdm_dp_crypto_clk",
109 "disp_cc_mdss_spdm_dp_pixel1_clk",
110 "disp_cc_mdss_spdm_dp_pixel_clk",
111 "disp_cc_mdss_spdm_mdp_clk",
112 "disp_cc_mdss_spdm_pclk0_clk",
113 "disp_cc_mdss_spdm_pclk1_clk",
114 "disp_cc_mdss_spdm_rot_clk",
115 "disp_cc_mdss_vsync_clk",
Deepak Katragaddad075ba32017-04-06 13:45:47 -0700[diff] [blame]116 "measure_only_snoc_clk",
117 "measure_only_cnoc_clk",
118 "measure_only_bimc_clk",
119 "measure_only_ipa_2x_clk",
Deepak Katragaddac617c382017-02-28 11:06:06 -0800[diff] [blame]120 "gcc_aggre_noc_pcie_tbu_clk",
121 "gcc_aggre_ufs_card_axi_clk",
122 "gcc_aggre_ufs_phy_axi_clk",
123 "gcc_aggre_usb3_prim_axi_clk",
124 "gcc_aggre_usb3_sec_axi_clk",
125 "gcc_boot_rom_ahb_clk",
126 "gcc_camera_ahb_clk",
127 "gcc_camera_axi_clk",
128 "gcc_camera_xo_clk",
129 "gcc_ce1_ahb_clk",
130 "gcc_ce1_axi_clk",
131 "gcc_ce1_clk",
132 "gcc_cfg_noc_usb3_prim_axi_clk",
133 "gcc_cfg_noc_usb3_sec_axi_clk",
134 "gcc_cpuss_ahb_clk",
135 "gcc_cpuss_dvm_bus_clk",
136 "gcc_cpuss_gnoc_clk",
137 "gcc_cpuss_rbcpr_clk",
138 "gcc_ddrss_gpu_axi_clk",
139 "gcc_disp_ahb_clk",
140 "gcc_disp_axi_clk",
141 "gcc_disp_gpll0_clk_src",
142 "gcc_disp_gpll0_div_clk_src",
143 "gcc_disp_xo_clk",
144 "gcc_gp1_clk",
145 "gcc_gp2_clk",
146 "gcc_gp3_clk",
147 "gcc_gpu_cfg_ahb_clk",
148 "gcc_gpu_gpll0_clk_src",
149 "gcc_gpu_gpll0_div_clk_src",
150 "gcc_gpu_memnoc_gfx_clk",
151 "gcc_gpu_snoc_dvm_gfx_clk",
152 "gcc_mss_axis2_clk",
153 "gcc_mss_cfg_ahb_clk",
154 "gcc_mss_gpll0_div_clk_src",
155 "gcc_mss_mfab_axis_clk",
156 "gcc_mss_q6_memnoc_axi_clk",
157 "gcc_mss_snoc_axi_clk",
158 "gcc_pcie_0_aux_clk",
159 "gcc_pcie_0_cfg_ahb_clk",
160 "gcc_pcie_0_mstr_axi_clk",
161 "gcc_pcie_0_pipe_clk",
162 "gcc_pcie_0_slv_axi_clk",
163 "gcc_pcie_0_slv_q2a_axi_clk",
164 "gcc_pcie_1_aux_clk",
165 "gcc_pcie_1_cfg_ahb_clk",
166 "gcc_pcie_1_mstr_axi_clk",
167 "gcc_pcie_1_pipe_clk",
168 "gcc_pcie_1_slv_axi_clk",
169 "gcc_pcie_1_slv_q2a_axi_clk",
170 "gcc_pcie_phy_aux_clk",
171 "gcc_pcie_phy_refgen_clk",
172 "gcc_pdm2_clk",
173 "gcc_pdm_ahb_clk",
174 "gcc_pdm_xo4_clk",
175 "gcc_prng_ahb_clk",
176 "gcc_qmip_camera_ahb_clk",
177 "gcc_qmip_disp_ahb_clk",
178 "gcc_qmip_video_ahb_clk",
179 "gcc_qupv3_wrap0_core_2x_clk",
180 "gcc_qupv3_wrap0_core_clk",
181 "gcc_qupv3_wrap0_s0_clk",
182 "gcc_qupv3_wrap0_s1_clk",
183 "gcc_qupv3_wrap0_s2_clk",
184 "gcc_qupv3_wrap0_s3_clk",
185 "gcc_qupv3_wrap0_s4_clk",
186 "gcc_qupv3_wrap0_s5_clk",
187 "gcc_qupv3_wrap0_s6_clk",
188 "gcc_qupv3_wrap0_s7_clk",
189 "gcc_qupv3_wrap1_core_2x_clk",
190 "gcc_qupv3_wrap1_core_clk",
191 "gcc_qupv3_wrap1_s0_clk",
192 "gcc_qupv3_wrap1_s1_clk",
193 "gcc_qupv3_wrap1_s2_clk",
194 "gcc_qupv3_wrap1_s3_clk",
195 "gcc_qupv3_wrap1_s4_clk",
196 "gcc_qupv3_wrap1_s5_clk",
197 "gcc_qupv3_wrap1_s6_clk",
198 "gcc_qupv3_wrap1_s7_clk",
199 "gcc_qupv3_wrap_0_m_ahb_clk",
200 "gcc_qupv3_wrap_0_s_ahb_clk",
201 "gcc_qupv3_wrap_1_m_ahb_clk",
202 "gcc_qupv3_wrap_1_s_ahb_clk",
203 "gcc_sdcc2_ahb_clk",
204 "gcc_sdcc2_apps_clk",
205 "gcc_sdcc4_ahb_clk",
206 "gcc_sdcc4_apps_clk",
207 "gcc_sys_noc_cpuss_ahb_clk",
208 "gcc_tsif_ahb_clk",
209 "gcc_tsif_inactivity_timers_clk",
210 "gcc_tsif_ref_clk",
211 "gcc_ufs_card_ahb_clk",
212 "gcc_ufs_card_axi_clk",
213 "gcc_ufs_card_ice_core_clk",
214 "gcc_ufs_card_phy_aux_clk",
215 "gcc_ufs_card_rx_symbol_0_clk",
216 "gcc_ufs_card_rx_symbol_1_clk",
217 "gcc_ufs_card_tx_symbol_0_clk",
218 "gcc_ufs_card_unipro_core_clk",
219 "gcc_ufs_phy_ahb_clk",
220 "gcc_ufs_phy_axi_clk",
221 "gcc_ufs_phy_ice_core_clk",
222 "gcc_ufs_phy_phy_aux_clk",
223 "gcc_ufs_phy_rx_symbol_0_clk",
224 "gcc_ufs_phy_rx_symbol_1_clk",
225 "gcc_ufs_phy_tx_symbol_0_clk",
226 "gcc_ufs_phy_unipro_core_clk",
227 "gcc_usb30_prim_master_clk",
228 "gcc_usb30_prim_mock_utmi_clk",
229 "gcc_usb30_prim_sleep_clk",
230 "gcc_usb30_sec_master_clk",
231 "gcc_usb30_sec_mock_utmi_clk",
232 "gcc_usb30_sec_sleep_clk",
233 "gcc_usb3_prim_phy_aux_clk",
234 "gcc_usb3_prim_phy_com_aux_clk",
235 "gcc_usb3_prim_phy_pipe_clk",
236 "gcc_usb3_sec_phy_aux_clk",
237 "gcc_usb3_sec_phy_com_aux_clk",
238 "gcc_usb3_sec_phy_pipe_clk",
239 "gcc_usb_phy_cfg_ahb2phy_clk",
240 "gcc_video_ahb_clk",
241 "gcc_video_axi_clk",
242 "gcc_video_xo_clk",
243 "gpu_cc_acd_cxo_clk",
244 "gpu_cc_ahb_clk",
245 "gpu_cc_crc_ahb_clk",
246 "gpu_cc_cx_apb_clk",
247 "gpu_cc_cx_gfx3d_clk",
248 "gpu_cc_cx_gfx3d_slv_clk",
249 "gpu_cc_cx_gmu_clk",
250 "gpu_cc_cx_qdss_at_clk",
251 "gpu_cc_cx_qdss_trig_clk",
252 "gpu_cc_cx_qdss_tsctr_clk",
253 "gpu_cc_cx_snoc_dvm_clk",
254 "gpu_cc_cxo_aon_clk",
255 "gpu_cc_cxo_clk",
256 "gpu_cc_gx_cxo_clk",
257 "gpu_cc_gx_gmu_clk",
258 "gpu_cc_gx_qdss_tsctr_clk",
259 "gpu_cc_gx_vsense_clk",
260 "gpu_cc_rbcpr_ahb_clk",
261 "gpu_cc_rbcpr_clk",
262 "gpu_cc_sleep_clk",
263 "gpu_cc_spdm_gx_gfx3d_div_clk",
264 "video_cc_apb_clk",
265 "video_cc_at_clk",
266 "video_cc_qdss_trig_clk",
267 "video_cc_qdss_tsctr_div8_clk",
268 "video_cc_vcodec0_axi_clk",
269 "video_cc_vcodec0_core_clk",
270 "video_cc_vcodec1_axi_clk",
271 "video_cc_vcodec1_core_clk",
272 "video_cc_venus_ahb_clk",
273 "video_cc_venus_ctl_axi_clk",
274 "video_cc_venus_ctl_core_clk",
Deepak Katragaddabca4a872017-04-24 15:51:03 -0700[diff] [blame^]275 "l3_clk",
276 "pwrcl_clk",
277 "perfcl_clk",
Deepak Katragaddac617c382017-02-28 11:06:06 -0800[diff] [blame]278};
279
280static struct clk_debug_mux gcc_debug_mux = {
281 .priv = &debug_mux_priv,
282 .debug_offset = 0x62008,
283 .post_div_offset = 0x62000,
284 .cbcr_offset = 0x62004,
285 .src_sel_mask = 0x3FF,
286 .src_sel_shift = 0,
287 .post_div_mask = 0xF,
288 .post_div_shift = 0,
289 MUX_SRC_LIST(
290 { "cam_cc_bps_ahb_clk", 0x46, 4, CAM_CC,
291 0xE, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
292 { "cam_cc_bps_areg_clk", 0x46, 4, CAM_CC,
293 0xD, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
294 { "cam_cc_bps_axi_clk", 0x46, 4, CAM_CC,
295 0xC, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
296 { "cam_cc_bps_clk", 0x46, 4, CAM_CC,
297 0xB, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
298 { "cam_cc_camnoc_atb_clk", 0x46, 4, CAM_CC,
299 0x34, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
300 { "cam_cc_camnoc_axi_clk", 0x46, 4, CAM_CC,
301 0x2D, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
302 { "cam_cc_cci_clk", 0x46, 4, CAM_CC,
303 0x2A, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
304 { "cam_cc_cpas_ahb_clk", 0x46, 4, CAM_CC,
305 0x2C, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
306 { "cam_cc_csi0phytimer_clk", 0x46, 4, CAM_CC,
307 0x5, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
308 { "cam_cc_csi1phytimer_clk", 0x46, 4, CAM_CC,
309 0x7, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
310 { "cam_cc_csi2phytimer_clk", 0x46, 4, CAM_CC,
311 0x9, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
312 { "cam_cc_csiphy0_clk", 0x46, 4, CAM_CC,
313 0x6, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
314 { "cam_cc_csiphy1_clk", 0x46, 4, CAM_CC,
315 0x8, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
316 { "cam_cc_csiphy2_clk", 0x46, 4, CAM_CC,
317 0xA, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
318 { "cam_cc_fd_core_clk", 0x46, 4, CAM_CC,
319 0x28, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
320 { "cam_cc_fd_core_uar_clk", 0x46, 4, CAM_CC,
321 0x29, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
322 { "cam_cc_icp_apb_clk", 0x46, 4, CAM_CC,
323 0x32, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
324 { "cam_cc_icp_atb_clk", 0x46, 4, CAM_CC,
325 0x2F, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
326 { "cam_cc_icp_clk", 0x46, 4, CAM_CC,
327 0x26, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
328 { "cam_cc_icp_cti_clk", 0x46, 4, CAM_CC,
329 0x30, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
330 { "cam_cc_icp_ts_clk", 0x46, 4, CAM_CC,
331 0x31, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
332 { "cam_cc_ife_0_axi_clk", 0x46, 4, CAM_CC,
333 0x1B, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
334 { "cam_cc_ife_0_clk", 0x46, 4, CAM_CC,
335 0x17, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
336 { "cam_cc_ife_0_cphy_rx_clk", 0x46, 4, CAM_CC,
337 0x1A, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
338 { "cam_cc_ife_0_csid_clk", 0x46, 4, CAM_CC,
339 0x19, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
340 { "cam_cc_ife_0_dsp_clk", 0x46, 4, CAM_CC,
341 0x18, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
342 { "cam_cc_ife_1_axi_clk", 0x46, 4, CAM_CC,
343 0x21, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
344 { "cam_cc_ife_1_clk", 0x46, 4, CAM_CC,
345 0x1D, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
346 { "cam_cc_ife_1_cphy_rx_clk", 0x46, 4, CAM_CC,
347 0x20, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
348 { "cam_cc_ife_1_csid_clk", 0x46, 4, CAM_CC,
349 0x1F, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
350 { "cam_cc_ife_1_dsp_clk", 0x46, 4, CAM_CC,
351 0x1E, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
352 { "cam_cc_ife_lite_clk", 0x46, 4, CAM_CC,
353 0x22, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
354 { "cam_cc_ife_lite_cphy_rx_clk", 0x46, 4, CAM_CC,
355 0x24, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
356 { "cam_cc_ife_lite_csid_clk", 0x46, 4, CAM_CC,
357 0x23, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
358 { "cam_cc_ipe_0_ahb_clk", 0x46, 4, CAM_CC,
359 0x12, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
360 { "cam_cc_ipe_0_areg_clk", 0x46, 4, CAM_CC,
361 0x11, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
362 { "cam_cc_ipe_0_axi_clk", 0x46, 4, CAM_CC,
363 0x10, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
364 { "cam_cc_ipe_0_clk", 0x46, 4, CAM_CC,
365 0xF, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
366 { "cam_cc_ipe_1_ahb_clk", 0x46, 4, CAM_CC,
367 0x16, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
368 { "cam_cc_ipe_1_areg_clk", 0x46, 4, CAM_CC,
369 0x15, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
370 { "cam_cc_ipe_1_axi_clk", 0x46, 4, CAM_CC,
371 0x14, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
372 { "cam_cc_ipe_1_clk", 0x46, 4, CAM_CC,
373 0x13, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
374 { "cam_cc_jpeg_clk", 0x46, 4, CAM_CC,
375 0x25, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
376 { "cam_cc_lrme_clk", 0x46, 4, CAM_CC,
377 0x2B, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
378 { "cam_cc_mclk0_clk", 0x46, 4, CAM_CC,
379 0x1, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
380 { "cam_cc_mclk1_clk", 0x46, 4, CAM_CC,
381 0x2, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
382 { "cam_cc_mclk2_clk", 0x46, 4, CAM_CC,
383 0x3, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
384 { "cam_cc_mclk3_clk", 0x46, 4, CAM_CC,
385 0x4, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
386 { "cam_cc_soc_ahb_clk", 0x46, 4, CAM_CC,
387 0x2E, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
388 { "cam_cc_sys_tmr_clk", 0x46, 4, CAM_CC,
389 0x33, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 },
390 { "disp_cc_mdss_ahb_clk", 0x47, 4, DISP_CC,
391 0x13, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
392 { "disp_cc_mdss_axi_clk", 0x47, 4, DISP_CC,
393 0x14, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
394 { "disp_cc_mdss_byte0_clk", 0x47, 4, DISP_CC,
395 0x7, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
396 { "disp_cc_mdss_byte0_intf_clk", 0x47, 4, DISP_CC,
397 0x8, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
398 { "disp_cc_mdss_byte1_clk", 0x47, 4, DISP_CC,
399 0x9, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
400 { "disp_cc_mdss_byte1_intf_clk", 0x47, 4, DISP_CC,
401 0xA, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
402 { "disp_cc_mdss_dp_aux_clk", 0x47, 4, DISP_CC,
403 0x12, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
404 { "disp_cc_mdss_dp_crypto_clk", 0x47, 4, DISP_CC,
405 0xF, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
406 { "disp_cc_mdss_dp_link_clk", 0x47, 4, DISP_CC,
407 0xD, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
408 { "disp_cc_mdss_dp_link_intf_clk", 0x47, 4, DISP_CC,
409 0xE, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
410 { "disp_cc_mdss_dp_pixel1_clk", 0x47, 4, DISP_CC,
411 0x11, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
412 { "disp_cc_mdss_dp_pixel_clk", 0x47, 4, DISP_CC,
413 0x10, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
414 { "disp_cc_mdss_esc0_clk", 0x47, 4, DISP_CC,
415 0xB, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
416 { "disp_cc_mdss_esc1_clk", 0x47, 4, DISP_CC,
417 0xC, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
418 { "disp_cc_mdss_mdp_clk", 0x47, 4, DISP_CC,
419 0x3, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
420 { "disp_cc_mdss_mdp_lut_clk", 0x47, 4, DISP_CC,
421 0x5, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
422 { "disp_cc_mdss_pclk0_clk", 0x47, 4, DISP_CC,
423 0x1, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
424 { "disp_cc_mdss_pclk1_clk", 0x47, 4, DISP_CC,
425 0x2, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
426 { "disp_cc_mdss_qdss_at_clk", 0x47, 4, DISP_CC,
427 0x15, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
428 { "disp_cc_mdss_qdss_tsctr_div8_clk", 0x47, 4, DISP_CC,
429 0x16, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
430 { "disp_cc_mdss_rot_clk", 0x47, 4, DISP_CC,
431 0x4, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
432 { "disp_cc_mdss_rscc_ahb_clk", 0x47, 4, DISP_CC,
433 0x17, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
434 { "disp_cc_mdss_rscc_vsync_clk", 0x47, 4, DISP_CC,
435 0x18, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
436 { "disp_cc_mdss_spdm_debug_clk", 0x47, 4, DISP_CC,
437 0x20, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
438 { "disp_cc_mdss_spdm_dp_crypto_clk", 0x47, 4, DISP_CC,
439 0x1D, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
440 { "disp_cc_mdss_spdm_dp_pixel1_clk", 0x47, 4, DISP_CC,
441 0x1F, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
442 { "disp_cc_mdss_spdm_dp_pixel_clk", 0x47, 4, DISP_CC,
443 0x1E, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
444 { "disp_cc_mdss_spdm_mdp_clk", 0x47, 4, DISP_CC,
445 0x1B, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
446 { "disp_cc_mdss_spdm_pclk0_clk", 0x47, 4, DISP_CC,
447 0x19, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
448 { "disp_cc_mdss_spdm_pclk1_clk", 0x47, 4, DISP_CC,
449 0x1A, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
450 { "disp_cc_mdss_spdm_rot_clk", 0x47, 4, DISP_CC,
451 0x1C, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
452 { "disp_cc_mdss_vsync_clk", 0x47, 4, DISP_CC,
453 0x6, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C },
Deepak Katragaddad075ba32017-04-06 13:45:47 -0700[diff] [blame]454 { "measure_only_snoc_clk", 0x7, 4, GCC,
455 0x7, 0x3FFF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
456 { "measure_only_cnoc_clk", 0x15, 4, GCC,
457 0x7, 0x3FFF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
458 { "measure_only_bimc_clk", 0xc2, 4, GCC,
459 0x7, 0x3FFF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
460 { "measure_only_ipa_2x_clk", 0x128, 4, GCC,
461 0x7, 0x3FFF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
Deepak Katragaddac617c382017-02-28 11:06:06 -0800[diff] [blame]462 { "gcc_aggre_noc_pcie_tbu_clk", 0x2D, 4, GCC,
463 0x2D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
464 { "gcc_aggre_ufs_card_axi_clk", 0x11E, 4, GCC,
465 0x11E, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
466 { "gcc_aggre_ufs_phy_axi_clk", 0x11D, 4, GCC,
467 0x11D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
468 { "gcc_aggre_usb3_prim_axi_clk", 0x11B, 4, GCC,
469 0x11B, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
470 { "gcc_aggre_usb3_sec_axi_clk", 0x11C, 4, GCC,
471 0x11C, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
472 { "gcc_boot_rom_ahb_clk", 0x94, 4, GCC,
473 0x94, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
474 { "gcc_camera_ahb_clk", 0x3A, 4, GCC,
475 0x3A, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
476 { "gcc_camera_axi_clk", 0x40, 4, GCC,
477 0x40, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
478 { "gcc_camera_xo_clk", 0x43, 4, GCC,
479 0x43, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
480 { "gcc_ce1_ahb_clk", 0xA9, 4, GCC,
481 0xA9, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
482 { "gcc_ce1_axi_clk", 0xA8, 4, GCC,
483 0xA8, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
484 { "gcc_ce1_clk", 0xA7, 4, GCC,
485 0xA7, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
486 { "gcc_cfg_noc_usb3_prim_axi_clk", 0x1D, 4, GCC,
487 0x1D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
488 { "gcc_cfg_noc_usb3_sec_axi_clk", 0x1E, 4, GCC,
489 0x1E, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
490 { "gcc_cpuss_ahb_clk", 0xCE, 4, GCC,
491 0xCE, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
492 { "gcc_cpuss_dvm_bus_clk", 0xD3, 4, GCC,
493 0xD3, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
494 { "gcc_cpuss_gnoc_clk", 0xCF, 4, GCC,
495 0xCF, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
496 { "gcc_cpuss_rbcpr_clk", 0xD0, 4, GCC,
497 0xD0, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
498 { "gcc_ddrss_gpu_axi_clk", 0xBB, 4, GCC,
499 0xBB, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
500 { "gcc_disp_ahb_clk", 0x3B, 4, GCC,
501 0x3B, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
502 { "gcc_disp_axi_clk", 0x41, 4, GCC,
503 0x41, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
504 { "gcc_disp_gpll0_clk_src", 0x4C, 4, GCC,
505 0x4C, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
506 { "gcc_disp_gpll0_div_clk_src", 0x4D, 4, GCC,
507 0x4D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
508 { "gcc_disp_xo_clk", 0x44, 4, GCC,
509 0x44, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
510 { "gcc_gp1_clk", 0xDE, 4, GCC,
511 0xDE, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
512 { "gcc_gp2_clk", 0xDF, 4, GCC,
513 0xDF, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
514 { "gcc_gp3_clk", 0xE0, 4, GCC,
515 0xE0, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
516 { "gcc_gpu_cfg_ahb_clk", 0x142, 4, GCC,
517 0x142, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
518 { "gcc_gpu_gpll0_clk_src", 0x148, 4, GCC,
519 0x148, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
520 { "gcc_gpu_gpll0_div_clk_src", 0x149, 4, GCC,
521 0x149, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
522 { "gcc_gpu_memnoc_gfx_clk", 0x145, 4, GCC,
523 0x145, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
524 { "gcc_gpu_snoc_dvm_gfx_clk", 0x147, 4, GCC,
525 0x147, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
526 { "gcc_mss_axis2_clk", 0x12F, 4, GCC,
527 0x12F, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
528 { "gcc_mss_cfg_ahb_clk", 0x12D, 4, GCC,
529 0x12D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
530 { "gcc_mss_gpll0_div_clk_src", 0x133, 4, GCC,
531 0x133, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
532 { "gcc_mss_mfab_axis_clk", 0x12E, 4, GCC,
533 0x12E, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
534 { "gcc_mss_q6_memnoc_axi_clk", 0x135, 4, GCC,
535 0x135, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
536 { "gcc_mss_snoc_axi_clk", 0x134, 4, GCC,
537 0x134, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
538 { "gcc_pcie_0_aux_clk", 0xE5, 4, GCC,
539 0xE5, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
540 { "gcc_pcie_0_cfg_ahb_clk", 0xE4, 4, GCC,
541 0xE4, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
542 { "gcc_pcie_0_mstr_axi_clk", 0xE3, 4, GCC,
543 0xE3, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
544 { "gcc_pcie_0_pipe_clk", 0xE6, 4, GCC,
545 0xE6, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
546 { "gcc_pcie_0_slv_axi_clk", 0xE2, 4, GCC,
547 0xE2, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
548 { "gcc_pcie_0_slv_q2a_axi_clk", 0xE1, 4, GCC,
549 0xE1, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
550 { "gcc_pcie_1_aux_clk", 0xEC, 4, GCC,
551 0xEC, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
552 { "gcc_pcie_1_cfg_ahb_clk", 0xEB, 4, GCC,
553 0xEB, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
554 { "gcc_pcie_1_mstr_axi_clk", 0xEA, 4, GCC,
555 0xEA, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
556 { "gcc_pcie_1_pipe_clk", 0xED, 4, GCC,
557 0xED, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
558 { "gcc_pcie_1_slv_axi_clk", 0xE9, 4, GCC,
559 0xE9, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
560 { "gcc_pcie_1_slv_q2a_axi_clk", 0xE8, 4, GCC,
561 0xE8, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
562 { "gcc_pcie_phy_aux_clk", 0xEF, 4, GCC,
563 0xEF, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
564 { "gcc_pcie_phy_refgen_clk", 0x160, 4, GCC,
565 0x160, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
566 { "gcc_pdm2_clk", 0x8E, 4, GCC,
567 0x8E, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
568 { "gcc_pdm_ahb_clk", 0x8C, 4, GCC,
569 0x8C, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
570 { "gcc_pdm_xo4_clk", 0x8D, 4, GCC,
571 0x8D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
572 { "gcc_prng_ahb_clk", 0x8F, 4, GCC,
573 0x8F, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
574 { "gcc_qmip_camera_ahb_clk", 0x3D, 4, GCC,
575 0x3D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
576 { "gcc_qmip_disp_ahb_clk", 0x3E, 4, GCC,
577 0x3E, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
578 { "gcc_qmip_video_ahb_clk", 0x3C, 4, GCC,
579 0x3C, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
580 { "gcc_qupv3_wrap0_core_2x_clk", 0x77, 4, GCC,
581 0x77, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
582 { "gcc_qupv3_wrap0_core_clk", 0x76, 4, GCC,
583 0x76, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
584 { "gcc_qupv3_wrap0_s0_clk", 0x78, 4, GCC,
585 0x78, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
586 { "gcc_qupv3_wrap0_s1_clk", 0x79, 4, GCC,
587 0x79, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
588 { "gcc_qupv3_wrap0_s2_clk", 0x7A, 4, GCC,
589 0x7A, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
590 { "gcc_qupv3_wrap0_s3_clk", 0x7B, 4, GCC,
591 0x7B, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
592 { "gcc_qupv3_wrap0_s4_clk", 0x7C, 4, GCC,
593 0x7C, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
594 { "gcc_qupv3_wrap0_s5_clk", 0x7D, 4, GCC,
595 0x7D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
596 { "gcc_qupv3_wrap0_s6_clk", 0x7E, 4, GCC,
597 0x7E, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
598 { "gcc_qupv3_wrap0_s7_clk", 0x7F, 4, GCC,
599 0x7F, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
600 { "gcc_qupv3_wrap1_core_2x_clk", 0x80, 4, GCC,
601 0x80, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
602 { "gcc_qupv3_wrap1_core_clk", 0x81, 4, GCC,
603 0x81, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
604 { "gcc_qupv3_wrap1_s0_clk", 0x84, 4, GCC,
605 0x84, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
606 { "gcc_qupv3_wrap1_s1_clk", 0x85, 4, GCC,
607 0x85, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
608 { "gcc_qupv3_wrap1_s2_clk", 0x86, 4, GCC,
609 0x86, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
610 { "gcc_qupv3_wrap1_s3_clk", 0x87, 4, GCC,
611 0x87, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
612 { "gcc_qupv3_wrap1_s4_clk", 0x88, 4, GCC,
613 0x88, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
614 { "gcc_qupv3_wrap1_s5_clk", 0x89, 4, GCC,
615 0x89, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
616 { "gcc_qupv3_wrap1_s6_clk", 0x8A, 4, GCC,
617 0x8A, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
618 { "gcc_qupv3_wrap1_s7_clk", 0x8B, 4, GCC,
619 0x8B, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
620 { "gcc_qupv3_wrap_0_m_ahb_clk", 0x74, 4, GCC,
621 0x74, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
622 { "gcc_qupv3_wrap_0_s_ahb_clk", 0x75, 4, GCC,
623 0x75, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
624 { "gcc_qupv3_wrap_1_m_ahb_clk", 0x82, 4, GCC,
625 0x82, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
626 { "gcc_qupv3_wrap_1_s_ahb_clk", 0x83, 4, GCC,
627 0x83, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
628 { "gcc_sdcc2_ahb_clk", 0x71, 4, GCC,
629 0x71, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
630 { "gcc_sdcc2_apps_clk", 0x70, 4, GCC,
631 0x70, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
632 { "gcc_sdcc4_ahb_clk", 0x73, 4, GCC,
633 0x73, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
634 { "gcc_sdcc4_apps_clk", 0x72, 4, GCC,
635 0x72, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
636 { "gcc_sys_noc_cpuss_ahb_clk", 0xC, 4, GCC,
637 0xC, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
638 { "gcc_tsif_ahb_clk", 0x90, 4, GCC,
639 0x90, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
640 { "gcc_tsif_inactivity_timers_clk", 0x92, 4, GCC,
641 0x92, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
642 { "gcc_tsif_ref_clk", 0x91, 4, GCC,
643 0x91, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
644 { "gcc_ufs_card_ahb_clk", 0xF1, 4, GCC,
645 0xF1, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
646 { "gcc_ufs_card_axi_clk", 0xF0, 4, GCC,
647 0xF0, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
648 { "gcc_ufs_card_ice_core_clk", 0xF7, 4, GCC,
649 0xF7, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
650 { "gcc_ufs_card_phy_aux_clk", 0xF8, 4, GCC,
651 0xF8, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
652 { "gcc_ufs_card_rx_symbol_0_clk", 0xF3, 4, GCC,
653 0xF3, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
654 { "gcc_ufs_card_rx_symbol_1_clk", 0xF9, 4, GCC,
655 0xF9, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
656 { "gcc_ufs_card_tx_symbol_0_clk", 0xF2, 4, GCC,
657 0xF2, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
658 { "gcc_ufs_card_unipro_core_clk", 0xF6, 4, GCC,
659 0xF6, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
660 { "gcc_ufs_phy_ahb_clk", 0xFC, 4, GCC,
661 0xFC, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
662 { "gcc_ufs_phy_axi_clk", 0xFB, 4, GCC,
663 0xFB, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
664 { "gcc_ufs_phy_ice_core_clk", 0x102, 4, GCC,
665 0x102, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
666 { "gcc_ufs_phy_phy_aux_clk", 0x103, 4, GCC,
667 0x103, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
668 { "gcc_ufs_phy_rx_symbol_0_clk", 0xFE, 4, GCC,
669 0xFE, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
670 { "gcc_ufs_phy_rx_symbol_1_clk", 0x104, 4, GCC,
671 0x104, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
672 { "gcc_ufs_phy_tx_symbol_0_clk", 0xFD, 4, GCC,
673 0xFD, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
674 { "gcc_ufs_phy_unipro_core_clk", 0x101, 4, GCC,
675 0x101, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
676 { "gcc_usb30_prim_master_clk", 0x5F, 4, GCC,
677 0x5F, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
678 { "gcc_usb30_prim_mock_utmi_clk", 0x61, 4, GCC,
679 0x61, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
680 { "gcc_usb30_prim_sleep_clk", 0x60, 4, GCC,
681 0x60, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
682 { "gcc_usb30_sec_master_clk", 0x65, 4, GCC,
683 0x65, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
684 { "gcc_usb30_sec_mock_utmi_clk", 0x67, 4, GCC,
685 0x67, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
686 { "gcc_usb30_sec_sleep_clk", 0x66, 4, GCC,
687 0x66, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
688 { "gcc_usb3_prim_phy_aux_clk", 0x62, 4, GCC,
689 0x62, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
690 { "gcc_usb3_prim_phy_com_aux_clk", 0x63, 4, GCC,
691 0x63, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
692 { "gcc_usb3_prim_phy_pipe_clk", 0x64, 4, GCC,
693 0x64, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
694 { "gcc_usb3_sec_phy_aux_clk", 0x68, 4, GCC,
695 0x68, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
696 { "gcc_usb3_sec_phy_com_aux_clk", 0x69, 4, GCC,
697 0x69, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
698 { "gcc_usb3_sec_phy_pipe_clk", 0x6A, 4, GCC,
699 0x6A, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
700 { "gcc_usb_phy_cfg_ahb2phy_clk", 0x6F, 4, GCC,
701 0x6F, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
702 { "gcc_video_ahb_clk", 0x39, 4, GCC,
703 0x39, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
704 { "gcc_video_axi_clk", 0x3F, 4, GCC,
705 0x3F, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
706 { "gcc_video_xo_clk", 0x42, 4, GCC,
707 0x42, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },
708 { "gpu_cc_acd_cxo_clk", 0x144, 4, GPU_CC,
709 0x1F, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
710 { "gpu_cc_ahb_clk", 0x144, 4, GPU_CC,
711 0x11, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
712 { "gpu_cc_crc_ahb_clk", 0x144, 4, GPU_CC,
713 0x12, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
714 { "gpu_cc_cx_apb_clk", 0x144, 4, GPU_CC,
715 0x15, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
716 { "gpu_cc_cx_gfx3d_clk", 0x144, 4, GPU_CC,
717 0x1A, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
718 { "gpu_cc_cx_gfx3d_slv_clk", 0x144, 4, GPU_CC,
719 0x1B, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
720 { "gpu_cc_cx_gmu_clk", 0x144, 4, GPU_CC,
721 0x19, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
722 { "gpu_cc_cx_qdss_at_clk", 0x144, 4, GPU_CC,
723 0x13, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
724 { "gpu_cc_cx_qdss_trig_clk", 0x144, 4, GPU_CC,
725 0x18, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
726 { "gpu_cc_cx_qdss_tsctr_clk", 0x144, 4, GPU_CC,
727 0x14, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
728 { "gpu_cc_cx_snoc_dvm_clk", 0x144, 4, GPU_CC,
729 0x16, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
730 { "gpu_cc_cxo_aon_clk", 0x144, 4, GPU_CC,
731 0xB, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
732 { "gpu_cc_cxo_clk", 0x144, 4, GPU_CC,
733 0xA, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
734 { "gpu_cc_gx_cxo_clk", 0x144, 4, GPU_CC,
735 0xF, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
736 { "gpu_cc_gx_gmu_clk", 0x144, 4, GPU_CC,
737 0x10, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
738 { "gpu_cc_gx_qdss_tsctr_clk", 0x144, 4, GPU_CC,
739 0xE, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
740 { "gpu_cc_gx_vsense_clk", 0x144, 4, GPU_CC,
741 0xD, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
742 { "gpu_cc_rbcpr_ahb_clk", 0x144, 4, GPU_CC,
743 0x1D, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
744 { "gpu_cc_rbcpr_clk", 0x144, 4, GPU_CC,
745 0x1C, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
746 { "gpu_cc_sleep_clk", 0x144, 4, GPU_CC,
747 0x17, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
748 { "gpu_cc_spdm_gx_gfx3d_div_clk", 0x144, 4, GPU_CC,
749 0x1E, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },
750 { "video_cc_apb_clk", 0x48, 4, VIDEO_CC,
751 0x8, 0x3F, 0, 0x7, 0, 1, 0xA4C, 0xA50, 0xA58 },
752 { "video_cc_at_clk", 0x48, 4, VIDEO_CC,
753 0xB, 0x3F, 0, 0x7, 0, 1, 0xA4C, 0xA50, 0xA58 },
754 { "video_cc_qdss_trig_clk", 0x48, 4, VIDEO_CC,
755 0x7, 0x3F, 0, 0x7, 0, 1, 0xA4C, 0xA50, 0xA58 },
756 { "video_cc_qdss_tsctr_div8_clk", 0x48, 4, VIDEO_CC,
757 0xA, 0x3F, 0, 0x7, 0, 1, 0xA4C, 0xA50, 0xA58 },
758 { "video_cc_vcodec0_axi_clk", 0x48, 4, VIDEO_CC,
759 0x5, 0x3F, 0, 0x7, 0, 1, 0xA4C, 0xA50, 0xA58 },
760 { "video_cc_vcodec0_core_clk", 0x48, 4, VIDEO_CC,
761 0x2, 0x3F, 0, 0x7, 0, 1, 0xA4C, 0xA50, 0xA58 },
762 { "video_cc_vcodec1_axi_clk", 0x48, 4, VIDEO_CC,
763 0x6, 0x3F, 0, 0x7, 0, 1, 0xA4C, 0xA50, 0xA58 },
764 { "video_cc_vcodec1_core_clk", 0x48, 4, VIDEO_CC,
765 0x3, 0x3F, 0, 0x7, 0, 1, 0xA4C, 0xA50, 0xA58 },
766 { "video_cc_venus_ahb_clk", 0x48, 4, VIDEO_CC,
767 0x9, 0x3F, 0, 0x7, 0, 1, 0xA4C, 0xA50, 0xA58 },
768 { "video_cc_venus_ctl_axi_clk", 0x48, 4, VIDEO_CC,
769 0x4, 0x3F, 0, 0x7, 0, 1, 0xA4C, 0xA50, 0xA58 },
770 { "video_cc_venus_ctl_core_clk", 0x48, 4, VIDEO_CC,
771 0x1, 0x3F, 0, 0x7, 0, 1, 0xA4C, 0xA50, 0xA58 },
Deepak Katragaddabca4a872017-04-24 15:51:03 -0700[diff] [blame^]772 { "l3_clk", 0xD6, 4, CPU,
773 0x46, 0x7F, 4, 0xf, 11, 1, 0x0, 0x0, U32_MAX, 16 },
774 { "pwrcl_clk", 0xD6, 4, CPU,
775 0x44, 0x7F, 4, 0xf, 11, 1, 0x0, 0x0, U32_MAX, 16 },
776 { "perfcl_clk", 0xD6, 4, CPU,
777 0x45, 0x7F, 4, 0xf, 11, 1, 0x0, 0x0, U32_MAX, 16 },
Deepak Katragaddac617c382017-02-28 11:06:06 -0800[diff] [blame]778 ),
779 .hw.init = &(struct clk_init_data){
780 .name = "gcc_debug_mux",
781 .ops = &clk_debug_mux_ops,
782 .parent_names = debug_mux_parent_names,
783 .num_parents = ARRAY_SIZE(debug_mux_parent_names),
784 .flags = CLK_IS_MEASURE,
785 },
786};
787
788static const struct of_device_id clk_debug_match_table[] = {
789 { .compatible = "qcom,debugcc-sdm845" },
790 {}
791};
792
793static int clk_debug_845_probe(struct platform_device *pdev)
794{
795 struct clk *clk;
796 int ret = 0, count;
797
798 clk = devm_clk_get(&pdev->dev, "xo_clk_src");
799 if (IS_ERR(clk)) {
800 if (PTR_ERR(clk) != -EPROBE_DEFER)
801 dev_err(&pdev->dev, "Unable to get xo clock\n");
802 return PTR_ERR(clk);
803 }
804
805 debug_mux_priv.cxo = clk;
806
807 ret = of_property_read_u32(pdev->dev.of_node, "qcom,cc-count",
808 &count);
809 if (ret < 0) {
810 dev_err(&pdev->dev, "Num of debug clock controller not specified\n");
811 return ret;
812 }
813
814 if (!count) {
815 dev_err(&pdev->dev, "Count of CC cannot be zero\n");
816 return -EINVAL;
817 }
818
819 gcc_debug_mux.regmap = devm_kzalloc(&pdev->dev,
820 sizeof(struct regmap *) * count, GFP_KERNEL);
821 if (!gcc_debug_mux.regmap)
822 return -ENOMEM;
823
824 if (of_get_property(pdev->dev.of_node, "qcom,gcc", NULL)) {
825 gcc_debug_mux.regmap[GCC] =
826 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
827 "qcom,gcc");
828 if (IS_ERR(gcc_debug_mux.regmap[GCC])) {
829 pr_err("Failed to map qcom,gcc\n");
830 return PTR_ERR(gcc_debug_mux.regmap[GCC]);
831 }
832 }
833
834 if (of_get_property(pdev->dev.of_node, "qcom,dispcc", NULL)) {
835 gcc_debug_mux.regmap[DISP_CC] =
836 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
837 "qcom,dispcc");
838 if (IS_ERR(gcc_debug_mux.regmap[DISP_CC])) {
839 pr_err("Failed to map qcom,dispcc\n");
840 return PTR_ERR(gcc_debug_mux.regmap[DISP_CC]);
841 }
842 }
843
844 if (of_get_property(pdev->dev.of_node, "qcom,videocc", NULL)) {
845 gcc_debug_mux.regmap[VIDEO_CC] =
846 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
847 "qcom,videocc");
848 if (IS_ERR(gcc_debug_mux.regmap[VIDEO_CC])) {
849 pr_err("Failed to map qcom,videocc\n");
850 return PTR_ERR(gcc_debug_mux.regmap[VIDEO_CC]);
851 }
852 }
853
854 if (of_get_property(pdev->dev.of_node, "qcom,camcc", NULL)) {
855 gcc_debug_mux.regmap[CAM_CC] =
856 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
857 "qcom,camcc");
858 if (IS_ERR(gcc_debug_mux.regmap[CAM_CC])) {
859 pr_err("Failed to map qcom,camcc\n");
860 return PTR_ERR(gcc_debug_mux.regmap[CAM_CC]);
861 }
862 }
863
864 if (of_get_property(pdev->dev.of_node, "qcom,gpucc", NULL)) {
865 gcc_debug_mux.regmap[GPU_CC] =
866 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
867 "qcom,gpucc");
868 if (IS_ERR(gcc_debug_mux.regmap[GPU_CC])) {
869 pr_err("Failed to map qcom,gpucc\n");
870 return PTR_ERR(gcc_debug_mux.regmap[GPU_CC]);
871 }
872 }
873
Deepak Katragaddabca4a872017-04-24 15:51:03 -0700[diff] [blame^]874 if (of_get_property(pdev->dev.of_node, "qcom,cpucc", NULL)) {
875 gcc_debug_mux.regmap[CPU] =
876 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
877 "qcom,cpucc");
878 if (IS_ERR(gcc_debug_mux.regmap[CPU])) {
879 pr_err("Failed to map qcom,cpucc\n");
880 return PTR_ERR(gcc_debug_mux.regmap[CPU]);
881 }
882 }
883
Deepak Katragaddac617c382017-02-28 11:06:06 -0800[diff] [blame]884 clk = devm_clk_register(&pdev->dev, &gcc_debug_mux.hw);
885 if (IS_ERR(clk)) {
886 dev_err(&pdev->dev, "Unable to register GCC debug mux\n");
887 return PTR_ERR(clk);
888 }
889
890 ret = clk_debug_measure_register(&gcc_debug_mux.hw);
891 if (ret)
892 dev_err(&pdev->dev, "Could not register Measure clock\n");
893 else
894 dev_info(&pdev->dev, "Registered debug mux successfully\n");
895
896 return ret;
897}
898
899static struct platform_driver clk_debug_driver = {
900 .probe = clk_debug_845_probe,
901 .driver = {
902 .name = "debugcc-sdm845",
903 .of_match_table = clk_debug_match_table,
904 .owner = THIS_MODULE,
905 },
906};
907
908int __init clk_debug_845_init(void)
909{
910 return platform_driver_register(&clk_debug_driver);
911}
912fs_initcall(clk_debug_845_init);
913
914MODULE_DESCRIPTION("QTI DEBUG CC SDM845 Driver");
915MODULE_LICENSE("GPL v2");
916MODULE_ALIAS("platform:debugcc-sdm845");