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Matthew Wilcoxb60503b2011-01-20 12:50:14 -05001/*
2 * Definitions for the NVM Express interface
Matthew Wilcox8757ad62014-04-11 10:37:39 -04003 * Copyright (c) 2011-2014, Intel Corporation.
Matthew Wilcoxb60503b2011-01-20 12:50:14 -05004 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
Matthew Wilcoxb60503b2011-01-20 12:50:14 -050013 */
14
15#ifndef _LINUX_NVME_H
16#define _LINUX_NVME_H
17
Matthew Wilcox42c77682013-06-25 15:14:56 -040018#include <uapi/linux/nvme.h>
19#include <linux/pci.h>
20#include <linux/miscdevice.h>
21#include <linux/kref.h>
Matthew Wilcoxb60503b2011-01-20 12:50:14 -050022
23struct nvme_bar {
24 __u64 cap; /* Controller Capabilities */
25 __u32 vs; /* Version */
Matthew Wilcox897cfe12011-02-14 12:20:15 -050026 __u32 intms; /* Interrupt Mask Set */
27 __u32 intmc; /* Interrupt Mask Clear */
Matthew Wilcoxb60503b2011-01-20 12:50:14 -050028 __u32 cc; /* Controller Configuration */
Matthew Wilcox897cfe12011-02-14 12:20:15 -050029 __u32 rsvd1; /* Reserved */
Matthew Wilcoxb60503b2011-01-20 12:50:14 -050030 __u32 csts; /* Controller Status */
Matthew Wilcox897cfe12011-02-14 12:20:15 -050031 __u32 rsvd2; /* Reserved */
Matthew Wilcoxb60503b2011-01-20 12:50:14 -050032 __u32 aqa; /* Admin Queue Attributes */
33 __u64 asq; /* Admin SQ Base Address */
34 __u64 acq; /* Admin CQ Base Address */
35};
36
Keith Buscha0cadb82012-07-27 13:57:23 -040037#define NVME_CAP_MQES(cap) ((cap) & 0xffff)
Matthew Wilcox22605f92011-04-19 15:04:20 -040038#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
Matthew Wilcoxf1938f62011-10-20 17:00:41 -040039#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
Keith Busch8fc23e02012-07-26 11:29:57 -060040#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
Matthew Wilcox22605f92011-04-19 15:04:20 -040041
Matthew Wilcoxb60503b2011-01-20 12:50:14 -050042enum {
43 NVME_CC_ENABLE = 1 << 0,
44 NVME_CC_CSS_NVM = 0 << 4,
45 NVME_CC_MPS_SHIFT = 7,
46 NVME_CC_ARB_RR = 0 << 11,
47 NVME_CC_ARB_WRRU = 1 << 11,
Matthew Wilcox7f53f9d2011-03-22 15:55:45 -040048 NVME_CC_ARB_VS = 7 << 11,
49 NVME_CC_SHN_NONE = 0 << 14,
50 NVME_CC_SHN_NORMAL = 1 << 14,
51 NVME_CC_SHN_ABRUPT = 2 << 14,
Keith Busch1894d8f2013-07-15 15:02:22 -060052 NVME_CC_SHN_MASK = 3 << 14,
Matthew Wilcox7f53f9d2011-03-22 15:55:45 -040053 NVME_CC_IOSQES = 6 << 16,
54 NVME_CC_IOCQES = 4 << 20,
Matthew Wilcoxb60503b2011-01-20 12:50:14 -050055 NVME_CSTS_RDY = 1 << 0,
56 NVME_CSTS_CFS = 1 << 1,
57 NVME_CSTS_SHST_NORMAL = 0 << 2,
58 NVME_CSTS_SHST_OCCUR = 1 << 2,
59 NVME_CSTS_SHST_CMPLT = 2 << 2,
Keith Busch1894d8f2013-07-15 15:02:22 -060060 NVME_CSTS_SHST_MASK = 3 << 2,
Matthew Wilcoxb60503b2011-01-20 12:50:14 -050061};
62
63#define NVME_VS(major, minor) (major << 16 | minor)
64
Matthew Wilcoxbd676082014-06-03 23:04:30 -040065extern unsigned char nvme_io_timeout;
66#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
Vishal Verma13c3b0f2013-03-04 18:40:57 -070067
68/*
69 * Represents an NVM Express device. Each nvme_dev is a PCI function.
70 */
71struct nvme_dev {
72 struct list_head node;
Keith Busch5a92e702014-02-21 14:13:44 -070073 struct nvme_queue __rcu **queues;
Keith Busch42f61422014-03-24 10:46:25 -060074 unsigned short __percpu *io_queue;
Vishal Verma13c3b0f2013-03-04 18:40:57 -070075 u32 __iomem *dbs;
76 struct pci_dev *pci_dev;
77 struct dma_pool *prp_page_pool;
78 struct dma_pool *prp_small_pool;
79 int instance;
Keith Busch42f61422014-03-24 10:46:25 -060080 unsigned queue_count;
81 unsigned online_queues;
82 unsigned max_qid;
83 int q_depth;
Haiyan Hub80d5cc2013-09-10 11:25:37 +080084 u32 db_stride;
Vishal Verma13c3b0f2013-03-04 18:40:57 -070085 u32 ctrl_config;
86 struct msix_entry *entry;
87 struct nvme_bar __iomem *bar;
88 struct list_head namespaces;
Keith Busch5e82e952013-02-19 10:17:58 -070089 struct kref kref;
90 struct miscdevice miscdev;
Tejun Heo9ca97372014-03-07 10:24:49 -050091 work_func_t reset_workfn;
Keith Busch9a6b9452013-12-10 13:10:36 -070092 struct work_struct reset_work;
Keith Buschf3db22f2014-06-11 11:51:35 -060093 struct work_struct cpu_work;
Keith Busch5e82e952013-02-19 10:17:58 -070094 char name[12];
Vishal Verma13c3b0f2013-03-04 18:40:57 -070095 char serial[20];
96 char model[40];
97 char firmware_rev[8];
98 u32 max_hw_sectors;
Keith Busch159b67d2013-04-09 17:13:20 -060099 u32 stripe_size;
Vishal Verma13c3b0f2013-03-04 18:40:57 -0700100 u16 oncs;
Keith Buschc30341d2013-12-10 13:10:38 -0700101 u16 abort_limit;
Keith Buscha7d2ce22014-04-29 11:41:28 -0600102 u8 vwc;
Keith Buschd4b4ff82013-12-10 13:10:37 -0700103 u8 initialized;
Vishal Verma13c3b0f2013-03-04 18:40:57 -0700104};
105
106/*
107 * An NVM Express namespace is equivalent to a SCSI LUN
108 */
109struct nvme_ns {
110 struct list_head list;
111
112 struct nvme_dev *dev;
113 struct request_queue *queue;
114 struct gendisk *disk;
115
Matthew Wilcoxc3bfe712013-07-08 17:26:25 -0400116 unsigned ns_id;
Vishal Verma13c3b0f2013-03-04 18:40:57 -0700117 int lba_shift;
Keith Buschf410c682013-04-23 17:23:59 -0600118 int ms;
Vishal Verma5d0f6132013-03-04 18:40:58 -0700119 u64 mode_select_num_blocks;
120 u32 mode_select_block_len;
Vishal Verma13c3b0f2013-03-04 18:40:57 -0700121};
122
123/*
124 * The nvme_iod describes the data in an I/O, including the list of PRP
125 * entries. You can't see it in this data structure because C doesn't let
126 * me express that. Use nvme_alloc_iod to ensure there's enough space
127 * allocated to store the PRP list.
128 */
129struct nvme_iod {
130 void *private; /* For the use of the submitter of the I/O */
131 int npages; /* In the PRP list. 0 means small pool in use */
132 int offset; /* Of PRP list */
133 int nents; /* Used in scatterlist */
134 int length; /* Of data, in bytes */
Keith Busch61982212013-05-29 15:59:39 -0600135 unsigned long start_time;
Vishal Verma13c3b0f2013-03-04 18:40:57 -0700136 dma_addr_t first_dma;
Keith Buschedd10d32014-04-03 16:45:23 -0600137 struct list_head node;
Vishal Verma13c3b0f2013-03-04 18:40:57 -0700138 struct scatterlist sg[0];
139};
Vishal Verma5d0f6132013-03-04 18:40:58 -0700140
Matthew Wilcox063cc6d2013-03-27 21:28:22 -0400141static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
142{
143 return (sector >> (ns->lba_shift - 9));
144}
145
Vishal Verma5d0f6132013-03-04 18:40:58 -0700146/**
147 * nvme_free_iod - frees an nvme_iod
148 * @dev: The device that the I/O was submitted to
149 * @iod: The memory to free
150 */
151void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod);
152
Keith Buschedd10d32014-04-03 16:45:23 -0600153int nvme_setup_prps(struct nvme_dev *, struct nvme_iod *, int , gfp_t);
Vishal Verma5d0f6132013-03-04 18:40:58 -0700154struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
155 unsigned long addr, unsigned length);
156void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
157 struct nvme_iod *iod);
Keith Busch4f5099a2014-03-03 16:39:13 -0700158int nvme_submit_io_cmd(struct nvme_dev *, struct nvme_command *, u32 *);
Vishal Verma5d0f6132013-03-04 18:40:58 -0700159int nvme_submit_admin_cmd(struct nvme_dev *, struct nvme_command *,
160 u32 *result);
161int nvme_identify(struct nvme_dev *, unsigned nsid, unsigned cns,
162 dma_addr_t dma_addr);
163int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
164 dma_addr_t dma_addr, u32 *result);
165int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
166 dma_addr_t dma_addr, u32 *result);
167
168struct sg_io_hdr;
169
170int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr);
Keith Busch320a3822013-10-23 13:07:34 -0600171int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
Vishal Verma5d0f6132013-03-04 18:40:58 -0700172int nvme_sg_get_version_num(int __user *ip);
173
Matthew Wilcoxb60503b2011-01-20 12:50:14 -0500174#endif /* _LINUX_NVME_H */