Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> |
| 3 | * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> |
| 4 | * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org> |
| 5 | * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu> |
| 6 | * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org> |
| 7 | * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> |
| 8 | * |
| 9 | * Permission to use, copy, modify, and distribute this software for any |
| 10 | * purpose with or without fee is hereby granted, provided that the above |
| 11 | * copyright notice and this permission notice appear in all copies. |
| 12 | * |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 14 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 15 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 16 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 17 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 18 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 19 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 20 | * |
| 21 | */ |
| 22 | |
| 23 | /*********************************\ |
| 24 | * Protocol Control Unit Functions * |
| 25 | \*********************************/ |
| 26 | |
Luis R. Rodriguez | bcd8f54 | 2009-09-09 22:43:17 -0700 | [diff] [blame^] | 27 | #include <asm/unaligned.h> |
| 28 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 29 | #include "ath5k.h" |
| 30 | #include "reg.h" |
| 31 | #include "debug.h" |
| 32 | #include "base.h" |
| 33 | |
| 34 | /*******************\ |
| 35 | * Generic functions * |
| 36 | \*******************/ |
| 37 | |
| 38 | /** |
| 39 | * ath5k_hw_set_opmode - Set PCU operating mode |
| 40 | * |
| 41 | * @ah: The &struct ath5k_hw |
| 42 | * |
| 43 | * Initialize PCU for the various operating modes (AP/STA etc) |
| 44 | * |
| 45 | * NOTE: ah->ah_op_mode must be set before calling this. |
| 46 | */ |
| 47 | int ath5k_hw_set_opmode(struct ath5k_hw *ah) |
| 48 | { |
| 49 | u32 pcu_reg, beacon_reg, low_id, high_id; |
| 50 | |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 51 | |
| 52 | /* Preserve rest settings */ |
| 53 | pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; |
| 54 | pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP |
| 55 | | AR5K_STA_ID1_KEYSRCH_MODE |
| 56 | | (ah->ah_version == AR5K_AR5210 ? |
| 57 | (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0)); |
| 58 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 59 | beacon_reg = 0; |
| 60 | |
| 61 | ATH5K_TRACE(ah->ah_sc); |
| 62 | |
| 63 | switch (ah->ah_op_mode) { |
Johannes Berg | 05c914f | 2008-09-11 00:01:58 +0200 | [diff] [blame] | 64 | case NL80211_IFTYPE_ADHOC: |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 65 | pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE; |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 66 | beacon_reg |= AR5K_BCR_ADHOC; |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 67 | if (ah->ah_version == AR5K_AR5210) |
| 68 | pcu_reg |= AR5K_STA_ID1_NO_PSPOLL; |
| 69 | else |
Steve Brown | 4fb7404 | 2008-12-23 07:57:05 -0500 | [diff] [blame] | 70 | AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 71 | break; |
| 72 | |
Johannes Berg | 05c914f | 2008-09-11 00:01:58 +0200 | [diff] [blame] | 73 | case NL80211_IFTYPE_AP: |
| 74 | case NL80211_IFTYPE_MESH_POINT: |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 75 | pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_KEYSRCH_MODE; |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 76 | beacon_reg |= AR5K_BCR_AP; |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 77 | if (ah->ah_version == AR5K_AR5210) |
| 78 | pcu_reg |= AR5K_STA_ID1_NO_PSPOLL; |
| 79 | else |
Steve Brown | 4fb7404 | 2008-12-23 07:57:05 -0500 | [diff] [blame] | 80 | AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 81 | break; |
| 82 | |
Johannes Berg | 05c914f | 2008-09-11 00:01:58 +0200 | [diff] [blame] | 83 | case NL80211_IFTYPE_STATION: |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 84 | pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE |
| 85 | | (ah->ah_version == AR5K_AR5210 ? |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 86 | AR5K_STA_ID1_PWR_SV : 0); |
Johannes Berg | 05c914f | 2008-09-11 00:01:58 +0200 | [diff] [blame] | 87 | case NL80211_IFTYPE_MONITOR: |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 88 | pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE |
| 89 | | (ah->ah_version == AR5K_AR5210 ? |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 90 | AR5K_STA_ID1_NO_PSPOLL : 0); |
| 91 | break; |
| 92 | |
| 93 | default: |
| 94 | return -EINVAL; |
| 95 | } |
| 96 | |
| 97 | /* |
| 98 | * Set PCU registers |
| 99 | */ |
Luis R. Rodriguez | bcd8f54 | 2009-09-09 22:43:17 -0700 | [diff] [blame^] | 100 | low_id = get_unaligned_le32(ah->ah_sta_id); |
| 101 | high_id = get_unaligned_le16(ah->ah_sta_id + 4); |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 102 | ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); |
| 103 | ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); |
| 104 | |
| 105 | /* |
| 106 | * Set Beacon Control Register on 5210 |
| 107 | */ |
| 108 | if (ah->ah_version == AR5K_AR5210) |
| 109 | ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR); |
| 110 | |
| 111 | return 0; |
| 112 | } |
| 113 | |
| 114 | /** |
| 115 | * ath5k_hw_update - Update mib counters (mac layer statistics) |
| 116 | * |
| 117 | * @ah: The &struct ath5k_hw |
| 118 | * @stats: The &struct ieee80211_low_level_stats we use to track |
| 119 | * statistics on the driver |
| 120 | * |
| 121 | * Reads MIB counters from PCU and updates sw statistics. Must be |
| 122 | * called after a MIB interrupt. |
| 123 | */ |
| 124 | void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, |
| 125 | struct ieee80211_low_level_stats *stats) |
| 126 | { |
| 127 | ATH5K_TRACE(ah->ah_sc); |
| 128 | |
| 129 | /* Read-And-Clear */ |
| 130 | stats->dot11ACKFailureCount += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL); |
| 131 | stats->dot11RTSFailureCount += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL); |
| 132 | stats->dot11RTSSuccessCount += ath5k_hw_reg_read(ah, AR5K_RTS_OK); |
| 133 | stats->dot11FCSErrorCount += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL); |
| 134 | |
| 135 | /* XXX: Should we use this to track beacon count ? |
| 136 | * -we read it anyway to clear the register */ |
| 137 | ath5k_hw_reg_read(ah, AR5K_BEACON_CNT); |
| 138 | |
| 139 | /* Reset profile count registers on 5212*/ |
| 140 | if (ah->ah_version == AR5K_AR5212) { |
| 141 | ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_TX); |
| 142 | ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RX); |
| 143 | ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RXCLR); |
| 144 | ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_CYCLE); |
| 145 | } |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 146 | |
| 147 | /* TODO: Handle ANI stats */ |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 148 | } |
| 149 | |
| 150 | /** |
| 151 | * ath5k_hw_set_ack_bitrate - set bitrate for ACKs |
| 152 | * |
| 153 | * @ah: The &struct ath5k_hw |
| 154 | * @high: Flag to determine if we want to use high transmition rate |
| 155 | * for ACKs or not |
| 156 | * |
| 157 | * If high flag is set, we tell hw to use a set of control rates based on |
| 158 | * the current transmition rate (check out control_rates array inside reset.c). |
| 159 | * If not hw just uses the lowest rate available for the current modulation |
| 160 | * scheme being used (1Mbit for CCK and 6Mbits for OFDM). |
| 161 | */ |
| 162 | void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high) |
| 163 | { |
| 164 | if (ah->ah_version != AR5K_AR5212) |
| 165 | return; |
| 166 | else { |
| 167 | u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB; |
| 168 | if (high) |
| 169 | AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val); |
| 170 | else |
| 171 | AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val); |
| 172 | } |
| 173 | } |
| 174 | |
| 175 | |
| 176 | /******************\ |
| 177 | * ACK/CTS Timeouts * |
| 178 | \******************/ |
| 179 | |
| 180 | /** |
| 181 | * ath5k_hw_het_ack_timeout - Get ACK timeout from PCU in usec |
| 182 | * |
| 183 | * @ah: The &struct ath5k_hw |
| 184 | */ |
| 185 | unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah) |
| 186 | { |
| 187 | ATH5K_TRACE(ah->ah_sc); |
| 188 | |
| 189 | return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah, |
| 190 | AR5K_TIME_OUT), AR5K_TIME_OUT_ACK), ah->ah_turbo); |
| 191 | } |
| 192 | |
| 193 | /** |
| 194 | * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU |
| 195 | * |
| 196 | * @ah: The &struct ath5k_hw |
| 197 | * @timeout: Timeout in usec |
| 198 | */ |
| 199 | int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout) |
| 200 | { |
| 201 | ATH5K_TRACE(ah->ah_sc); |
| 202 | if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK), |
| 203 | ah->ah_turbo) <= timeout) |
| 204 | return -EINVAL; |
| 205 | |
| 206 | AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, |
| 207 | ath5k_hw_htoclock(timeout, ah->ah_turbo)); |
| 208 | |
| 209 | return 0; |
| 210 | } |
| 211 | |
| 212 | /** |
| 213 | * ath5k_hw_get_cts_timeout - Get CTS timeout from PCU in usec |
| 214 | * |
| 215 | * @ah: The &struct ath5k_hw |
| 216 | */ |
| 217 | unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah) |
| 218 | { |
| 219 | ATH5K_TRACE(ah->ah_sc); |
| 220 | return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah, |
| 221 | AR5K_TIME_OUT), AR5K_TIME_OUT_CTS), ah->ah_turbo); |
| 222 | } |
| 223 | |
| 224 | /** |
| 225 | * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU |
| 226 | * |
| 227 | * @ah: The &struct ath5k_hw |
| 228 | * @timeout: Timeout in usec |
| 229 | */ |
| 230 | int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout) |
| 231 | { |
| 232 | ATH5K_TRACE(ah->ah_sc); |
| 233 | if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS), |
| 234 | ah->ah_turbo) <= timeout) |
| 235 | return -EINVAL; |
| 236 | |
| 237 | AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, |
| 238 | ath5k_hw_htoclock(timeout, ah->ah_turbo)); |
| 239 | |
| 240 | return 0; |
| 241 | } |
| 242 | |
| 243 | |
| 244 | /****************\ |
| 245 | * BSSID handling * |
| 246 | \****************/ |
| 247 | |
| 248 | /** |
| 249 | * ath5k_hw_get_lladdr - Get station id |
| 250 | * |
| 251 | * @ah: The &struct ath5k_hw |
| 252 | * @mac: The card's mac address |
| 253 | * |
| 254 | * Initialize ah->ah_sta_id using the mac address provided |
| 255 | * (just a memcpy). |
| 256 | * |
| 257 | * TODO: Remove it once we merge ath5k_softc and ath5k_hw |
| 258 | */ |
| 259 | void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac) |
| 260 | { |
| 261 | ATH5K_TRACE(ah->ah_sc); |
| 262 | memcpy(mac, ah->ah_sta_id, ETH_ALEN); |
| 263 | } |
| 264 | |
| 265 | /** |
| 266 | * ath5k_hw_set_lladdr - Set station id |
| 267 | * |
| 268 | * @ah: The &struct ath5k_hw |
| 269 | * @mac: The card's mac address |
| 270 | * |
| 271 | * Set station id on hw using the provided mac address |
| 272 | */ |
| 273 | int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac) |
| 274 | { |
| 275 | u32 low_id, high_id; |
Bob Copeland | f6bac3e | 2008-11-26 16:17:11 -0500 | [diff] [blame] | 276 | u32 pcu_reg; |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 277 | |
| 278 | ATH5K_TRACE(ah->ah_sc); |
| 279 | /* Set new station ID */ |
| 280 | memcpy(ah->ah_sta_id, mac, ETH_ALEN); |
| 281 | |
Bob Copeland | f6bac3e | 2008-11-26 16:17:11 -0500 | [diff] [blame] | 282 | pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; |
| 283 | |
Luis R. Rodriguez | bcd8f54 | 2009-09-09 22:43:17 -0700 | [diff] [blame^] | 284 | low_id = get_unaligned_le32(mac); |
| 285 | high_id = get_unaligned_le16(mac + 4); |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 286 | |
| 287 | ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); |
Bob Copeland | f6bac3e | 2008-11-26 16:17:11 -0500 | [diff] [blame] | 288 | ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 289 | |
| 290 | return 0; |
| 291 | } |
| 292 | |
| 293 | /** |
| 294 | * ath5k_hw_set_associd - Set BSSID for association |
| 295 | * |
| 296 | * @ah: The &struct ath5k_hw |
| 297 | * @bssid: BSSID |
| 298 | * @assoc_id: Assoc id |
| 299 | * |
| 300 | * Sets the BSSID which trigers the "SME Join" operation |
| 301 | */ |
| 302 | void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id) |
| 303 | { |
| 304 | u32 low_id, high_id; |
| 305 | u16 tim_offset = 0; |
| 306 | |
| 307 | /* |
| 308 | * Set simple BSSID mask on 5212 |
| 309 | */ |
| 310 | if (ah->ah_version == AR5K_AR5212) { |
Luis R. Rodriguez | bcd8f54 | 2009-09-09 22:43:17 -0700 | [diff] [blame^] | 311 | ath5k_hw_reg_write(ah, get_unaligned_le32(ah->ah_bssid_mask), |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 312 | AR5K_BSS_IDM0); |
Luis R. Rodriguez | bcd8f54 | 2009-09-09 22:43:17 -0700 | [diff] [blame^] | 313 | ath5k_hw_reg_write(ah, |
| 314 | get_unaligned_le16(ah->ah_bssid_mask + 4), |
| 315 | AR5K_BSS_IDM1); |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 316 | } |
| 317 | |
| 318 | /* |
| 319 | * Set BSSID which triggers the "SME Join" operation |
| 320 | */ |
Luis R. Rodriguez | bcd8f54 | 2009-09-09 22:43:17 -0700 | [diff] [blame^] | 321 | low_id = get_unaligned_le32(bssid); |
| 322 | high_id = get_unaligned_le16(bssid); |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 323 | ath5k_hw_reg_write(ah, low_id, AR5K_BSS_ID0); |
| 324 | ath5k_hw_reg_write(ah, high_id | ((assoc_id & 0x3fff) << |
| 325 | AR5K_BSS_ID1_AID_S), AR5K_BSS_ID1); |
| 326 | |
| 327 | if (assoc_id == 0) { |
| 328 | ath5k_hw_disable_pspoll(ah); |
| 329 | return; |
| 330 | } |
| 331 | |
| 332 | AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM, |
| 333 | tim_offset ? tim_offset + 4 : 0); |
| 334 | |
| 335 | ath5k_hw_enable_pspoll(ah, NULL, 0); |
| 336 | } |
| 337 | |
| 338 | /** |
| 339 | * ath5k_hw_set_bssid_mask - filter out bssids we listen |
| 340 | * |
| 341 | * @ah: the &struct ath5k_hw |
| 342 | * @mask: the bssid_mask, a u8 array of size ETH_ALEN |
| 343 | * |
| 344 | * BSSID masking is a method used by AR5212 and newer hardware to inform PCU |
| 345 | * which bits of the interface's MAC address should be looked at when trying |
| 346 | * to decide which packets to ACK. In station mode and AP mode with a single |
| 347 | * BSS every bit matters since we lock to only one BSS. In AP mode with |
| 348 | * multiple BSSes (virtual interfaces) not every bit matters because hw must |
| 349 | * accept frames for all BSSes and so we tweak some bits of our mac address |
| 350 | * in order to have multiple BSSes. |
| 351 | * |
| 352 | * NOTE: This is a simple filter and does *not* filter out all |
| 353 | * relevant frames. Some frames that are not for us might get ACKed from us |
| 354 | * by PCU because they just match the mask. |
| 355 | * |
| 356 | * When handling multiple BSSes you can get the BSSID mask by computing the |
| 357 | * set of ~ ( MAC XOR BSSID ) for all bssids we handle. |
| 358 | * |
| 359 | * When you do this you are essentially computing the common bits of all your |
| 360 | * BSSes. Later it is assumed the harware will "and" (&) the BSSID mask with |
| 361 | * the MAC address to obtain the relevant bits and compare the result with |
| 362 | * (frame's BSSID & mask) to see if they match. |
| 363 | */ |
| 364 | /* |
| 365 | * Simple example: on your card you have have two BSSes you have created with |
| 366 | * BSSID-01 and BSSID-02. Lets assume BSSID-01 will not use the MAC address. |
| 367 | * There is another BSSID-03 but you are not part of it. For simplicity's sake, |
| 368 | * assuming only 4 bits for a mac address and for BSSIDs you can then have: |
| 369 | * |
| 370 | * \ |
Luis R. Rodriguez | 1775374 | 2009-09-09 22:19:26 -0700 | [diff] [blame] | 371 | * MAC: 0001 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 372 | * BSSID-01: 0100 | --> Belongs to us |
| 373 | * BSSID-02: 1001 | |
| 374 | * / |
| 375 | * ------------------- |
| 376 | * BSSID-03: 0110 | --> External |
| 377 | * ------------------- |
| 378 | * |
| 379 | * Our bssid_mask would then be: |
| 380 | * |
| 381 | * On loop iteration for BSSID-01: |
| 382 | * ~(0001 ^ 0100) -> ~(0101) |
| 383 | * -> 1010 |
| 384 | * bssid_mask = 1010 |
| 385 | * |
| 386 | * On loop iteration for BSSID-02: |
| 387 | * bssid_mask &= ~(0001 ^ 1001) |
| 388 | * bssid_mask = (1010) & ~(0001 ^ 1001) |
| 389 | * bssid_mask = (1010) & ~(1001) |
| 390 | * bssid_mask = (1010) & (0110) |
| 391 | * bssid_mask = 0010 |
| 392 | * |
| 393 | * A bssid_mask of 0010 means "only pay attention to the second least |
| 394 | * significant bit". This is because its the only bit common |
| 395 | * amongst the MAC and all BSSIDs we support. To findout what the real |
| 396 | * common bit is we can simply "&" the bssid_mask now with any BSSID we have |
| 397 | * or our MAC address (we assume the hardware uses the MAC address). |
| 398 | * |
| 399 | * Now, suppose there's an incoming frame for BSSID-03: |
| 400 | * |
| 401 | * IFRAME-01: 0110 |
| 402 | * |
| 403 | * An easy eye-inspeciton of this already should tell you that this frame |
| 404 | * will not pass our check. This is beacuse the bssid_mask tells the |
| 405 | * hardware to only look at the second least significant bit and the |
| 406 | * common bit amongst the MAC and BSSIDs is 0, this frame has the 2nd LSB |
| 407 | * as 1, which does not match 0. |
| 408 | * |
| 409 | * So with IFRAME-01 we *assume* the hardware will do: |
| 410 | * |
| 411 | * allow = (IFRAME-01 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0; |
| 412 | * --> allow = (0110 & 0010) == (0010 & 0001) ? 1 : 0; |
| 413 | * --> allow = (0010) == 0000 ? 1 : 0; |
| 414 | * --> allow = 0 |
| 415 | * |
| 416 | * Lets now test a frame that should work: |
| 417 | * |
| 418 | * IFRAME-02: 0001 (we should allow) |
| 419 | * |
| 420 | * allow = (0001 & 1010) == 1010 |
| 421 | * |
| 422 | * allow = (IFRAME-02 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0; |
| 423 | * --> allow = (0001 & 0010) == (0010 & 0001) ? 1 :0; |
| 424 | * --> allow = (0010) == (0010) |
| 425 | * --> allow = 1 |
| 426 | * |
| 427 | * Other examples: |
| 428 | * |
| 429 | * IFRAME-03: 0100 --> allowed |
| 430 | * IFRAME-04: 1001 --> allowed |
| 431 | * IFRAME-05: 1101 --> allowed but its not for us!!! |
| 432 | * |
| 433 | */ |
| 434 | int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask) |
| 435 | { |
| 436 | u32 low_id, high_id; |
| 437 | ATH5K_TRACE(ah->ah_sc); |
| 438 | |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 439 | /* Cache bssid mask so that we can restore it |
| 440 | * on reset */ |
| 441 | memcpy(ah->ah_bssid_mask, mask, ETH_ALEN); |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 442 | if (ah->ah_version == AR5K_AR5212) { |
Luis R. Rodriguez | bcd8f54 | 2009-09-09 22:43:17 -0700 | [diff] [blame^] | 443 | low_id = get_unaligned_le32(mask); |
| 444 | high_id = get_unaligned_le16(mask + 4); |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 445 | |
| 446 | ath5k_hw_reg_write(ah, low_id, AR5K_BSS_IDM0); |
| 447 | ath5k_hw_reg_write(ah, high_id, AR5K_BSS_IDM1); |
| 448 | |
| 449 | return 0; |
| 450 | } |
| 451 | |
| 452 | return -EIO; |
| 453 | } |
| 454 | |
| 455 | |
| 456 | /************\ |
| 457 | * RX Control * |
| 458 | \************/ |
| 459 | |
| 460 | /** |
| 461 | * ath5k_hw_start_rx_pcu - Start RX engine |
| 462 | * |
| 463 | * @ah: The &struct ath5k_hw |
| 464 | * |
| 465 | * Starts RX engine on PCU so that hw can process RXed frames |
| 466 | * (ACK etc). |
| 467 | * |
| 468 | * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma |
| 469 | * TODO: Init ANI here |
| 470 | */ |
| 471 | void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah) |
| 472 | { |
| 473 | ATH5K_TRACE(ah->ah_sc); |
| 474 | AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); |
| 475 | } |
| 476 | |
| 477 | /** |
| 478 | * at5k_hw_stop_rx_pcu - Stop RX engine |
| 479 | * |
| 480 | * @ah: The &struct ath5k_hw |
| 481 | * |
| 482 | * Stops RX engine on PCU |
| 483 | * |
| 484 | * TODO: Detach ANI here |
| 485 | */ |
| 486 | void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah) |
| 487 | { |
| 488 | ATH5K_TRACE(ah->ah_sc); |
| 489 | AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); |
| 490 | } |
| 491 | |
| 492 | /* |
| 493 | * Set multicast filter |
| 494 | */ |
| 495 | void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1) |
| 496 | { |
| 497 | ATH5K_TRACE(ah->ah_sc); |
| 498 | /* Set the multicat filter */ |
| 499 | ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0); |
| 500 | ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1); |
| 501 | } |
| 502 | |
| 503 | /* |
| 504 | * Set multicast filter by index |
| 505 | */ |
| 506 | int ath5k_hw_set_mcast_filter_idx(struct ath5k_hw *ah, u32 index) |
| 507 | { |
| 508 | |
| 509 | ATH5K_TRACE(ah->ah_sc); |
| 510 | if (index >= 64) |
| 511 | return -EINVAL; |
| 512 | else if (index >= 32) |
| 513 | AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER1, |
| 514 | (1 << (index - 32))); |
| 515 | else |
| 516 | AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index)); |
| 517 | |
| 518 | return 0; |
| 519 | } |
| 520 | |
| 521 | /* |
| 522 | * Clear Multicast filter by index |
| 523 | */ |
| 524 | int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index) |
| 525 | { |
| 526 | |
| 527 | ATH5K_TRACE(ah->ah_sc); |
| 528 | if (index >= 64) |
| 529 | return -EINVAL; |
| 530 | else if (index >= 32) |
| 531 | AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER1, |
| 532 | (1 << (index - 32))); |
| 533 | else |
| 534 | AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index)); |
| 535 | |
| 536 | return 0; |
| 537 | } |
| 538 | |
| 539 | /** |
| 540 | * ath5k_hw_get_rx_filter - Get current rx filter |
| 541 | * |
| 542 | * @ah: The &struct ath5k_hw |
| 543 | * |
| 544 | * Returns the RX filter by reading rx filter and |
| 545 | * phy error filter registers. RX filter is used |
| 546 | * to set the allowed frame types that PCU will accept |
| 547 | * and pass to the driver. For a list of frame types |
| 548 | * check out reg.h. |
| 549 | */ |
| 550 | u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah) |
| 551 | { |
| 552 | u32 data, filter = 0; |
| 553 | |
| 554 | ATH5K_TRACE(ah->ah_sc); |
| 555 | filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER); |
| 556 | |
| 557 | /*Radar detection for 5212*/ |
| 558 | if (ah->ah_version == AR5K_AR5212) { |
| 559 | data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL); |
| 560 | |
| 561 | if (data & AR5K_PHY_ERR_FIL_RADAR) |
| 562 | filter |= AR5K_RX_FILTER_RADARERR; |
| 563 | if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK)) |
| 564 | filter |= AR5K_RX_FILTER_PHYERR; |
| 565 | } |
| 566 | |
| 567 | return filter; |
| 568 | } |
| 569 | |
| 570 | /** |
| 571 | * ath5k_hw_set_rx_filter - Set rx filter |
| 572 | * |
| 573 | * @ah: The &struct ath5k_hw |
| 574 | * @filter: RX filter mask (see reg.h) |
| 575 | * |
| 576 | * Sets RX filter register and also handles PHY error filter |
| 577 | * register on 5212 and newer chips so that we have proper PHY |
| 578 | * error reporting. |
| 579 | */ |
| 580 | void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter) |
| 581 | { |
| 582 | u32 data = 0; |
| 583 | |
| 584 | ATH5K_TRACE(ah->ah_sc); |
| 585 | |
| 586 | /* Set PHY error filter register on 5212*/ |
| 587 | if (ah->ah_version == AR5K_AR5212) { |
| 588 | if (filter & AR5K_RX_FILTER_RADARERR) |
| 589 | data |= AR5K_PHY_ERR_FIL_RADAR; |
| 590 | if (filter & AR5K_RX_FILTER_PHYERR) |
| 591 | data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK; |
| 592 | } |
| 593 | |
| 594 | /* |
| 595 | * The AR5210 uses promiscous mode to detect radar activity |
| 596 | */ |
| 597 | if (ah->ah_version == AR5K_AR5210 && |
| 598 | (filter & AR5K_RX_FILTER_RADARERR)) { |
| 599 | filter &= ~AR5K_RX_FILTER_RADARERR; |
| 600 | filter |= AR5K_RX_FILTER_PROM; |
| 601 | } |
| 602 | |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 603 | /*Zero length DMA (phy error reporting) */ |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 604 | if (data) |
| 605 | AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); |
| 606 | else |
| 607 | AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); |
| 608 | |
| 609 | /*Write RX Filter register*/ |
| 610 | ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER); |
| 611 | |
| 612 | /*Write PHY error filter register on 5212*/ |
| 613 | if (ah->ah_version == AR5K_AR5212) |
| 614 | ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL); |
| 615 | |
| 616 | } |
| 617 | |
| 618 | |
| 619 | /****************\ |
| 620 | * Beacon control * |
| 621 | \****************/ |
| 622 | |
| 623 | /** |
| 624 | * ath5k_hw_get_tsf32 - Get a 32bit TSF |
| 625 | * |
| 626 | * @ah: The &struct ath5k_hw |
| 627 | * |
| 628 | * Returns lower 32 bits of current TSF |
| 629 | */ |
| 630 | u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah) |
| 631 | { |
| 632 | ATH5K_TRACE(ah->ah_sc); |
| 633 | return ath5k_hw_reg_read(ah, AR5K_TSF_L32); |
| 634 | } |
| 635 | |
| 636 | /** |
| 637 | * ath5k_hw_get_tsf64 - Get the full 64bit TSF |
| 638 | * |
| 639 | * @ah: The &struct ath5k_hw |
| 640 | * |
| 641 | * Returns the current TSF |
| 642 | */ |
| 643 | u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah) |
| 644 | { |
| 645 | u64 tsf = ath5k_hw_reg_read(ah, AR5K_TSF_U32); |
| 646 | ATH5K_TRACE(ah->ah_sc); |
| 647 | |
| 648 | return ath5k_hw_reg_read(ah, AR5K_TSF_L32) | (tsf << 32); |
| 649 | } |
| 650 | |
| 651 | /** |
Alina Friedrichsen | 8cab758 | 2009-01-23 05:39:13 +0100 | [diff] [blame] | 652 | * ath5k_hw_set_tsf64 - Set a new 64bit TSF |
| 653 | * |
| 654 | * @ah: The &struct ath5k_hw |
| 655 | * @tsf64: The new 64bit TSF |
| 656 | * |
| 657 | * Sets the new TSF |
| 658 | */ |
| 659 | void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64) |
| 660 | { |
| 661 | ATH5K_TRACE(ah->ah_sc); |
| 662 | |
Alina Friedrichsen | 8cab758 | 2009-01-23 05:39:13 +0100 | [diff] [blame] | 663 | ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32); |
Alina Friedrichsen | 0ad65bd | 2009-03-02 23:29:48 +0100 | [diff] [blame] | 664 | ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32); |
Alina Friedrichsen | 8cab758 | 2009-01-23 05:39:13 +0100 | [diff] [blame] | 665 | } |
| 666 | |
| 667 | /** |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 668 | * ath5k_hw_reset_tsf - Force a TSF reset |
| 669 | * |
| 670 | * @ah: The &struct ath5k_hw |
| 671 | * |
| 672 | * Forces a TSF reset on PCU |
| 673 | */ |
| 674 | void ath5k_hw_reset_tsf(struct ath5k_hw *ah) |
| 675 | { |
Bob Copeland | 14be994 | 2008-09-28 12:09:43 -0400 | [diff] [blame] | 676 | u32 val; |
| 677 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 678 | ATH5K_TRACE(ah->ah_sc); |
Bob Copeland | 14be994 | 2008-09-28 12:09:43 -0400 | [diff] [blame] | 679 | |
| 680 | val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF; |
| 681 | |
| 682 | /* |
| 683 | * Each write to the RESET_TSF bit toggles a hardware internal |
| 684 | * signal to reset TSF, but if left high it will cause a TSF reset |
| 685 | * on the next chip reset as well. Thus we always write the value |
| 686 | * twice to clear the signal. |
| 687 | */ |
| 688 | ath5k_hw_reg_write(ah, val, AR5K_BEACON); |
| 689 | ath5k_hw_reg_write(ah, val, AR5K_BEACON); |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 690 | } |
| 691 | |
| 692 | /* |
| 693 | * Initialize beacon timers |
| 694 | */ |
| 695 | void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval) |
| 696 | { |
| 697 | u32 timer1, timer2, timer3; |
| 698 | |
| 699 | ATH5K_TRACE(ah->ah_sc); |
| 700 | /* |
| 701 | * Set the additional timers by mode |
| 702 | */ |
| 703 | switch (ah->ah_op_mode) { |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 704 | case NL80211_IFTYPE_MONITOR: |
Johannes Berg | 05c914f | 2008-09-11 00:01:58 +0200 | [diff] [blame] | 705 | case NL80211_IFTYPE_STATION: |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 706 | /* In STA mode timer1 is used as next wakeup |
| 707 | * timer and timer2 as next CFP duration start |
| 708 | * timer. Both in 1/8TUs. */ |
| 709 | /* TODO: PCF handling */ |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 710 | if (ah->ah_version == AR5K_AR5210) { |
| 711 | timer1 = 0xffffffff; |
| 712 | timer2 = 0xffffffff; |
| 713 | } else { |
| 714 | timer1 = 0x0000ffff; |
| 715 | timer2 = 0x0007ffff; |
| 716 | } |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 717 | /* Mark associated AP as PCF incapable for now */ |
| 718 | AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PCF); |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 719 | break; |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 720 | case NL80211_IFTYPE_ADHOC: |
| 721 | AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM); |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 722 | default: |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 723 | /* On non-STA modes timer1 is used as next DMA |
| 724 | * beacon alert (DBA) timer and timer2 as next |
| 725 | * software beacon alert. Both in 1/8TUs. */ |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 726 | timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3; |
| 727 | timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3; |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 728 | break; |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 729 | } |
| 730 | |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 731 | /* Timer3 marks the end of our ATIM window |
| 732 | * a zero length window is not allowed because |
| 733 | * we 'll get no beacons */ |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 734 | timer3 = next_beacon + (ah->ah_atim_window ? ah->ah_atim_window : 1); |
| 735 | |
| 736 | /* |
| 737 | * Set the beacon register and enable all timers. |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 738 | */ |
Nick Kossifidis | 35edf8a | 2009-06-12 16:09:53 -0700 | [diff] [blame] | 739 | /* When in AP or Mesh Point mode zero timer0 to start TSF */ |
| 740 | if (ah->ah_op_mode == NL80211_IFTYPE_AP || |
| 741 | ah->ah_op_mode == NL80211_IFTYPE_MESH_POINT) |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 742 | ath5k_hw_reg_write(ah, 0, AR5K_TIMER0); |
Nick Kossifidis | 428cbd4 | 2009-04-30 15:55:47 -0400 | [diff] [blame] | 743 | |
| 744 | ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0); |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 745 | ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1); |
| 746 | ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2); |
| 747 | ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3); |
| 748 | |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 749 | /* Force a TSF reset if requested and enable beacons */ |
| 750 | if (interval & AR5K_BEACON_RESET_TSF) |
| 751 | ath5k_hw_reset_tsf(ah); |
| 752 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 753 | ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD | |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 754 | AR5K_BEACON_ENABLE), |
| 755 | AR5K_BEACON); |
| 756 | |
| 757 | /* Flush any pending BMISS interrupts on ISR by |
| 758 | * performing a clear-on-write operation on PISR |
| 759 | * register for the BMISS bit (writing a bit on |
| 760 | * ISR togles a reset for that bit and leaves |
| 761 | * the rest bits intact) */ |
| 762 | if (ah->ah_version == AR5K_AR5210) |
| 763 | ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR); |
| 764 | else |
| 765 | ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR); |
| 766 | |
| 767 | /* TODO: Set enchanced sleep registers on AR5212 |
| 768 | * based on vif->bss_conf params, until then |
| 769 | * disable power save reporting.*/ |
| 770 | AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV); |
| 771 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 772 | } |
| 773 | |
| 774 | #if 0 |
| 775 | /* |
| 776 | * Set beacon timers |
| 777 | */ |
| 778 | int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah, |
| 779 | const struct ath5k_beacon_state *state) |
| 780 | { |
| 781 | u32 cfp_period, next_cfp, dtim, interval, next_beacon; |
| 782 | |
| 783 | /* |
| 784 | * TODO: should be changed through *state |
| 785 | * review struct ath5k_beacon_state struct |
| 786 | * |
| 787 | * XXX: These are used for cfp period bellow, are they |
| 788 | * ok ? Is it O.K. for tsf here to be 0 or should we use |
| 789 | * get_tsf ? |
| 790 | */ |
| 791 | u32 dtim_count = 0; /* XXX */ |
| 792 | u32 cfp_count = 0; /* XXX */ |
| 793 | u32 tsf = 0; /* XXX */ |
| 794 | |
| 795 | ATH5K_TRACE(ah->ah_sc); |
| 796 | /* Return on an invalid beacon state */ |
| 797 | if (state->bs_interval < 1) |
| 798 | return -EINVAL; |
| 799 | |
| 800 | interval = state->bs_interval; |
| 801 | dtim = state->bs_dtim_period; |
| 802 | |
| 803 | /* |
| 804 | * PCF support? |
| 805 | */ |
| 806 | if (state->bs_cfp_period > 0) { |
| 807 | /* |
| 808 | * Enable PCF mode and set the CFP |
| 809 | * (Contention Free Period) and timer registers |
| 810 | */ |
| 811 | cfp_period = state->bs_cfp_period * state->bs_dtim_period * |
| 812 | state->bs_interval; |
| 813 | next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) * |
| 814 | state->bs_interval; |
| 815 | |
| 816 | AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, |
| 817 | AR5K_STA_ID1_DEFAULT_ANTENNA | |
| 818 | AR5K_STA_ID1_PCF); |
| 819 | ath5k_hw_reg_write(ah, cfp_period, AR5K_CFP_PERIOD); |
| 820 | ath5k_hw_reg_write(ah, state->bs_cfp_max_duration, |
| 821 | AR5K_CFP_DUR); |
| 822 | ath5k_hw_reg_write(ah, (tsf + (next_cfp == 0 ? cfp_period : |
| 823 | next_cfp)) << 3, AR5K_TIMER2); |
| 824 | } else { |
| 825 | /* Disable PCF mode */ |
| 826 | AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, |
| 827 | AR5K_STA_ID1_DEFAULT_ANTENNA | |
| 828 | AR5K_STA_ID1_PCF); |
| 829 | } |
| 830 | |
| 831 | /* |
| 832 | * Enable the beacon timer register |
| 833 | */ |
| 834 | ath5k_hw_reg_write(ah, state->bs_next_beacon, AR5K_TIMER0); |
| 835 | |
| 836 | /* |
| 837 | * Start the beacon timers |
| 838 | */ |
| 839 | ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_BEACON) & |
| 840 | ~(AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) | |
| 841 | AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, |
| 842 | AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval, |
| 843 | AR5K_BEACON_PERIOD), AR5K_BEACON); |
| 844 | |
| 845 | /* |
| 846 | * Write new beacon miss threshold, if it appears to be valid |
| 847 | * XXX: Figure out right values for min <= bs_bmiss_threshold <= max |
| 848 | * and return if its not in range. We can test this by reading value and |
| 849 | * setting value to a largest value and seeing which values register. |
| 850 | */ |
| 851 | |
| 852 | AR5K_REG_WRITE_BITS(ah, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS, |
| 853 | state->bs_bmiss_threshold); |
| 854 | |
| 855 | /* |
| 856 | * Set sleep control register |
| 857 | * XXX: Didn't find this in 5210 code but since this register |
| 858 | * exists also in ar5k's 5210 headers i leave it as common code. |
| 859 | */ |
| 860 | AR5K_REG_WRITE_BITS(ah, AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR, |
| 861 | (state->bs_sleep_duration - 3) << 3); |
| 862 | |
| 863 | /* |
| 864 | * Set enhanced sleep registers on 5212 |
| 865 | */ |
| 866 | if (ah->ah_version == AR5K_AR5212) { |
| 867 | if (state->bs_sleep_duration > state->bs_interval && |
| 868 | roundup(state->bs_sleep_duration, interval) == |
| 869 | state->bs_sleep_duration) |
| 870 | interval = state->bs_sleep_duration; |
| 871 | |
| 872 | if (state->bs_sleep_duration > dtim && (dtim == 0 || |
| 873 | roundup(state->bs_sleep_duration, dtim) == |
| 874 | state->bs_sleep_duration)) |
| 875 | dtim = state->bs_sleep_duration; |
| 876 | |
| 877 | if (interval > dtim) |
| 878 | return -EINVAL; |
| 879 | |
| 880 | next_beacon = interval == dtim ? state->bs_next_dtim : |
| 881 | state->bs_next_beacon; |
| 882 | |
| 883 | ath5k_hw_reg_write(ah, |
| 884 | AR5K_REG_SM((state->bs_next_dtim - 3) << 3, |
| 885 | AR5K_SLEEP0_NEXT_DTIM) | |
| 886 | AR5K_REG_SM(10, AR5K_SLEEP0_CABTO) | |
| 887 | AR5K_SLEEP0_ENH_SLEEP_EN | |
| 888 | AR5K_SLEEP0_ASSUME_DTIM, AR5K_SLEEP0); |
| 889 | |
| 890 | ath5k_hw_reg_write(ah, AR5K_REG_SM((next_beacon - 3) << 3, |
| 891 | AR5K_SLEEP1_NEXT_TIM) | |
| 892 | AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO), AR5K_SLEEP1); |
| 893 | |
| 894 | ath5k_hw_reg_write(ah, |
| 895 | AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) | |
| 896 | AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER), AR5K_SLEEP2); |
| 897 | } |
| 898 | |
| 899 | return 0; |
| 900 | } |
| 901 | |
| 902 | /* |
| 903 | * Reset beacon timers |
| 904 | */ |
| 905 | void ath5k_hw_reset_beacon(struct ath5k_hw *ah) |
| 906 | { |
| 907 | ATH5K_TRACE(ah->ah_sc); |
| 908 | /* |
| 909 | * Disable beacon timer |
| 910 | */ |
| 911 | ath5k_hw_reg_write(ah, 0, AR5K_TIMER0); |
| 912 | |
| 913 | /* |
| 914 | * Disable some beacon register values |
| 915 | */ |
| 916 | AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, |
| 917 | AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF); |
| 918 | ath5k_hw_reg_write(ah, AR5K_BEACON_PERIOD, AR5K_BEACON); |
| 919 | } |
| 920 | |
| 921 | /* |
| 922 | * Wait for beacon queue to finish |
| 923 | */ |
| 924 | int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr) |
| 925 | { |
| 926 | unsigned int i; |
| 927 | int ret; |
| 928 | |
| 929 | ATH5K_TRACE(ah->ah_sc); |
| 930 | |
| 931 | /* 5210 doesn't have QCU*/ |
| 932 | if (ah->ah_version == AR5K_AR5210) { |
| 933 | /* |
| 934 | * Wait for beaconn queue to finish by checking |
| 935 | * Control Register and Beacon Status Register. |
| 936 | */ |
| 937 | for (i = AR5K_TUNE_BEACON_INTERVAL / 2; i > 0; i--) { |
| 938 | if (!(ath5k_hw_reg_read(ah, AR5K_BSR) & AR5K_BSR_TXQ1F) |
| 939 | || |
| 940 | !(ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_BSR_TXQ1F)) |
| 941 | break; |
| 942 | udelay(10); |
| 943 | } |
| 944 | |
| 945 | /* Timeout... */ |
| 946 | if (i <= 0) { |
| 947 | /* |
| 948 | * Re-schedule the beacon queue |
| 949 | */ |
| 950 | ath5k_hw_reg_write(ah, phys_addr, AR5K_NOQCU_TXDP1); |
| 951 | ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, |
| 952 | AR5K_BCR); |
| 953 | |
| 954 | return -EIO; |
| 955 | } |
| 956 | ret = 0; |
| 957 | } else { |
| 958 | /*5211/5212*/ |
| 959 | ret = ath5k_hw_register_timeout(ah, |
| 960 | AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON), |
| 961 | AR5K_QCU_STS_FRMPENDCNT, 0, false); |
| 962 | |
| 963 | if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON)) |
| 964 | return -EIO; |
| 965 | } |
| 966 | |
| 967 | return ret; |
| 968 | } |
| 969 | #endif |
| 970 | |
| 971 | |
| 972 | /*********************\ |
| 973 | * Key table functions * |
| 974 | \*********************/ |
| 975 | |
| 976 | /* |
| 977 | * Reset a key entry on the table |
| 978 | */ |
| 979 | int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry) |
| 980 | { |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 981 | unsigned int i, type; |
Bob Copeland | 17683c6 | 2008-10-29 23:24:26 -0400 | [diff] [blame] | 982 | u16 micentry = entry + AR5K_KEYTABLE_MIC_OFFSET; |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 983 | |
| 984 | ATH5K_TRACE(ah->ah_sc); |
| 985 | AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); |
| 986 | |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 987 | type = ath5k_hw_reg_read(ah, AR5K_KEYTABLE_TYPE(entry)); |
| 988 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 989 | for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) |
| 990 | ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i)); |
| 991 | |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 992 | /* Reset associated MIC entry if TKIP |
| 993 | * is enabled located at offset (entry + 64) */ |
| 994 | if (type == AR5K_KEYTABLE_TYPE_TKIP) { |
Bob Copeland | 17683c6 | 2008-10-29 23:24:26 -0400 | [diff] [blame] | 995 | AR5K_ASSERT_ENTRY(micentry, AR5K_KEYTABLE_SIZE); |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 996 | for (i = 0; i < AR5K_KEYCACHE_SIZE / 2 ; i++) |
Bob Copeland | 17683c6 | 2008-10-29 23:24:26 -0400 | [diff] [blame] | 997 | ath5k_hw_reg_write(ah, 0, |
| 998 | AR5K_KEYTABLE_OFF(micentry, i)); |
Nick Kossifidis | f07a6c4 | 2008-10-29 04:28:28 +0200 | [diff] [blame] | 999 | } |
| 1000 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1001 | /* |
| 1002 | * Set NULL encryption on AR5212+ |
| 1003 | * |
| 1004 | * Note: AR5K_KEYTABLE_TYPE -> AR5K_KEYTABLE_OFF(entry, 5) |
| 1005 | * AR5K_KEYTABLE_TYPE_NULL -> 0x00000007 |
| 1006 | * |
| 1007 | * Note2: Windows driver (ndiswrapper) sets this to |
| 1008 | * 0x00000714 instead of 0x00000007 |
| 1009 | */ |
Jiri Slaby | ded7a7e | 2009-04-25 14:09:23 +0200 | [diff] [blame] | 1010 | if (ah->ah_version >= AR5K_AR5211) { |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1011 | ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL, |
| 1012 | AR5K_KEYTABLE_TYPE(entry)); |
| 1013 | |
Bob Copeland | 17683c6 | 2008-10-29 23:24:26 -0400 | [diff] [blame] | 1014 | if (type == AR5K_KEYTABLE_TYPE_TKIP) { |
| 1015 | ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL, |
| 1016 | AR5K_KEYTABLE_TYPE(micentry)); |
| 1017 | } |
| 1018 | } |
| 1019 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1020 | return 0; |
| 1021 | } |
| 1022 | |
| 1023 | /* |
| 1024 | * Check if a table entry is valid |
| 1025 | */ |
| 1026 | int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry) |
| 1027 | { |
| 1028 | ATH5K_TRACE(ah->ah_sc); |
| 1029 | AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); |
| 1030 | |
| 1031 | /* Check the validation flag at the end of the entry */ |
| 1032 | return ath5k_hw_reg_read(ah, AR5K_KEYTABLE_MAC1(entry)) & |
| 1033 | AR5K_KEYTABLE_VALID; |
| 1034 | } |
| 1035 | |
Bob Copeland | 67143490 | 2008-11-25 20:55:21 -0500 | [diff] [blame] | 1036 | static |
| 1037 | int ath5k_keycache_type(const struct ieee80211_key_conf *key) |
| 1038 | { |
| 1039 | switch (key->alg) { |
| 1040 | case ALG_TKIP: |
| 1041 | return AR5K_KEYTABLE_TYPE_TKIP; |
| 1042 | case ALG_CCMP: |
| 1043 | return AR5K_KEYTABLE_TYPE_CCM; |
| 1044 | case ALG_WEP: |
Zhu Yi | e31a16d | 2009-05-21 21:47:03 +0800 | [diff] [blame] | 1045 | if (key->keylen == WLAN_KEY_LEN_WEP40) |
Bob Copeland | 67143490 | 2008-11-25 20:55:21 -0500 | [diff] [blame] | 1046 | return AR5K_KEYTABLE_TYPE_40; |
Zhu Yi | e31a16d | 2009-05-21 21:47:03 +0800 | [diff] [blame] | 1047 | else if (key->keylen == WLAN_KEY_LEN_WEP104) |
Bob Copeland | 67143490 | 2008-11-25 20:55:21 -0500 | [diff] [blame] | 1048 | return AR5K_KEYTABLE_TYPE_104; |
Jouni Malinen | 3cfcf6ac | 2009-01-08 13:32:02 +0200 | [diff] [blame] | 1049 | return -EINVAL; |
| 1050 | default: |
| 1051 | return -EINVAL; |
Bob Copeland | 67143490 | 2008-11-25 20:55:21 -0500 | [diff] [blame] | 1052 | } |
| 1053 | return -EINVAL; |
| 1054 | } |
| 1055 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1056 | /* |
| 1057 | * Set a key entry on the table |
| 1058 | */ |
| 1059 | int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry, |
| 1060 | const struct ieee80211_key_conf *key, const u8 *mac) |
| 1061 | { |
| 1062 | unsigned int i; |
Bob Copeland | 3f64b43 | 2008-10-29 23:19:14 -0400 | [diff] [blame] | 1063 | int keylen; |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1064 | __le32 key_v[5] = {}; |
Bob Copeland | 3f64b43 | 2008-10-29 23:19:14 -0400 | [diff] [blame] | 1065 | __le32 key0 = 0, key1 = 0; |
| 1066 | __le32 *rxmic, *txmic; |
Roel Kluin | 672cf3c | 2009-01-18 23:50:27 +0100 | [diff] [blame] | 1067 | int keytype; |
Bob Copeland | 3f64b43 | 2008-10-29 23:19:14 -0400 | [diff] [blame] | 1068 | u16 micentry = entry + AR5K_KEYTABLE_MIC_OFFSET; |
| 1069 | bool is_tkip; |
Bob Copeland | 67143490 | 2008-11-25 20:55:21 -0500 | [diff] [blame] | 1070 | const u8 *key_ptr; |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1071 | |
| 1072 | ATH5K_TRACE(ah->ah_sc); |
| 1073 | |
Bob Copeland | 3f64b43 | 2008-10-29 23:19:14 -0400 | [diff] [blame] | 1074 | is_tkip = (key->alg == ALG_TKIP); |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1075 | |
Bob Copeland | 3f64b43 | 2008-10-29 23:19:14 -0400 | [diff] [blame] | 1076 | /* |
| 1077 | * key->keylen comes in from mac80211 in bytes. |
| 1078 | * TKIP is 128 bit + 128 bit mic |
| 1079 | */ |
| 1080 | keylen = (is_tkip) ? (128 / 8) : key->keylen; |
| 1081 | |
| 1082 | if (entry > AR5K_KEYTABLE_SIZE || |
| 1083 | (is_tkip && micentry > AR5K_KEYTABLE_SIZE)) |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1084 | return -EOPNOTSUPP; |
| 1085 | |
Bob Copeland | 67143490 | 2008-11-25 20:55:21 -0500 | [diff] [blame] | 1086 | if (unlikely(keylen > 16)) |
| 1087 | return -EOPNOTSUPP; |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1088 | |
Bob Copeland | 67143490 | 2008-11-25 20:55:21 -0500 | [diff] [blame] | 1089 | keytype = ath5k_keycache_type(key); |
| 1090 | if (keytype < 0) |
| 1091 | return keytype; |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1092 | |
Bob Copeland | 67143490 | 2008-11-25 20:55:21 -0500 | [diff] [blame] | 1093 | /* |
| 1094 | * each key block is 6 bytes wide, written as pairs of |
| 1095 | * alternating 32 and 16 bit le values. |
| 1096 | */ |
| 1097 | key_ptr = key->key; |
| 1098 | for (i = 0; keylen >= 6; keylen -= 6) { |
| 1099 | memcpy(&key_v[i], key_ptr, 6); |
| 1100 | i += 2; |
| 1101 | key_ptr += 6; |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1102 | } |
Bob Copeland | 67143490 | 2008-11-25 20:55:21 -0500 | [diff] [blame] | 1103 | if (keylen) |
| 1104 | memcpy(&key_v[i], key_ptr, keylen); |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1105 | |
Bob Copeland | 3f64b43 | 2008-10-29 23:19:14 -0400 | [diff] [blame] | 1106 | /* intentionally corrupt key until mic is installed */ |
| 1107 | if (is_tkip) { |
| 1108 | key0 = key_v[0] = ~key_v[0]; |
| 1109 | key1 = key_v[1] = ~key_v[1]; |
| 1110 | } |
| 1111 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1112 | for (i = 0; i < ARRAY_SIZE(key_v); i++) |
| 1113 | ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]), |
| 1114 | AR5K_KEYTABLE_OFF(entry, i)); |
| 1115 | |
| 1116 | ath5k_hw_reg_write(ah, keytype, AR5K_KEYTABLE_TYPE(entry)); |
| 1117 | |
Bob Copeland | 3f64b43 | 2008-10-29 23:19:14 -0400 | [diff] [blame] | 1118 | if (is_tkip) { |
| 1119 | /* Install rx/tx MIC */ |
| 1120 | rxmic = (__le32 *) &key->key[16]; |
| 1121 | txmic = (__le32 *) &key->key[24]; |
Bob Copeland | f650470 | 2008-11-26 16:17:25 -0500 | [diff] [blame] | 1122 | |
| 1123 | if (ah->ah_combined_mic) { |
| 1124 | key_v[0] = rxmic[0]; |
Bob Copeland | 388cdf3 | 2008-12-09 23:05:38 -0500 | [diff] [blame] | 1125 | key_v[1] = cpu_to_le32(le32_to_cpu(txmic[0]) >> 16); |
Bob Copeland | f650470 | 2008-11-26 16:17:25 -0500 | [diff] [blame] | 1126 | key_v[2] = rxmic[1]; |
Bob Copeland | 388cdf3 | 2008-12-09 23:05:38 -0500 | [diff] [blame] | 1127 | key_v[3] = cpu_to_le32(le32_to_cpu(txmic[0]) & 0xffff); |
Bob Copeland | f650470 | 2008-11-26 16:17:25 -0500 | [diff] [blame] | 1128 | key_v[4] = txmic[1]; |
| 1129 | } else { |
| 1130 | key_v[0] = rxmic[0]; |
| 1131 | key_v[1] = 0; |
| 1132 | key_v[2] = rxmic[1]; |
| 1133 | key_v[3] = 0; |
| 1134 | key_v[4] = 0; |
| 1135 | } |
Bob Copeland | 3f64b43 | 2008-10-29 23:19:14 -0400 | [diff] [blame] | 1136 | for (i = 0; i < ARRAY_SIZE(key_v); i++) |
| 1137 | ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]), |
| 1138 | AR5K_KEYTABLE_OFF(micentry, i)); |
| 1139 | |
| 1140 | ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL, |
| 1141 | AR5K_KEYTABLE_TYPE(micentry)); |
| 1142 | ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_MAC0(micentry)); |
| 1143 | ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_MAC1(micentry)); |
| 1144 | |
| 1145 | /* restore first 2 words of key */ |
| 1146 | ath5k_hw_reg_write(ah, le32_to_cpu(~key0), |
| 1147 | AR5K_KEYTABLE_OFF(entry, 0)); |
| 1148 | ath5k_hw_reg_write(ah, le32_to_cpu(~key1), |
| 1149 | AR5K_KEYTABLE_OFF(entry, 1)); |
| 1150 | } |
| 1151 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1152 | return ath5k_hw_set_key_lladdr(ah, entry, mac); |
| 1153 | } |
| 1154 | |
| 1155 | int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac) |
| 1156 | { |
| 1157 | u32 low_id, high_id; |
| 1158 | |
| 1159 | ATH5K_TRACE(ah->ah_sc); |
| 1160 | /* Invalid entry (key table overflow) */ |
| 1161 | AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); |
| 1162 | |
Luis R. Rodriguez | bcd8f54 | 2009-09-09 22:43:17 -0700 | [diff] [blame^] | 1163 | /* |
| 1164 | * MAC may be NULL if it's a broadcast key. In this case no need to |
| 1165 | * to compute get_unaligned_le32 and get_unaligned_le16 as we |
| 1166 | * already know it. |
| 1167 | */ |
Johannes Berg | dc822b5 | 2008-12-29 12:55:09 +0100 | [diff] [blame] | 1168 | if (!mac) { |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1169 | low_id = 0xffffffff; |
| 1170 | high_id = 0xffff | AR5K_KEYTABLE_VALID; |
| 1171 | } else { |
Luis R. Rodriguez | bcd8f54 | 2009-09-09 22:43:17 -0700 | [diff] [blame^] | 1172 | low_id = get_unaligned_le32(mac); |
| 1173 | high_id = get_unaligned_le16(mac + 4) | AR5K_KEYTABLE_VALID; |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1174 | } |
| 1175 | |
| 1176 | ath5k_hw_reg_write(ah, low_id, AR5K_KEYTABLE_MAC0(entry)); |
| 1177 | ath5k_hw_reg_write(ah, high_id, AR5K_KEYTABLE_MAC1(entry)); |
| 1178 | |
| 1179 | return 0; |
| 1180 | } |
| 1181 | |