blob: 9c9b88934bcc904de8b63f20778ef12985ad7ed5 [file] [log] [blame]
Linus Walleijbd41b992009-04-23 21:15:04 +01001/*
Grant Likelyc103de22011-06-04 18:38:28 -06002 * U300 GPIO module.
Linus Walleijbd41b992009-04-23 21:15:04 +01003 *
Linus Walleij04b13de2012-08-13 10:36:55 +02004 * Copyright (C) 2007-2012 ST-Ericsson AB
Linus Walleijbd41b992009-04-23 21:15:04 +01005 * License terms: GNU General Public License (GPL) version 2
Linus Walleijbd41b992009-04-23 21:15:04 +01006 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
Linus Walleijcc890cd2011-09-08 09:04:51 +01007 * Author: Linus Walleij <linus.walleij@linaro.org>
Linus Walleijbd41b992009-04-23 21:15:04 +01008 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
Linus Walleijbd41b992009-04-23 21:15:04 +01009 */
10#include <linux/module.h>
11#include <linux/interrupt.h>
12#include <linux/delay.h>
13#include <linux/errno.h>
14#include <linux/io.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/gpio.h>
Linus Walleijcc890cd2011-09-08 09:04:51 +010019#include <linux/slab.h>
Linus Walleij28a8d142012-02-09 01:52:22 +010020#include <linux/pinctrl/consumer.h>
Linus Walleijdc0b1aa2011-11-16 21:58:10 +010021#include <linux/pinctrl/pinconf-generic.h>
Linus Walleijdc0b1aa2011-11-16 21:58:10 +010022#include "pinctrl-coh901.h"
Linus Walleijbd41b992009-04-23 21:15:04 +010023
Linus Walleij04b13de2012-08-13 10:36:55 +020024#define U300_GPIO_PORT_STRIDE (0x30)
Linus Walleijcc890cd2011-09-08 09:04:51 +010025/*
Linus Walleij04b13de2012-08-13 10:36:55 +020026 * Control Register 32bit (R/W)
27 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
28 * gives the number of GPIO pins.
29 * bit 8-2 (mask 0x000001FC) contains the core version ID.
Linus Walleijcc890cd2011-09-08 09:04:51 +010030 */
Linus Walleij04b13de2012-08-13 10:36:55 +020031#define U300_GPIO_CR (0x00)
32#define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL)
33#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
34#define U300_GPIO_PXPDIR (0x04)
35#define U300_GPIO_PXPDOR (0x08)
36#define U300_GPIO_PXPCR (0x0C)
Linus Walleijcc890cd2011-09-08 09:04:51 +010037#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
38#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
39#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
40#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
41#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
42#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
43#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
Linus Walleij04b13de2012-08-13 10:36:55 +020044#define U300_GPIO_PXPER (0x10)
45#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
46#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
47#define U300_GPIO_PXIEV (0x14)
48#define U300_GPIO_PXIEN (0x18)
49#define U300_GPIO_PXIFR (0x1C)
50#define U300_GPIO_PXICR (0x20)
Linus Walleijcc890cd2011-09-08 09:04:51 +010051#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
52#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
53#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
54#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
Linus Walleijcc890cd2011-09-08 09:04:51 +010055
56/* 8 bits per port, no version has more than 7 ports */
Linus Walleijb263e9b2013-05-23 20:09:43 +020057#define U300_GPIO_NUM_PORTS 7
Linus Walleijcc890cd2011-09-08 09:04:51 +010058#define U300_GPIO_PINS_PER_PORT 8
Linus Walleijb263e9b2013-05-23 20:09:43 +020059#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS)
Linus Walleijcc890cd2011-09-08 09:04:51 +010060
Linus Walleij523dcce2014-03-25 13:37:17 +010061struct u300_gpio_port {
62 struct u300_gpio *gpio;
63 char name[8];
64 int irq;
65 int number;
66 u8 toggle_edge_mode;
67};
68
Linus Walleijcc890cd2011-09-08 09:04:51 +010069struct u300_gpio {
70 struct gpio_chip chip;
Linus Walleij523dcce2014-03-25 13:37:17 +010071 struct u300_gpio_port ports[U300_GPIO_NUM_PORTS];
Linus Walleijcc890cd2011-09-08 09:04:51 +010072 struct clk *clk;
Linus Walleijcc890cd2011-09-08 09:04:51 +010073 void __iomem *base;
74 struct device *dev;
Linus Walleijcc890cd2011-09-08 09:04:51 +010075 u32 stride;
76 /* Register offsets */
77 u32 pcr;
78 u32 dor;
79 u32 dir;
80 u32 per;
81 u32 icr;
82 u32 ien;
83 u32 iev;
84};
Linus Walleijbd41b992009-04-23 21:15:04 +010085
Linus Walleijcc890cd2011-09-08 09:04:51 +010086/*
87 * Macro to expand to read a specific register found in the "gpio"
88 * struct. It requires the struct u300_gpio *gpio variable to exist in
89 * its context. It calculates the port offset from the given pin
90 * offset, muliplies by the port stride and adds the register offset
91 * so it provides a pointer to the desired register.
92 */
93#define U300_PIN_REG(pin, reg) \
94 (gpio->base + (pin >> 3) * gpio->stride + gpio->reg)
Linus Walleijbd41b992009-04-23 21:15:04 +010095
Linus Walleijcc890cd2011-09-08 09:04:51 +010096/*
97 * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO
98 * register.
99 */
100#define U300_PIN_BIT(pin) \
101 (1 << (pin & 0x07))
Linus Walleijbd41b992009-04-23 21:15:04 +0100102
Linus Walleijcc890cd2011-09-08 09:04:51 +0100103struct u300_gpio_confdata {
104 u16 bias_mode;
105 bool output;
106 int outval;
Linus Walleijbd41b992009-04-23 21:15:04 +0100107};
108
Linus Walleijcc890cd2011-09-08 09:04:51 +0100109#define U300_FLOATING_INPUT { \
Linus Walleija050b3e2011-11-16 20:10:09 +0100110 .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
Linus Walleijcc890cd2011-09-08 09:04:51 +0100111 .output = false, \
112}
Linus Walleijbd41b992009-04-23 21:15:04 +0100113
Linus Walleijcc890cd2011-09-08 09:04:51 +0100114#define U300_PULL_UP_INPUT { \
Linus Walleija050b3e2011-11-16 20:10:09 +0100115 .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \
Linus Walleijcc890cd2011-09-08 09:04:51 +0100116 .output = false, \
117}
Linus Walleijbd41b992009-04-23 21:15:04 +0100118
Linus Walleijcc890cd2011-09-08 09:04:51 +0100119#define U300_OUTPUT_LOW { \
120 .output = true, \
121 .outval = 0, \
122}
Linus Walleijbd41b992009-04-23 21:15:04 +0100123
Linus Walleijcc890cd2011-09-08 09:04:51 +0100124#define U300_OUTPUT_HIGH { \
125 .output = true, \
126 .outval = 1, \
127}
Linus Walleijbd41b992009-04-23 21:15:04 +0100128
Linus Walleijbd41b992009-04-23 21:15:04 +0100129/* Initial configuration */
Uwe Kleine-König122dbe72012-03-30 22:04:51 +0200130static const struct __initconst u300_gpio_confdata
Linus Walleijb263e9b2013-05-23 20:09:43 +0200131bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
Linus Walleijbd41b992009-04-23 21:15:04 +0100132 /* Port 0, pins 0-7 */
133 {
Linus Walleijcc890cd2011-09-08 09:04:51 +0100134 U300_FLOATING_INPUT,
135 U300_OUTPUT_HIGH,
136 U300_FLOATING_INPUT,
137 U300_OUTPUT_LOW,
138 U300_OUTPUT_LOW,
139 U300_OUTPUT_LOW,
140 U300_OUTPUT_LOW,
141 U300_OUTPUT_LOW,
Linus Walleijbd41b992009-04-23 21:15:04 +0100142 },
143 /* Port 1, pins 0-7 */
144 {
Linus Walleijcc890cd2011-09-08 09:04:51 +0100145 U300_OUTPUT_LOW,
146 U300_OUTPUT_LOW,
147 U300_OUTPUT_LOW,
148 U300_PULL_UP_INPUT,
149 U300_FLOATING_INPUT,
150 U300_OUTPUT_HIGH,
151 U300_OUTPUT_LOW,
152 U300_OUTPUT_LOW,
Linus Walleijbd41b992009-04-23 21:15:04 +0100153 },
154 /* Port 2, pins 0-7 */
155 {
Linus Walleijcc890cd2011-09-08 09:04:51 +0100156 U300_FLOATING_INPUT,
157 U300_FLOATING_INPUT,
158 U300_FLOATING_INPUT,
159 U300_FLOATING_INPUT,
160 U300_OUTPUT_LOW,
161 U300_PULL_UP_INPUT,
162 U300_OUTPUT_LOW,
163 U300_PULL_UP_INPUT,
Linus Walleijbd41b992009-04-23 21:15:04 +0100164 },
165 /* Port 3, pins 0-7 */
166 {
Linus Walleijcc890cd2011-09-08 09:04:51 +0100167 U300_PULL_UP_INPUT,
168 U300_OUTPUT_LOW,
169 U300_FLOATING_INPUT,
170 U300_FLOATING_INPUT,
171 U300_FLOATING_INPUT,
172 U300_FLOATING_INPUT,
173 U300_FLOATING_INPUT,
174 U300_FLOATING_INPUT,
Linus Walleijbd41b992009-04-23 21:15:04 +0100175 },
176 /* Port 4, pins 0-7 */
177 {
Linus Walleijcc890cd2011-09-08 09:04:51 +0100178 U300_FLOATING_INPUT,
179 U300_FLOATING_INPUT,
180 U300_FLOATING_INPUT,
181 U300_FLOATING_INPUT,
182 U300_FLOATING_INPUT,
183 U300_FLOATING_INPUT,
184 U300_FLOATING_INPUT,
185 U300_FLOATING_INPUT,
Linus Walleijbd41b992009-04-23 21:15:04 +0100186 },
187 /* Port 5, pins 0-7 */
188 {
Linus Walleijcc890cd2011-09-08 09:04:51 +0100189 U300_FLOATING_INPUT,
190 U300_FLOATING_INPUT,
191 U300_FLOATING_INPUT,
192 U300_FLOATING_INPUT,
193 U300_FLOATING_INPUT,
194 U300_FLOATING_INPUT,
195 U300_FLOATING_INPUT,
196 U300_FLOATING_INPUT,
Linus Walleijbd41b992009-04-23 21:15:04 +0100197 },
198 /* Port 6, pind 0-7 */
199 {
Linus Walleijcc890cd2011-09-08 09:04:51 +0100200 U300_FLOATING_INPUT,
201 U300_FLOATING_INPUT,
202 U300_FLOATING_INPUT,
203 U300_FLOATING_INPUT,
204 U300_FLOATING_INPUT,
205 U300_FLOATING_INPUT,
206 U300_FLOATING_INPUT,
207 U300_FLOATING_INPUT,
Linus Walleijbd41b992009-04-23 21:15:04 +0100208 }
Linus Walleijcc890cd2011-09-08 09:04:51 +0100209};
Linus Walleijbd41b992009-04-23 21:15:04 +0100210
Linus Walleijcc890cd2011-09-08 09:04:51 +0100211/**
212 * to_u300_gpio() - get the pointer to u300_gpio
213 * @chip: the gpio chip member of the structure u300_gpio
Linus Walleijbd41b992009-04-23 21:15:04 +0100214 */
Linus Walleijcc890cd2011-09-08 09:04:51 +0100215static inline struct u300_gpio *to_u300_gpio(struct gpio_chip *chip)
Linus Walleijbd41b992009-04-23 21:15:04 +0100216{
Linus Walleijcc890cd2011-09-08 09:04:51 +0100217 return container_of(chip, struct u300_gpio, chip);
Linus Walleijbd41b992009-04-23 21:15:04 +0100218}
Linus Walleijbd41b992009-04-23 21:15:04 +0100219
Linus Walleijb4e3ac72011-11-16 10:24:39 +0100220static int u300_gpio_request(struct gpio_chip *chip, unsigned offset)
221{
222 /*
223 * Map back to global GPIO space and request muxing, the direction
224 * parameter does not matter for this controller.
225 */
226 int gpio = chip->base + offset;
227
Linus Walleije93bcee2012-02-09 07:23:28 +0100228 return pinctrl_request_gpio(gpio);
Linus Walleijb4e3ac72011-11-16 10:24:39 +0100229}
230
231static void u300_gpio_free(struct gpio_chip *chip, unsigned offset)
232{
233 int gpio = chip->base + offset;
234
Linus Walleije93bcee2012-02-09 07:23:28 +0100235 pinctrl_free_gpio(gpio);
Linus Walleijb4e3ac72011-11-16 10:24:39 +0100236}
237
Linus Walleijcc890cd2011-09-08 09:04:51 +0100238static int u300_gpio_get(struct gpio_chip *chip, unsigned offset)
Linus Walleijbd41b992009-04-23 21:15:04 +0100239{
Linus Walleijcc890cd2011-09-08 09:04:51 +0100240 struct u300_gpio *gpio = to_u300_gpio(chip);
Linus Walleijbd41b992009-04-23 21:15:04 +0100241
Linus Walleijcc890cd2011-09-08 09:04:51 +0100242 return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset);
Linus Walleijbd41b992009-04-23 21:15:04 +0100243}
Linus Walleijbd41b992009-04-23 21:15:04 +0100244
Linus Walleijcc890cd2011-09-08 09:04:51 +0100245static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
Linus Walleijee179622009-09-28 12:36:18 +0100246{
Linus Walleijcc890cd2011-09-08 09:04:51 +0100247 struct u300_gpio *gpio = to_u300_gpio(chip);
248 unsigned long flags;
249 u32 val;
Linus Walleijee179622009-09-28 12:36:18 +0100250
Linus Walleijcc890cd2011-09-08 09:04:51 +0100251 local_irq_save(flags);
252
253 val = readl(U300_PIN_REG(offset, dor));
254 if (value)
255 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
Linus Walleijbd41b992009-04-23 21:15:04 +0100256 else
Linus Walleijcc890cd2011-09-08 09:04:51 +0100257 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
Linus Walleijbd41b992009-04-23 21:15:04 +0100258
Linus Walleijbd41b992009-04-23 21:15:04 +0100259 local_irq_restore(flags);
260}
Linus Walleijbd41b992009-04-23 21:15:04 +0100261
Linus Walleijcc890cd2011-09-08 09:04:51 +0100262static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
Linus Walleijbd41b992009-04-23 21:15:04 +0100263{
Linus Walleijcc890cd2011-09-08 09:04:51 +0100264 struct u300_gpio *gpio = to_u300_gpio(chip);
Linus Walleijbd41b992009-04-23 21:15:04 +0100265 unsigned long flags;
266 u32 val;
267
Linus Walleijbd41b992009-04-23 21:15:04 +0100268 local_irq_save(flags);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100269 val = readl(U300_PIN_REG(offset, pcr));
270 /* Mask out this pin, note 2 bits per setting */
271 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
272 writel(val, U300_PIN_REG(offset, pcr));
Linus Walleijbd41b992009-04-23 21:15:04 +0100273 local_irq_restore(flags);
274 return 0;
275}
Linus Walleijbd41b992009-04-23 21:15:04 +0100276
Linus Walleijcc890cd2011-09-08 09:04:51 +0100277static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
278 int value)
Linus Walleijbd41b992009-04-23 21:15:04 +0100279{
Linus Walleijcc890cd2011-09-08 09:04:51 +0100280 struct u300_gpio *gpio = to_u300_gpio(chip);
Linus Walleijbd41b992009-04-23 21:15:04 +0100281 unsigned long flags;
Linus Walleijcc890cd2011-09-08 09:04:51 +0100282 u32 oldmode;
Linus Walleijbd41b992009-04-23 21:15:04 +0100283 u32 val;
284
Linus Walleijbd41b992009-04-23 21:15:04 +0100285 local_irq_save(flags);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100286 val = readl(U300_PIN_REG(offset, pcr));
Linus Walleijbd41b992009-04-23 21:15:04 +0100287 /*
Linus Walleijcc890cd2011-09-08 09:04:51 +0100288 * Drive mode must be set by the special mode set function, set
289 * push/pull mode by default if no mode has been selected.
Linus Walleijbd41b992009-04-23 21:15:04 +0100290 */
Linus Walleijcc890cd2011-09-08 09:04:51 +0100291 oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK <<
292 ((offset & 0x07) << 1));
293 /* mode = 0 means input, else some mode is already set */
294 if (oldmode == 0) {
295 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK <<
296 ((offset & 0x07) << 1));
297 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
298 << ((offset & 0x07) << 1));
299 writel(val, U300_PIN_REG(offset, pcr));
300 }
301 u300_gpio_set(chip, offset, value);
Linus Walleijbd41b992009-04-23 21:15:04 +0100302 local_irq_restore(flags);
303 return 0;
304}
Linus Walleijbd41b992009-04-23 21:15:04 +0100305
Linus Walleijdc0b1aa2011-11-16 21:58:10 +0100306/* Returning -EINVAL means "supported but not available" */
307int u300_gpio_config_get(struct gpio_chip *chip,
308 unsigned offset,
309 unsigned long *config)
310{
311 struct u300_gpio *gpio = to_u300_gpio(chip);
312 enum pin_config_param param = (enum pin_config_param) *config;
313 bool biasmode;
314 u32 drmode;
315
316 /* One bit per pin, clamp to bool range */
317 biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset));
318
319 /* Mask out the two bits for this pin and shift to bits 0,1 */
320 drmode = readl(U300_PIN_REG(offset, pcr));
321 drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
322 drmode >>= ((offset & 0x07) << 1);
323
Sachin Kamat8b0ef252013-03-15 10:39:52 +0530324 switch (param) {
Linus Walleijdc0b1aa2011-11-16 21:58:10 +0100325 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
326 *config = 0;
327 if (biasmode)
328 return 0;
329 else
330 return -EINVAL;
331 break;
332 case PIN_CONFIG_BIAS_PULL_UP:
333 *config = 0;
334 if (!biasmode)
335 return 0;
336 else
337 return -EINVAL;
338 break;
339 case PIN_CONFIG_DRIVE_PUSH_PULL:
340 *config = 0;
341 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL)
342 return 0;
343 else
344 return -EINVAL;
345 break;
346 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
347 *config = 0;
348 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN)
349 return 0;
350 else
351 return -EINVAL;
352 break;
353 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
354 *config = 0;
355 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE)
356 return 0;
357 else
358 return -EINVAL;
359 break;
360 default:
361 break;
362 }
363 return -ENOTSUPP;
364}
365
366int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
367 enum pin_config_param param)
Linus Walleijbd41b992009-04-23 21:15:04 +0100368{
Linus Walleijcc890cd2011-09-08 09:04:51 +0100369 struct u300_gpio *gpio = to_u300_gpio(chip);
Linus Walleijbd41b992009-04-23 21:15:04 +0100370 unsigned long flags;
Linus Walleijcc890cd2011-09-08 09:04:51 +0100371 u32 val;
Linus Walleijbd41b992009-04-23 21:15:04 +0100372
373 local_irq_save(flags);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100374 switch (param) {
Linus Walleija050b3e2011-11-16 20:10:09 +0100375 case PIN_CONFIG_BIAS_DISABLE:
376 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
Linus Walleijcc890cd2011-09-08 09:04:51 +0100377 val = readl(U300_PIN_REG(offset, per));
378 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
379 break;
Linus Walleija050b3e2011-11-16 20:10:09 +0100380 case PIN_CONFIG_BIAS_PULL_UP:
Linus Walleijcc890cd2011-09-08 09:04:51 +0100381 val = readl(U300_PIN_REG(offset, per));
382 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
383 break;
Linus Walleija050b3e2011-11-16 20:10:09 +0100384 case PIN_CONFIG_DRIVE_PUSH_PULL:
Linus Walleijcc890cd2011-09-08 09:04:51 +0100385 val = readl(U300_PIN_REG(offset, pcr));
386 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
387 << ((offset & 0x07) << 1));
388 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
389 << ((offset & 0x07) << 1));
390 writel(val, U300_PIN_REG(offset, pcr));
391 break;
Linus Walleija050b3e2011-11-16 20:10:09 +0100392 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
Linus Walleijcc890cd2011-09-08 09:04:51 +0100393 val = readl(U300_PIN_REG(offset, pcr));
394 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
395 << ((offset & 0x07) << 1));
396 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN
397 << ((offset & 0x07) << 1));
398 writel(val, U300_PIN_REG(offset, pcr));
399 break;
Linus Walleija050b3e2011-11-16 20:10:09 +0100400 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
Linus Walleijcc890cd2011-09-08 09:04:51 +0100401 val = readl(U300_PIN_REG(offset, pcr));
402 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
403 << ((offset & 0x07) << 1));
404 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE
405 << ((offset & 0x07) << 1));
406 writel(val, U300_PIN_REG(offset, pcr));
407 break;
408 default:
Linus Walleijbd41b992009-04-23 21:15:04 +0100409 local_irq_restore(flags);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100410 dev_err(gpio->dev, "illegal configuration requested\n");
411 return -EINVAL;
412 }
413 local_irq_restore(flags);
414 return 0;
415}
416
417static struct gpio_chip u300_gpio_chip = {
418 .label = "u300-gpio-chip",
419 .owner = THIS_MODULE,
Linus Walleijb4e3ac72011-11-16 10:24:39 +0100420 .request = u300_gpio_request,
421 .free = u300_gpio_free,
Linus Walleijcc890cd2011-09-08 09:04:51 +0100422 .get = u300_gpio_get,
423 .set = u300_gpio_set,
424 .direction_input = u300_gpio_direction_input,
425 .direction_output = u300_gpio_direction_output,
Linus Walleijcc890cd2011-09-08 09:04:51 +0100426};
427
428static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset)
429{
430 u32 val;
431
432 val = readl(U300_PIN_REG(offset, icr));
433 /* Set mode depending on state */
434 if (u300_gpio_get(&gpio->chip, offset)) {
435 /* High now, let's trigger on falling edge next then */
436 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
437 dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n",
438 offset);
439 } else {
440 /* Low now, let's trigger on rising edge next then */
441 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
442 dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n",
443 offset);
444 }
445}
446
447static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger)
448{
Linus Walleij523dcce2014-03-25 13:37:17 +0100449 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
450 struct u300_gpio *gpio = to_u300_gpio(chip);
451 struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3];
452 int offset = d->hwirq;
Linus Walleijcc890cd2011-09-08 09:04:51 +0100453 u32 val;
454
455 if ((trigger & IRQF_TRIGGER_RISING) &&
456 (trigger & IRQF_TRIGGER_FALLING)) {
457 /*
458 * The GPIO block can only trigger on falling OR rising edges,
459 * not both. So we need to toggle the mode whenever the pin
460 * goes from one state to the other with a special state flag
461 */
462 dev_dbg(gpio->dev,
463 "trigger on both rising and falling edge on pin %d\n",
464 offset);
465 port->toggle_edge_mode |= U300_PIN_BIT(offset);
466 u300_toggle_trigger(gpio, offset);
467 } else if (trigger & IRQF_TRIGGER_RISING) {
468 dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n",
469 offset);
470 val = readl(U300_PIN_REG(offset, icr));
471 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
472 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
473 } else if (trigger & IRQF_TRIGGER_FALLING) {
474 dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n",
475 offset);
476 val = readl(U300_PIN_REG(offset, icr));
477 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
478 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
Linus Walleijbd41b992009-04-23 21:15:04 +0100479 }
480
Linus Walleijcc890cd2011-09-08 09:04:51 +0100481 return 0;
482}
Linus Walleijbd41b992009-04-23 21:15:04 +0100483
Linus Walleijcc890cd2011-09-08 09:04:51 +0100484static void u300_gpio_irq_enable(struct irq_data *d)
485{
Linus Walleij523dcce2014-03-25 13:37:17 +0100486 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
487 struct u300_gpio *gpio = to_u300_gpio(chip);
488 struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3];
489 int offset = d->hwirq;
Linus Walleijcc890cd2011-09-08 09:04:51 +0100490 u32 val;
491 unsigned long flags;
492
Linus Walleija6c45b92012-10-17 18:31:20 +0200493 dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n",
494 d->hwirq, port->name, offset);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100495 local_irq_save(flags);
496 val = readl(U300_PIN_REG(offset, ien));
497 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
498 local_irq_restore(flags);
499}
500
501static void u300_gpio_irq_disable(struct irq_data *d)
502{
Linus Walleij523dcce2014-03-25 13:37:17 +0100503 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
504 struct u300_gpio *gpio = to_u300_gpio(chip);
505 int offset = d->hwirq;
Linus Walleijcc890cd2011-09-08 09:04:51 +0100506 u32 val;
507 unsigned long flags;
508
509 local_irq_save(flags);
510 val = readl(U300_PIN_REG(offset, ien));
511 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
512 local_irq_restore(flags);
Linus Walleij8c1d50a2014-03-14 18:24:30 +0100513}
514
Linus Walleijcc890cd2011-09-08 09:04:51 +0100515static struct irq_chip u300_gpio_irqchip = {
516 .name = "u300-gpio-irqchip",
517 .irq_enable = u300_gpio_irq_enable,
518 .irq_disable = u300_gpio_irq_disable,
519 .irq_set_type = u300_gpio_irq_type,
Linus Walleijcc890cd2011-09-08 09:04:51 +0100520};
521
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200522static void u300_gpio_irq_handler(struct irq_desc *desc)
Linus Walleijcc890cd2011-09-08 09:04:51 +0100523{
Thomas Gleixnerfc02a462015-07-13 01:50:02 +0200524 unsigned int irq = irq_desc_get_irq(desc);
Jiang Liu5663bb22015-06-04 12:13:16 +0800525 struct irq_chip *parent_chip = irq_desc_get_chip(desc);
526 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
Linus Walleij523dcce2014-03-25 13:37:17 +0100527 struct u300_gpio *gpio = to_u300_gpio(chip);
528 struct u300_gpio_port *port = &gpio->ports[irq - chip->base];
Linus Walleijcc890cd2011-09-08 09:04:51 +0100529 int pinoffset = port->number << 3; /* get the right stride */
530 unsigned long val;
531
Linus Walleij523dcce2014-03-25 13:37:17 +0100532 chained_irq_enter(parent_chip, desc);
533
Linus Walleijcc890cd2011-09-08 09:04:51 +0100534 /* Read event register */
535 val = readl(U300_PIN_REG(pinoffset, iev));
536 /* Mask relevant bits */
537 val &= 0xFFU; /* 8 bits per port */
538 /* ACK IRQ (clear event) */
539 writel(val, U300_PIN_REG(pinoffset, iev));
540
541 /* Call IRQ handler */
542 if (val != 0) {
543 int irqoffset;
544
545 for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
Linus Walleijcc890cd2011-09-08 09:04:51 +0100546 int offset = pinoffset + irqoffset;
Linus Walleij523dcce2014-03-25 13:37:17 +0100547 int pin_irq = irq_find_mapping(chip->irqdomain, offset);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100548
549 dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
550 pin_irq, offset);
551 generic_handle_irq(pin_irq);
552 /*
553 * Triggering IRQ on both rising and falling edge
554 * needs mockery
555 */
556 if (port->toggle_edge_mode & U300_PIN_BIT(offset))
557 u300_toggle_trigger(gpio, offset);
Linus Walleijbd41b992009-04-23 21:15:04 +0100558 }
559 }
560
Linus Walleij523dcce2014-03-25 13:37:17 +0100561 chained_irq_exit(parent_chip, desc);
Linus Walleijbd41b992009-04-23 21:15:04 +0100562}
563
Linus Walleijcc890cd2011-09-08 09:04:51 +0100564static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
565 int offset,
566 const struct u300_gpio_confdata *conf)
Linus Walleijbd41b992009-04-23 21:15:04 +0100567{
Linus Walleijcc890cd2011-09-08 09:04:51 +0100568 /* Set mode: input or output */
569 if (conf->output) {
570 u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
Linus Walleijbd41b992009-04-23 21:15:04 +0100571
Linus Walleijcc890cd2011-09-08 09:04:51 +0100572 /* Deactivate bias mode for output */
Linus Walleijdc0b1aa2011-11-16 21:58:10 +0100573 u300_gpio_config_set(&gpio->chip, offset,
574 PIN_CONFIG_BIAS_HIGH_IMPEDANCE);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100575
576 /* Set drive mode for output */
Linus Walleijdc0b1aa2011-11-16 21:58:10 +0100577 u300_gpio_config_set(&gpio->chip, offset,
578 PIN_CONFIG_DRIVE_PUSH_PULL);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100579
580 dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
581 offset, conf->outval);
582 } else {
583 u300_gpio_direction_input(&gpio->chip, offset);
584
585 /* Always set output low on input pins */
586 u300_gpio_set(&gpio->chip, offset, 0);
587
588 /* Set bias mode for input */
Linus Walleijdc0b1aa2011-11-16 21:58:10 +0100589 u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100590
591 dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
592 offset, conf->bias_mode);
593 }
594}
595
Linus Walleijb263e9b2013-05-23 20:09:43 +0200596static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio)
Linus Walleijcc890cd2011-09-08 09:04:51 +0100597{
598 int i, j;
599
600 /* Write default config and values to all pins */
Linus Walleijb263e9b2013-05-23 20:09:43 +0200601 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
Linus Walleijcc890cd2011-09-08 09:04:51 +0100602 for (j = 0; j < 8; j++) {
603 const struct u300_gpio_confdata *conf;
604 int offset = (i*8) + j;
605
Linus Walleij04b13de2012-08-13 10:36:55 +0200606 conf = &bs335_gpio_config[i][j];
Linus Walleijcc890cd2011-09-08 09:04:51 +0100607 u300_gpio_init_pin(gpio, offset, conf);
608 }
609 }
610}
611
Linus Walleij387923c2012-11-20 14:28:07 +0100612/*
613 * Here we map a GPIO in the local gpio_chip pin space to a pin in
614 * the local pinctrl pin space. The pin controller used is
615 * pinctrl-u300.
616 */
617struct coh901_pinpair {
618 unsigned int offset;
619 unsigned int pin_base;
620};
621
622#define COH901_PINRANGE(a, b) { .offset = a, .pin_base = b }
623
624static struct coh901_pinpair coh901_pintable[] = {
625 COH901_PINRANGE(10, 426),
626 COH901_PINRANGE(11, 180),
627 COH901_PINRANGE(12, 165), /* MS/MMC card insertion */
628 COH901_PINRANGE(13, 179),
629 COH901_PINRANGE(14, 178),
630 COH901_PINRANGE(16, 194),
631 COH901_PINRANGE(17, 193),
632 COH901_PINRANGE(18, 192),
633 COH901_PINRANGE(19, 191),
634 COH901_PINRANGE(20, 186),
635 COH901_PINRANGE(21, 185),
636 COH901_PINRANGE(22, 184),
637 COH901_PINRANGE(23, 183),
638 COH901_PINRANGE(24, 182),
639 COH901_PINRANGE(25, 181),
640};
641
Linus Walleijcc890cd2011-09-08 09:04:51 +0100642static int __init u300_gpio_probe(struct platform_device *pdev)
643{
Linus Walleijcc890cd2011-09-08 09:04:51 +0100644 struct u300_gpio *gpio;
Linus Walleij585583f2012-10-17 18:49:05 +0200645 struct resource *memres;
Linus Walleijcc890cd2011-09-08 09:04:51 +0100646 int err = 0;
647 int portno;
648 u32 val;
649 u32 ifr;
650 int i;
651
Linus Walleij585583f2012-10-17 18:49:05 +0200652 gpio = devm_kzalloc(&pdev->dev, sizeof(struct u300_gpio), GFP_KERNEL);
653 if (gpio == NULL)
Linus Walleijcc890cd2011-09-08 09:04:51 +0100654 return -ENOMEM;
Linus Walleijcc890cd2011-09-08 09:04:51 +0100655
656 gpio->chip = u300_gpio_chip;
Linus Walleijb263e9b2013-05-23 20:09:43 +0200657 gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT;
Linus Walleijcc890cd2011-09-08 09:04:51 +0100658 gpio->chip.dev = &pdev->dev;
Linus Walleijb263e9b2013-05-23 20:09:43 +0200659 gpio->chip.base = 0;
Linus Walleijcc890cd2011-09-08 09:04:51 +0100660 gpio->dev = &pdev->dev;
Linus Walleijbd41b992009-04-23 21:15:04 +0100661
Linus Walleij585583f2012-10-17 18:49:05 +0200662 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Thierry Reding9e0c1fb2013-01-21 11:09:14 +0100663 gpio->base = devm_ioremap_resource(&pdev->dev, memres);
664 if (IS_ERR(gpio->base))
665 return PTR_ERR(gpio->base);
Linus Walleij585583f2012-10-17 18:49:05 +0200666
667 gpio->clk = devm_clk_get(gpio->dev, NULL);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100668 if (IS_ERR(gpio->clk)) {
669 err = PTR_ERR(gpio->clk);
670 dev_err(gpio->dev, "could not get GPIO clock\n");
Linus Walleij585583f2012-10-17 18:49:05 +0200671 return err;
Linus Walleijbd41b992009-04-23 21:15:04 +0100672 }
Linus Walleij585583f2012-10-17 18:49:05 +0200673
Linus Walleij27e84612012-06-19 23:36:15 +0200674 err = clk_prepare_enable(gpio->clk);
Linus Walleijbd41b992009-04-23 21:15:04 +0100675 if (err) {
Linus Walleijcc890cd2011-09-08 09:04:51 +0100676 dev_err(gpio->dev, "could not enable GPIO clock\n");
Linus Walleij585583f2012-10-17 18:49:05 +0200677 return err;
Linus Walleijbd41b992009-04-23 21:15:04 +0100678 }
679
Linus Walleij04b13de2012-08-13 10:36:55 +0200680 dev_info(gpio->dev,
681 "initializing GPIO Controller COH 901 571/3\n");
682 gpio->stride = U300_GPIO_PORT_STRIDE;
683 gpio->pcr = U300_GPIO_PXPCR;
684 gpio->dor = U300_GPIO_PXPDOR;
685 gpio->dir = U300_GPIO_PXPDIR;
686 gpio->per = U300_GPIO_PXPER;
687 gpio->icr = U300_GPIO_PXICR;
688 gpio->ien = U300_GPIO_PXIEN;
689 gpio->iev = U300_GPIO_PXIEV;
690 ifr = U300_GPIO_PXIFR;
Linus Walleijbd41b992009-04-23 21:15:04 +0100691
Linus Walleij04b13de2012-08-13 10:36:55 +0200692 val = readl(gpio->base + U300_GPIO_CR);
693 dev_info(gpio->dev, "COH901571/3 block version: %d, " \
694 "number of cores: %d totalling %d pins\n",
695 ((val & 0x000001FC) >> 2),
696 ((val & 0x0000FE00) >> 9),
697 ((val & 0x0000FE00) >> 9) * 8);
698 writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
699 gpio->base + U300_GPIO_CR);
Linus Walleijb263e9b2013-05-23 20:09:43 +0200700 u300_gpio_init_coh901571(gpio);
Linus Walleijbd41b992009-04-23 21:15:04 +0100701
Linus Walleij351c2162013-04-10 10:49:31 +0200702#ifdef CONFIG_OF_GPIO
703 gpio->chip.of_node = pdev->dev.of_node;
704#endif
Linus Walleijcc890cd2011-09-08 09:04:51 +0100705 err = gpiochip_add(&gpio->chip);
706 if (err) {
707 dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
708 goto err_no_chip;
709 }
710
Linus Walleij523dcce2014-03-25 13:37:17 +0100711 err = gpiochip_irqchip_add(&gpio->chip,
712 &u300_gpio_irqchip,
713 0,
714 handle_simple_irq,
715 IRQ_TYPE_EDGE_FALLING);
716 if (err) {
717 dev_err(gpio->dev, "no GPIO irqchip\n");
718 goto err_no_irqchip;
719 }
720
721 /* Add each port with its IRQ separately */
722 for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) {
723 struct u300_gpio_port *port = &gpio->ports[portno];
724
725 snprintf(port->name, 8, "gpio%d", portno);
726 port->number = portno;
727 port->gpio = gpio;
728
729 port->irq = platform_get_irq(pdev, portno);
730
731 gpiochip_set_chained_irqchip(&gpio->chip,
732 &u300_gpio_irqchip,
733 port->irq,
734 u300_gpio_irq_handler);
735
736 /* Turns off irq force (test register) for this port */
737 writel(0x0, gpio->base + portno * gpio->stride + ifr);
738 }
739 dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno);
740
Linus Walleij387923c2012-11-20 14:28:07 +0100741 /*
742 * Add pinctrl pin ranges, the pin controller must be registered
743 * at this point
744 */
745 for (i = 0; i < ARRAY_SIZE(coh901_pintable); i++) {
746 struct coh901_pinpair *p = &coh901_pintable[i];
747
748 err = gpiochip_add_pin_range(&gpio->chip, "pinctrl-u300",
749 p->offset, p->pin_base, 1);
750 if (err)
751 goto err_no_range;
752 }
753
Linus Walleijcc890cd2011-09-08 09:04:51 +0100754 platform_set_drvdata(pdev, gpio);
755
Linus Walleijbd41b992009-04-23 21:15:04 +0100756 return 0;
757
Linus Walleij387923c2012-11-20 14:28:07 +0100758err_no_range:
Linus Walleij523dcce2014-03-25 13:37:17 +0100759err_no_irqchip:
abdoulaye bertheb4e7c552014-07-12 22:30:13 +0200760 gpiochip_remove(&gpio->chip);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100761err_no_chip:
Linus Walleij27e84612012-06-19 23:36:15 +0200762 clk_disable_unprepare(gpio->clk);
Axel Lin80357202012-11-14 00:16:14 +0800763 dev_err(&pdev->dev, "module ERROR:%d\n", err);
Linus Walleijbd41b992009-04-23 21:15:04 +0100764 return err;
765}
766
Linus Walleijcc890cd2011-09-08 09:04:51 +0100767static int __exit u300_gpio_remove(struct platform_device *pdev)
Linus Walleijbd41b992009-04-23 21:15:04 +0100768{
Linus Walleijcc890cd2011-09-08 09:04:51 +0100769 struct u300_gpio *gpio = platform_get_drvdata(pdev);
Linus Walleijbd41b992009-04-23 21:15:04 +0100770
771 /* Turn off the GPIO block */
Linus Walleij04b13de2012-08-13 10:36:55 +0200772 writel(0x00000000U, gpio->base + U300_GPIO_CR);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100773
abdoulaye bertheb4e7c552014-07-12 22:30:13 +0200774 gpiochip_remove(&gpio->chip);
Linus Walleij27e84612012-06-19 23:36:15 +0200775 clk_disable_unprepare(gpio->clk);
Linus Walleijbd41b992009-04-23 21:15:04 +0100776 return 0;
777}
778
Linus Walleij351c2162013-04-10 10:49:31 +0200779static const struct of_device_id u300_gpio_match[] = {
780 { .compatible = "stericsson,gpio-coh901" },
781 {},
782};
783
Linus Walleijcc890cd2011-09-08 09:04:51 +0100784static struct platform_driver u300_gpio_driver = {
Linus Walleijbd41b992009-04-23 21:15:04 +0100785 .driver = {
786 .name = "u300-gpio",
Linus Walleij351c2162013-04-10 10:49:31 +0200787 .of_match_table = u300_gpio_match,
Linus Walleijbd41b992009-04-23 21:15:04 +0100788 },
Linus Walleijcc890cd2011-09-08 09:04:51 +0100789 .remove = __exit_p(u300_gpio_remove),
Linus Walleijbd41b992009-04-23 21:15:04 +0100790};
791
Linus Walleijbd41b992009-04-23 21:15:04 +0100792static int __init u300_gpio_init(void)
793{
Linus Walleijcc890cd2011-09-08 09:04:51 +0100794 return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe);
Linus Walleijbd41b992009-04-23 21:15:04 +0100795}
796
797static void __exit u300_gpio_exit(void)
798{
Linus Walleijcc890cd2011-09-08 09:04:51 +0100799 platform_driver_unregister(&u300_gpio_driver);
Linus Walleijbd41b992009-04-23 21:15:04 +0100800}
801
802arch_initcall(u300_gpio_init);
803module_exit(u300_gpio_exit);
804
805MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
Linus Walleijcc890cd2011-09-08 09:04:51 +0100806MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver");
Linus Walleijbd41b992009-04-23 21:15:04 +0100807MODULE_LICENSE("GPL");