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Felipe Balbi550a7372008-07-24 12:27:36 +03001/*
2 * MUSB OTG driver peripheral support
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
Sergei Shtylyovcea83242009-11-18 22:51:18 +03007 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
Felipe Balbi550a7372008-07-24 12:27:36 +03008 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
35
36#include <linux/kernel.h>
37#include <linux/list.h>
38#include <linux/timer.h>
39#include <linux/module.h>
40#include <linux/smp.h>
41#include <linux/spinlock.h>
42#include <linux/delay.h>
43#include <linux/moduleparam.h>
44#include <linux/stat.h>
45#include <linux/dma-mapping.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090046#include <linux/slab.h>
Felipe Balbi550a7372008-07-24 12:27:36 +030047
48#include "musb_core.h"
49
50
51/* MUSB PERIPHERAL status 3-mar-2006:
52 *
53 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
54 * Minor glitches:
55 *
56 * + remote wakeup to Linux hosts work, but saw USBCV failures;
57 * in one test run (operator error?)
58 * + endpoint halt tests -- in both usbtest and usbcv -- seem
59 * to break when dma is enabled ... is something wrongly
60 * clearing SENDSTALL?
61 *
62 * - Mass storage behaved ok when last tested. Network traffic patterns
63 * (with lots of short transfers etc) need retesting; they turn up the
64 * worst cases of the DMA, since short packets are typical but are not
65 * required.
66 *
67 * - TX/IN
68 * + both pio and dma behave in with network and g_zero tests
69 * + no cppi throughput issues other than no-hw-queueing
70 * + failed with FLAT_REG (DaVinci)
71 * + seems to behave with double buffering, PIO -and- CPPI
72 * + with gadgetfs + AIO, requests got lost?
73 *
74 * - RX/OUT
75 * + both pio and dma behave in with network and g_zero tests
76 * + dma is slow in typical case (short_not_ok is clear)
77 * + double buffering ok with PIO
78 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
79 * + request lossage observed with gadgetfs
80 *
81 * - ISO not tested ... might work, but only weakly isochronous
82 *
83 * - Gadget driver disabling of softconnect during bind() is ignored; so
84 * drivers can't hold off host requests until userspace is ready.
85 * (Workaround: they can turn it off later.)
86 *
87 * - PORTABILITY (assumes PIO works):
88 * + DaVinci, basically works with cppi dma
89 * + OMAP 2430, ditto with mentor dma
90 * + TUSB 6010, platform-specific dma in the works
91 */
92
93/* ----------------------------------------------------------------------- */
94
95/*
96 * Immediately complete a request.
97 *
98 * @param request the request to complete
99 * @param status the status to complete the request with
100 * Context: controller locked, IRQs blocked.
101 */
102void musb_g_giveback(
103 struct musb_ep *ep,
104 struct usb_request *request,
105 int status)
106__releases(ep->musb->lock)
107__acquires(ep->musb->lock)
108{
109 struct musb_request *req;
110 struct musb *musb;
111 int busy = ep->busy;
112
113 req = to_musb_request(request);
114
115 list_del(&request->list);
116 if (req->request.status == -EINPROGRESS)
117 req->request.status = status;
118 musb = req->musb;
119
120 ep->busy = 1;
121 spin_unlock(&musb->lock);
122 if (is_dma_capable()) {
123 if (req->mapped) {
124 dma_unmap_single(musb->controller,
125 req->request.dma,
126 req->request.length,
127 req->tx
128 ? DMA_TO_DEVICE
129 : DMA_FROM_DEVICE);
130 req->request.dma = DMA_ADDR_INVALID;
131 req->mapped = 0;
132 } else if (req->request.dma != DMA_ADDR_INVALID)
133 dma_sync_single_for_cpu(musb->controller,
134 req->request.dma,
135 req->request.length,
136 req->tx
137 ? DMA_TO_DEVICE
138 : DMA_FROM_DEVICE);
139 }
140 if (request->status == 0)
141 DBG(5, "%s done request %p, %d/%d\n",
142 ep->end_point.name, request,
143 req->request.actual, req->request.length);
144 else
145 DBG(2, "%s request %p, %d/%d fault %d\n",
146 ep->end_point.name, request,
147 req->request.actual, req->request.length,
148 request->status);
149 req->request.complete(&req->ep->end_point, &req->request);
150 spin_lock(&musb->lock);
151 ep->busy = busy;
152}
153
154/* ----------------------------------------------------------------------- */
155
156/*
157 * Abort requests queued to an endpoint using the status. Synchronous.
158 * caller locked controller and blocked irqs, and selected this ep.
159 */
160static void nuke(struct musb_ep *ep, const int status)
161{
162 struct musb_request *req = NULL;
163 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
164
165 ep->busy = 1;
166
167 if (is_dma_capable() && ep->dma) {
168 struct dma_controller *c = ep->musb->dma_controller;
169 int value;
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700170
Felipe Balbi550a7372008-07-24 12:27:36 +0300171 if (ep->is_in) {
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700172 /*
173 * The programming guide says that we must not clear
174 * the DMAMODE bit before DMAENAB, so we only
175 * clear it in the second write...
176 */
Felipe Balbi550a7372008-07-24 12:27:36 +0300177 musb_writew(epio, MUSB_TXCSR,
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700178 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
Felipe Balbi550a7372008-07-24 12:27:36 +0300179 musb_writew(epio, MUSB_TXCSR,
180 0 | MUSB_TXCSR_FLUSHFIFO);
181 } else {
182 musb_writew(epio, MUSB_RXCSR,
183 0 | MUSB_RXCSR_FLUSHFIFO);
184 musb_writew(epio, MUSB_RXCSR,
185 0 | MUSB_RXCSR_FLUSHFIFO);
186 }
187
188 value = c->channel_abort(ep->dma);
189 DBG(value ? 1 : 6, "%s: abort DMA --> %d\n", ep->name, value);
190 c->channel_release(ep->dma);
191 ep->dma = NULL;
192 }
193
194 while (!list_empty(&(ep->req_list))) {
195 req = container_of(ep->req_list.next, struct musb_request,
196 request.list);
197 musb_g_giveback(ep, &req->request, status);
198 }
199}
200
201/* ----------------------------------------------------------------------- */
202
203/* Data transfers - pure PIO, pure DMA, or mixed mode */
204
205/*
206 * This assumes the separate CPPI engine is responding to DMA requests
207 * from the usb core ... sequenced a bit differently from mentor dma.
208 */
209
210static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
211{
212 if (can_bulk_split(musb, ep->type))
213 return ep->hw_ep->max_packet_sz_tx;
214 else
215 return ep->packet_sz;
216}
217
218
219#ifdef CONFIG_USB_INVENTRA_DMA
220
221/* Peripheral tx (IN) using Mentor DMA works as follows:
222 Only mode 0 is used for transfers <= wPktSize,
223 mode 1 is used for larger transfers,
224
225 One of the following happens:
226 - Host sends IN token which causes an endpoint interrupt
227 -> TxAvail
228 -> if DMA is currently busy, exit.
229 -> if queue is non-empty, txstate().
230
231 - Request is queued by the gadget driver.
232 -> if queue was previously empty, txstate()
233
234 txstate()
235 -> start
236 /\ -> setup DMA
237 | (data is transferred to the FIFO, then sent out when
238 | IN token(s) are recd from Host.
239 | -> DMA interrupt on completion
240 | calls TxAvail.
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700241 | -> stop DMA, ~DMAENAB,
Felipe Balbi550a7372008-07-24 12:27:36 +0300242 | -> set TxPktRdy for last short pkt or zlp
243 | -> Complete Request
244 | -> Continue next request (call txstate)
245 |___________________________________|
246
247 * Non-Mentor DMA engines can of course work differently, such as by
248 * upleveling from irq-per-packet to irq-per-buffer.
249 */
250
251#endif
252
253/*
254 * An endpoint is transmitting data. This can be called either from
255 * the IRQ routine or from ep.queue() to kickstart a request on an
256 * endpoint.
257 *
258 * Context: controller locked, IRQs blocked, endpoint selected
259 */
260static void txstate(struct musb *musb, struct musb_request *req)
261{
262 u8 epnum = req->epnum;
263 struct musb_ep *musb_ep;
264 void __iomem *epio = musb->endpoints[epnum].regs;
265 struct usb_request *request;
266 u16 fifo_count = 0, csr;
267 int use_dma = 0;
268
269 musb_ep = req->ep;
270
271 /* we shouldn't get here while DMA is active ... but we do ... */
272 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
273 DBG(4, "dma pending...\n");
274 return;
275 }
276
277 /* read TXCSR before */
278 csr = musb_readw(epio, MUSB_TXCSR);
279
280 request = &req->request;
281 fifo_count = min(max_ep_writesize(musb, musb_ep),
282 (int)(request->length - request->actual));
283
284 if (csr & MUSB_TXCSR_TXPKTRDY) {
285 DBG(5, "%s old packet still ready , txcsr %03x\n",
286 musb_ep->end_point.name, csr);
287 return;
288 }
289
290 if (csr & MUSB_TXCSR_P_SENDSTALL) {
291 DBG(5, "%s stalling, txcsr %03x\n",
292 musb_ep->end_point.name, csr);
293 return;
294 }
295
296 DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
297 epnum, musb_ep->packet_sz, fifo_count,
298 csr);
299
300#ifndef CONFIG_MUSB_PIO_ONLY
301 if (is_dma_capable() && musb_ep->dma) {
302 struct dma_controller *c = musb->dma_controller;
303
304 use_dma = (request->dma != DMA_ADDR_INVALID);
305
306 /* MUSB_TXCSR_P_ISO is still set correctly */
307
308#ifdef CONFIG_USB_INVENTRA_DMA
309 {
310 size_t request_size;
311
312 /* setup DMA, then program endpoint CSR */
Cliff Caif95c4c02009-12-15 11:08:44 +0200313 request_size = min_t(size_t, request->length,
Felipe Balbi550a7372008-07-24 12:27:36 +0300314 musb_ep->dma->max_len);
Anand Gadiyard1043a22009-04-02 12:07:08 -0700315 if (request_size < musb_ep->packet_sz)
Felipe Balbi550a7372008-07-24 12:27:36 +0300316 musb_ep->dma->desired_mode = 0;
317 else
318 musb_ep->dma->desired_mode = 1;
319
320 use_dma = use_dma && c->channel_program(
321 musb_ep->dma, musb_ep->packet_sz,
322 musb_ep->dma->desired_mode,
Cliff Cai796a83f2009-12-21 21:18:02 -0500323 request->dma + request->actual, request_size);
Felipe Balbi550a7372008-07-24 12:27:36 +0300324 if (use_dma) {
325 if (musb_ep->dma->desired_mode == 0) {
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700326 /*
327 * We must not clear the DMAMODE bit
328 * before the DMAENAB bit -- and the
329 * latter doesn't always get cleared
330 * before we get here...
331 */
332 csr &= ~(MUSB_TXCSR_AUTOSET
333 | MUSB_TXCSR_DMAENAB);
334 musb_writew(epio, MUSB_TXCSR, csr
335 | MUSB_TXCSR_P_WZC_BITS);
336 csr &= ~MUSB_TXCSR_DMAMODE;
Felipe Balbi550a7372008-07-24 12:27:36 +0300337 csr |= (MUSB_TXCSR_DMAENAB |
338 MUSB_TXCSR_MODE);
339 /* against programming guide */
340 } else
341 csr |= (MUSB_TXCSR_AUTOSET
342 | MUSB_TXCSR_DMAENAB
343 | MUSB_TXCSR_DMAMODE
344 | MUSB_TXCSR_MODE);
345
346 csr &= ~MUSB_TXCSR_P_UNDERRUN;
347 musb_writew(epio, MUSB_TXCSR, csr);
348 }
349 }
350
351#elif defined(CONFIG_USB_TI_CPPI_DMA)
352 /* program endpoint CSR first, then setup DMA */
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700353 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
Sergei Shtylyov37e3ee92009-03-27 12:53:32 -0700354 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
355 MUSB_TXCSR_MODE;
Felipe Balbi550a7372008-07-24 12:27:36 +0300356 musb_writew(epio, MUSB_TXCSR,
357 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
358 | csr);
359
360 /* ensure writebuffer is empty */
361 csr = musb_readw(epio, MUSB_TXCSR);
362
363 /* NOTE host side sets DMAENAB later than this; both are
364 * OK since the transfer dma glue (between CPPI and Mentor
365 * fifos) just tells CPPI it could start. Data only moves
366 * to the USB TX fifo when both fifos are ready.
367 */
368
369 /* "mode" is irrelevant here; handle terminating ZLPs like
370 * PIO does, since the hardware RNDIS mode seems unreliable
371 * except for the last-packet-is-already-short case.
372 */
373 use_dma = use_dma && c->channel_program(
374 musb_ep->dma, musb_ep->packet_sz,
375 0,
376 request->dma,
377 request->length);
378 if (!use_dma) {
379 c->channel_release(musb_ep->dma);
380 musb_ep->dma = NULL;
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700381 csr &= ~MUSB_TXCSR_DMAENAB;
382 musb_writew(epio, MUSB_TXCSR, csr);
Felipe Balbi550a7372008-07-24 12:27:36 +0300383 /* invariant: prequest->buf is non-null */
384 }
385#elif defined(CONFIG_USB_TUSB_OMAP_DMA)
386 use_dma = use_dma && c->channel_program(
387 musb_ep->dma, musb_ep->packet_sz,
388 request->zero,
389 request->dma,
390 request->length);
391#endif
392 }
393#endif
394
395 if (!use_dma) {
396 musb_write_fifo(musb_ep->hw_ep, fifo_count,
397 (u8 *) (request->buf + request->actual));
398 request->actual += fifo_count;
399 csr |= MUSB_TXCSR_TXPKTRDY;
400 csr &= ~MUSB_TXCSR_P_UNDERRUN;
401 musb_writew(epio, MUSB_TXCSR, csr);
402 }
403
404 /* host may already have the data when this message shows... */
405 DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
406 musb_ep->end_point.name, use_dma ? "dma" : "pio",
407 request->actual, request->length,
408 musb_readw(epio, MUSB_TXCSR),
409 fifo_count,
410 musb_readw(epio, MUSB_TXMAXP));
411}
412
413/*
414 * FIFO state update (e.g. data ready).
415 * Called from IRQ, with controller locked.
416 */
417void musb_g_tx(struct musb *musb, u8 epnum)
418{
419 u16 csr;
420 struct usb_request *request;
421 u8 __iomem *mbase = musb->mregs;
422 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
423 void __iomem *epio = musb->endpoints[epnum].regs;
424 struct dma_channel *dma;
425
426 musb_ep_select(mbase, epnum);
427 request = next_request(musb_ep);
428
429 csr = musb_readw(epio, MUSB_TXCSR);
430 DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
431
432 dma = is_dma_capable() ? musb_ep->dma : NULL;
Sergei Shtylyov7723de72009-11-18 22:55:28 +0300433
434 /*
435 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
436 * probably rates reporting as a host error.
437 */
438 if (csr & MUSB_TXCSR_P_SENTSTALL) {
439 csr |= MUSB_TXCSR_P_WZC_BITS;
440 csr &= ~MUSB_TXCSR_P_SENTSTALL;
441 musb_writew(epio, MUSB_TXCSR, csr);
442 return;
443 }
444
445 if (csr & MUSB_TXCSR_P_UNDERRUN) {
446 /* We NAKed, no big deal... little reason to care. */
447 csr |= MUSB_TXCSR_P_WZC_BITS;
448 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
449 musb_writew(epio, MUSB_TXCSR, csr);
450 DBG(20, "underrun on ep%d, req %p\n", epnum, request);
451 }
452
453 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
454 /*
455 * SHOULD NOT HAPPEN... has with CPPI though, after
456 * changing SENDSTALL (and other cases); harmless?
Felipe Balbi550a7372008-07-24 12:27:36 +0300457 */
Sergei Shtylyov7723de72009-11-18 22:55:28 +0300458 DBG(5, "%s dma still busy?\n", musb_ep->end_point.name);
459 return;
460 }
461
462 if (request) {
463 u8 is_dma = 0;
464
465 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
466 is_dma = 1;
Felipe Balbi550a7372008-07-24 12:27:36 +0300467 csr |= MUSB_TXCSR_P_WZC_BITS;
Sergei Shtylyov7723de72009-11-18 22:55:28 +0300468 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
469 MUSB_TXCSR_TXPKTRDY);
Felipe Balbi550a7372008-07-24 12:27:36 +0300470 musb_writew(epio, MUSB_TXCSR, csr);
Sergei Shtylyov7723de72009-11-18 22:55:28 +0300471 /* Ensure writebuffer is empty. */
472 csr = musb_readw(epio, MUSB_TXCSR);
473 request->actual += musb_ep->dma->actual_len;
474 DBG(4, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
475 epnum, csr, musb_ep->dma->actual_len, request);
Felipe Balbi550a7372008-07-24 12:27:36 +0300476 }
477
Sergei Shtylyov7723de72009-11-18 22:55:28 +0300478 if (is_dma || request->actual == request->length) {
479 /*
480 * First, maybe a terminating short packet. Some DMA
481 * engines might handle this by themselves.
Felipe Balbi550a7372008-07-24 12:27:36 +0300482 */
Sergei Shtylyov7723de72009-11-18 22:55:28 +0300483 if ((request->zero && request->length
484 && request->length % musb_ep->packet_sz == 0)
Felipe Balbi550a7372008-07-24 12:27:36 +0300485#ifdef CONFIG_USB_INVENTRA_DMA
Sergei Shtylyov7723de72009-11-18 22:55:28 +0300486 || (is_dma && (!dma->desired_mode ||
487 (request->actual &
488 (musb_ep->packet_sz - 1))))
Felipe Balbi550a7372008-07-24 12:27:36 +0300489#endif
Sergei Shtylyov7723de72009-11-18 22:55:28 +0300490 ) {
491 /*
492 * On DMA completion, FIFO may not be
493 * available yet...
Felipe Balbi550a7372008-07-24 12:27:36 +0300494 */
Sergei Shtylyov7723de72009-11-18 22:55:28 +0300495 if (csr & MUSB_TXCSR_TXPKTRDY)
496 return;
497
498 DBG(4, "sending zero pkt\n");
499 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
500 | MUSB_TXCSR_TXPKTRDY);
501 request->zero = 0;
Felipe Balbi550a7372008-07-24 12:27:36 +0300502 }
503
Sergei Shtylyov7723de72009-11-18 22:55:28 +0300504 /* ... or if not, then complete it. */
505 musb_g_giveback(musb_ep, request, 0);
506
507 /*
508 * Kickstart next transfer if appropriate;
509 * the packet that just completed might not
510 * be transmitted for hours or days.
511 * REVISIT for double buffering...
512 * FIXME revisit for stalls too...
513 */
514 musb_ep_select(mbase, epnum);
515 csr = musb_readw(epio, MUSB_TXCSR);
516 if (csr & MUSB_TXCSR_FIFONOTEMPTY)
517 return;
518
Sergei Shtylyov95962a72009-12-16 20:38:31 +0300519 request = musb_ep->desc ? next_request(musb_ep) : NULL;
520 if (!request) {
Sergei Shtylyov7723de72009-11-18 22:55:28 +0300521 DBG(4, "%s idle now\n",
522 musb_ep->end_point.name);
523 return;
Sergei Shtylyov95962a72009-12-16 20:38:31 +0300524 }
Felipe Balbi550a7372008-07-24 12:27:36 +0300525 }
526
Sergei Shtylyov7723de72009-11-18 22:55:28 +0300527 txstate(musb, to_musb_request(request));
528 }
Felipe Balbi550a7372008-07-24 12:27:36 +0300529}
530
531/* ------------------------------------------------------------ */
532
533#ifdef CONFIG_USB_INVENTRA_DMA
534
535/* Peripheral rx (OUT) using Mentor DMA works as follows:
536 - Only mode 0 is used.
537
538 - Request is queued by the gadget class driver.
539 -> if queue was previously empty, rxstate()
540
541 - Host sends OUT token which causes an endpoint interrupt
542 /\ -> RxReady
543 | -> if request queued, call rxstate
544 | /\ -> setup DMA
545 | | -> DMA interrupt on completion
546 | | -> RxReady
547 | | -> stop DMA
548 | | -> ack the read
549 | | -> if data recd = max expected
550 | | by the request, or host
551 | | sent a short packet,
552 | | complete the request,
553 | | and start the next one.
554 | |_____________________________________|
555 | else just wait for the host
556 | to send the next OUT token.
557 |__________________________________________________|
558
559 * Non-Mentor DMA engines can of course work differently.
560 */
561
562#endif
563
564/*
565 * Context: controller locked, IRQs blocked, endpoint selected
566 */
567static void rxstate(struct musb *musb, struct musb_request *req)
568{
Felipe Balbi550a7372008-07-24 12:27:36 +0300569 const u8 epnum = req->epnum;
570 struct usb_request *request = &req->request;
571 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out;
572 void __iomem *epio = musb->endpoints[epnum].regs;
Felipe Balbic2c96322009-02-21 15:29:42 -0800573 unsigned fifo_count = 0;
Felipe Balbi550a7372008-07-24 12:27:36 +0300574 u16 len = musb_ep->packet_sz;
Sergei Shtylyovcea83242009-11-18 22:51:18 +0300575 u16 csr = musb_readw(epio, MUSB_RXCSR);
Felipe Balbi550a7372008-07-24 12:27:36 +0300576
Sergei Shtylyovcea83242009-11-18 22:51:18 +0300577 /* We shouldn't get here while DMA is active, but we do... */
578 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
579 DBG(4, "DMA pending...\n");
580 return;
581 }
582
583 if (csr & MUSB_RXCSR_P_SENDSTALL) {
584 DBG(5, "%s stalling, RXCSR %04x\n",
585 musb_ep->end_point.name, csr);
586 return;
587 }
Felipe Balbi550a7372008-07-24 12:27:36 +0300588
589 if (is_cppi_enabled() && musb_ep->dma) {
590 struct dma_controller *c = musb->dma_controller;
591 struct dma_channel *channel = musb_ep->dma;
592
593 /* NOTE: CPPI won't actually stop advancing the DMA
594 * queue after short packet transfers, so this is almost
595 * always going to run as IRQ-per-packet DMA so that
596 * faults will be handled correctly.
597 */
598 if (c->channel_program(channel,
599 musb_ep->packet_sz,
600 !request->short_not_ok,
601 request->dma + request->actual,
602 request->length - request->actual)) {
603
604 /* make sure that if an rxpkt arrived after the irq,
605 * the cppi engine will be ready to take it as soon
606 * as DMA is enabled
607 */
608 csr &= ~(MUSB_RXCSR_AUTOCLEAR
609 | MUSB_RXCSR_DMAMODE);
610 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
611 musb_writew(epio, MUSB_RXCSR, csr);
612 return;
613 }
614 }
615
616 if (csr & MUSB_RXCSR_RXPKTRDY) {
617 len = musb_readw(epio, MUSB_RXCOUNT);
618 if (request->actual < request->length) {
619#ifdef CONFIG_USB_INVENTRA_DMA
620 if (is_dma_capable() && musb_ep->dma) {
621 struct dma_controller *c;
622 struct dma_channel *channel;
623 int use_dma = 0;
624
625 c = musb->dma_controller;
626 channel = musb_ep->dma;
627
628 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
629 * mode 0 only. So we do not get endpoint interrupts due to DMA
630 * completion. We only get interrupts from DMA controller.
631 *
632 * We could operate in DMA mode 1 if we knew the size of the tranfer
633 * in advance. For mass storage class, request->length = what the host
634 * sends, so that'd work. But for pretty much everything else,
635 * request->length is routinely more than what the host sends. For
636 * most these gadgets, end of is signified either by a short packet,
637 * or filling the last byte of the buffer. (Sending extra data in
638 * that last pckate should trigger an overflow fault.) But in mode 1,
639 * we don't get DMA completion interrrupt for short packets.
640 *
641 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
642 * to get endpoint interrupt on every DMA req, but that didn't seem
643 * to work reliably.
644 *
645 * REVISIT an updated g_file_storage can set req->short_not_ok, which
646 * then becomes usable as a runtime "use mode 1" hint...
647 */
648
649 csr |= MUSB_RXCSR_DMAENAB;
650#ifdef USE_MODE1
651 csr |= MUSB_RXCSR_AUTOCLEAR;
652 /* csr |= MUSB_RXCSR_DMAMODE; */
653
654 /* this special sequence (enabling and then
655 * disabling MUSB_RXCSR_DMAMODE) is required
656 * to get DMAReq to activate
657 */
658 musb_writew(epio, MUSB_RXCSR,
659 csr | MUSB_RXCSR_DMAMODE);
660#endif
661 musb_writew(epio, MUSB_RXCSR, csr);
662
663 if (request->actual < request->length) {
664 int transfer_size = 0;
665#ifdef USE_MODE1
666 transfer_size = min(request->length,
667 channel->max_len);
668#else
669 transfer_size = len;
670#endif
671 if (transfer_size <= musb_ep->packet_sz)
672 musb_ep->dma->desired_mode = 0;
673 else
674 musb_ep->dma->desired_mode = 1;
675
676 use_dma = c->channel_program(
677 channel,
678 musb_ep->packet_sz,
679 channel->desired_mode,
680 request->dma
681 + request->actual,
682 transfer_size);
683 }
684
685 if (use_dma)
686 return;
687 }
688#endif /* Mentor's DMA */
689
690 fifo_count = request->length - request->actual;
691 DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
692 musb_ep->end_point.name,
693 len, fifo_count,
694 musb_ep->packet_sz);
695
Felipe Balbic2c96322009-02-21 15:29:42 -0800696 fifo_count = min_t(unsigned, len, fifo_count);
Felipe Balbi550a7372008-07-24 12:27:36 +0300697
698#ifdef CONFIG_USB_TUSB_OMAP_DMA
699 if (tusb_dma_omap() && musb_ep->dma) {
700 struct dma_controller *c = musb->dma_controller;
701 struct dma_channel *channel = musb_ep->dma;
702 u32 dma_addr = request->dma + request->actual;
703 int ret;
704
705 ret = c->channel_program(channel,
706 musb_ep->packet_sz,
707 channel->desired_mode,
708 dma_addr,
709 fifo_count);
710 if (ret)
711 return;
712 }
713#endif
714
715 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
716 (request->buf + request->actual));
717 request->actual += fifo_count;
718
719 /* REVISIT if we left anything in the fifo, flush
720 * it and report -EOVERFLOW
721 */
722
723 /* ack the read! */
724 csr |= MUSB_RXCSR_P_WZC_BITS;
725 csr &= ~MUSB_RXCSR_RXPKTRDY;
726 musb_writew(epio, MUSB_RXCSR, csr);
727 }
728 }
729
730 /* reach the end or short packet detected */
731 if (request->actual == request->length || len < musb_ep->packet_sz)
732 musb_g_giveback(musb_ep, request, 0);
733}
734
735/*
736 * Data ready for a request; called from IRQ
737 */
738void musb_g_rx(struct musb *musb, u8 epnum)
739{
740 u16 csr;
741 struct usb_request *request;
742 void __iomem *mbase = musb->mregs;
743 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out;
744 void __iomem *epio = musb->endpoints[epnum].regs;
745 struct dma_channel *dma;
746
747 musb_ep_select(mbase, epnum);
748
749 request = next_request(musb_ep);
Maulik Mankad0abdc362009-12-22 16:18:19 +0530750 if (!request)
751 return;
Felipe Balbi550a7372008-07-24 12:27:36 +0300752
753 csr = musb_readw(epio, MUSB_RXCSR);
754 dma = is_dma_capable() ? musb_ep->dma : NULL;
755
756 DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
757 csr, dma ? " (dma)" : "", request);
758
759 if (csr & MUSB_RXCSR_P_SENTSTALL) {
Felipe Balbi550a7372008-07-24 12:27:36 +0300760 csr |= MUSB_RXCSR_P_WZC_BITS;
761 csr &= ~MUSB_RXCSR_P_SENTSTALL;
762 musb_writew(epio, MUSB_RXCSR, csr);
Sergei Shtylyovcea83242009-11-18 22:51:18 +0300763 return;
Felipe Balbi550a7372008-07-24 12:27:36 +0300764 }
765
766 if (csr & MUSB_RXCSR_P_OVERRUN) {
767 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
768 csr &= ~MUSB_RXCSR_P_OVERRUN;
769 musb_writew(epio, MUSB_RXCSR, csr);
770
771 DBG(3, "%s iso overrun on %p\n", musb_ep->name, request);
772 if (request && request->status == -EINPROGRESS)
773 request->status = -EOVERFLOW;
774 }
775 if (csr & MUSB_RXCSR_INCOMPRX) {
776 /* REVISIT not necessarily an error */
777 DBG(4, "%s, incomprx\n", musb_ep->end_point.name);
778 }
779
780 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
781 /* "should not happen"; likely RXPKTRDY pending for DMA */
782 DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1,
783 "%s busy, csr %04x\n",
784 musb_ep->end_point.name, csr);
Sergei Shtylyovcea83242009-11-18 22:51:18 +0300785 return;
Felipe Balbi550a7372008-07-24 12:27:36 +0300786 }
787
788 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
789 csr &= ~(MUSB_RXCSR_AUTOCLEAR
790 | MUSB_RXCSR_DMAENAB
791 | MUSB_RXCSR_DMAMODE);
792 musb_writew(epio, MUSB_RXCSR,
793 MUSB_RXCSR_P_WZC_BITS | csr);
794
795 request->actual += musb_ep->dma->actual_len;
796
797 DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
798 epnum, csr,
799 musb_readw(epio, MUSB_RXCSR),
800 musb_ep->dma->actual_len, request);
801
802#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
803 /* Autoclear doesn't clear RxPktRdy for short packets */
804 if ((dma->desired_mode == 0)
805 || (dma->actual_len
806 & (musb_ep->packet_sz - 1))) {
807 /* ack the read! */
808 csr &= ~MUSB_RXCSR_RXPKTRDY;
809 musb_writew(epio, MUSB_RXCSR, csr);
810 }
811
812 /* incomplete, and not short? wait for next IN packet */
813 if ((request->actual < request->length)
814 && (musb_ep->dma->actual_len
815 == musb_ep->packet_sz))
Sergei Shtylyovcea83242009-11-18 22:51:18 +0300816 return;
Felipe Balbi550a7372008-07-24 12:27:36 +0300817#endif
818 musb_g_giveback(musb_ep, request, 0);
819
820 request = next_request(musb_ep);
821 if (!request)
Sergei Shtylyovcea83242009-11-18 22:51:18 +0300822 return;
Felipe Balbi550a7372008-07-24 12:27:36 +0300823 }
824
Felipe Balbi550a7372008-07-24 12:27:36 +0300825 /* analyze request if the ep is hot */
826 if (request)
827 rxstate(musb, to_musb_request(request));
828 else
829 DBG(3, "packet waiting for %s%s request\n",
830 musb_ep->desc ? "" : "inactive ",
831 musb_ep->end_point.name);
Felipe Balbi550a7372008-07-24 12:27:36 +0300832 return;
833}
834
835/* ------------------------------------------------------------ */
836
837static int musb_gadget_enable(struct usb_ep *ep,
838 const struct usb_endpoint_descriptor *desc)
839{
840 unsigned long flags;
841 struct musb_ep *musb_ep;
842 struct musb_hw_ep *hw_ep;
843 void __iomem *regs;
844 struct musb *musb;
845 void __iomem *mbase;
846 u8 epnum;
847 u16 csr;
848 unsigned tmp;
849 int status = -EINVAL;
850
851 if (!ep || !desc)
852 return -EINVAL;
853
854 musb_ep = to_musb_ep(ep);
855 hw_ep = musb_ep->hw_ep;
856 regs = hw_ep->regs;
857 musb = musb_ep->musb;
858 mbase = musb->mregs;
859 epnum = musb_ep->current_epnum;
860
861 spin_lock_irqsave(&musb->lock, flags);
862
863 if (musb_ep->desc) {
864 status = -EBUSY;
865 goto fail;
866 }
Julia Lawall96bcd092009-01-24 17:57:24 -0800867 musb_ep->type = usb_endpoint_type(desc);
Felipe Balbi550a7372008-07-24 12:27:36 +0300868
869 /* check direction and (later) maxpacket size against endpoint */
Julia Lawall96bcd092009-01-24 17:57:24 -0800870 if (usb_endpoint_num(desc) != epnum)
Felipe Balbi550a7372008-07-24 12:27:36 +0300871 goto fail;
872
873 /* REVISIT this rules out high bandwidth periodic transfers */
874 tmp = le16_to_cpu(desc->wMaxPacketSize);
875 if (tmp & ~0x07ff)
876 goto fail;
877 musb_ep->packet_sz = tmp;
878
879 /* enable the interrupts for the endpoint, set the endpoint
880 * packet size (or fail), set the mode, clear the fifo
881 */
882 musb_ep_select(mbase, epnum);
Julia Lawall96bcd092009-01-24 17:57:24 -0800883 if (usb_endpoint_dir_in(desc)) {
Felipe Balbi550a7372008-07-24 12:27:36 +0300884 u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
885
886 if (hw_ep->is_shared_fifo)
887 musb_ep->is_in = 1;
888 if (!musb_ep->is_in)
889 goto fail;
890 if (tmp > hw_ep->max_packet_sz_tx)
891 goto fail;
892
893 int_txe |= (1 << epnum);
894 musb_writew(mbase, MUSB_INTRTXE, int_txe);
895
896 /* REVISIT if can_bulk_split(), use by updating "tmp";
897 * likewise high bandwidth periodic tx
898 */
Cliff Cai9f445cb2010-01-28 20:44:18 -0500899 /* Set TXMAXP with the FIFO size of the endpoint
900 * to disable double buffering mode. Currently, It seems that double
901 * buffering has problem if musb RTL revision number < 2.0.
902 */
903 if (musb->hwvers < MUSB_HWVERS_2000)
904 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
905 else
906 musb_writew(regs, MUSB_TXMAXP, tmp);
Felipe Balbi550a7372008-07-24 12:27:36 +0300907
908 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
909 if (musb_readw(regs, MUSB_TXCSR)
910 & MUSB_TXCSR_FIFONOTEMPTY)
911 csr |= MUSB_TXCSR_FLUSHFIFO;
912 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
913 csr |= MUSB_TXCSR_P_ISO;
914
915 /* set twice in case of double buffering */
916 musb_writew(regs, MUSB_TXCSR, csr);
917 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
918 musb_writew(regs, MUSB_TXCSR, csr);
919
920 } else {
921 u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE);
922
923 if (hw_ep->is_shared_fifo)
924 musb_ep->is_in = 0;
925 if (musb_ep->is_in)
926 goto fail;
927 if (tmp > hw_ep->max_packet_sz_rx)
928 goto fail;
929
930 int_rxe |= (1 << epnum);
931 musb_writew(mbase, MUSB_INTRRXE, int_rxe);
932
933 /* REVISIT if can_bulk_combine() use by updating "tmp"
934 * likewise high bandwidth periodic rx
935 */
Cliff Cai9f445cb2010-01-28 20:44:18 -0500936 /* Set RXMAXP with the FIFO size of the endpoint
937 * to disable double buffering mode.
938 */
939 if (musb->hwvers < MUSB_HWVERS_2000)
940 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_rx);
941 else
942 musb_writew(regs, MUSB_RXMAXP, tmp);
Felipe Balbi550a7372008-07-24 12:27:36 +0300943
944 /* force shared fifo to OUT-only mode */
945 if (hw_ep->is_shared_fifo) {
946 csr = musb_readw(regs, MUSB_TXCSR);
947 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
948 musb_writew(regs, MUSB_TXCSR, csr);
949 }
950
951 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
952 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
953 csr |= MUSB_RXCSR_P_ISO;
954 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
955 csr |= MUSB_RXCSR_DISNYET;
956
957 /* set twice in case of double buffering */
958 musb_writew(regs, MUSB_RXCSR, csr);
959 musb_writew(regs, MUSB_RXCSR, csr);
960 }
961
962 /* NOTE: all the I/O code _should_ work fine without DMA, in case
963 * for some reason you run out of channels here.
964 */
965 if (is_dma_capable() && musb->dma_controller) {
966 struct dma_controller *c = musb->dma_controller;
967
968 musb_ep->dma = c->channel_alloc(c, hw_ep,
969 (desc->bEndpointAddress & USB_DIR_IN));
970 } else
971 musb_ep->dma = NULL;
972
973 musb_ep->desc = desc;
974 musb_ep->busy = 0;
Sergei Shtylyov47e97602009-11-18 22:51:51 +0300975 musb_ep->wedged = 0;
Felipe Balbi550a7372008-07-24 12:27:36 +0300976 status = 0;
977
978 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
979 musb_driver_name, musb_ep->end_point.name,
980 ({ char *s; switch (musb_ep->type) {
981 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
982 case USB_ENDPOINT_XFER_INT: s = "int"; break;
983 default: s = "iso"; break;
984 }; s; }),
985 musb_ep->is_in ? "IN" : "OUT",
986 musb_ep->dma ? "dma, " : "",
987 musb_ep->packet_sz);
988
989 schedule_work(&musb->irq_work);
990
991fail:
992 spin_unlock_irqrestore(&musb->lock, flags);
993 return status;
994}
995
996/*
997 * Disable an endpoint flushing all requests queued.
998 */
999static int musb_gadget_disable(struct usb_ep *ep)
1000{
1001 unsigned long flags;
1002 struct musb *musb;
1003 u8 epnum;
1004 struct musb_ep *musb_ep;
1005 void __iomem *epio;
1006 int status = 0;
1007
1008 musb_ep = to_musb_ep(ep);
1009 musb = musb_ep->musb;
1010 epnum = musb_ep->current_epnum;
1011 epio = musb->endpoints[epnum].regs;
1012
1013 spin_lock_irqsave(&musb->lock, flags);
1014 musb_ep_select(musb->mregs, epnum);
1015
1016 /* zero the endpoint sizes */
1017 if (musb_ep->is_in) {
1018 u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE);
1019 int_txe &= ~(1 << epnum);
1020 musb_writew(musb->mregs, MUSB_INTRTXE, int_txe);
1021 musb_writew(epio, MUSB_TXMAXP, 0);
1022 } else {
1023 u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE);
1024 int_rxe &= ~(1 << epnum);
1025 musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe);
1026 musb_writew(epio, MUSB_RXMAXP, 0);
1027 }
1028
1029 musb_ep->desc = NULL;
1030
1031 /* abort all pending DMA and requests */
1032 nuke(musb_ep, -ESHUTDOWN);
1033
1034 schedule_work(&musb->irq_work);
1035
1036 spin_unlock_irqrestore(&(musb->lock), flags);
1037
1038 DBG(2, "%s\n", musb_ep->end_point.name);
1039
1040 return status;
1041}
1042
1043/*
1044 * Allocate a request for an endpoint.
1045 * Reused by ep0 code.
1046 */
1047struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1048{
1049 struct musb_ep *musb_ep = to_musb_ep(ep);
1050 struct musb_request *request = NULL;
1051
1052 request = kzalloc(sizeof *request, gfp_flags);
1053 if (request) {
1054 INIT_LIST_HEAD(&request->request.list);
1055 request->request.dma = DMA_ADDR_INVALID;
1056 request->epnum = musb_ep->current_epnum;
1057 request->ep = musb_ep;
1058 }
1059
1060 return &request->request;
1061}
1062
1063/*
1064 * Free a request
1065 * Reused by ep0 code.
1066 */
1067void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1068{
1069 kfree(to_musb_request(req));
1070}
1071
1072static LIST_HEAD(buffers);
1073
1074struct free_record {
1075 struct list_head list;
1076 struct device *dev;
1077 unsigned bytes;
1078 dma_addr_t dma;
1079};
1080
1081/*
1082 * Context: controller locked, IRQs blocked.
1083 */
1084static void musb_ep_restart(struct musb *musb, struct musb_request *req)
1085{
1086 DBG(3, "<== %s request %p len %u on hw_ep%d\n",
1087 req->tx ? "TX/IN" : "RX/OUT",
1088 &req->request, req->request.length, req->epnum);
1089
1090 musb_ep_select(musb->mregs, req->epnum);
1091 if (req->tx)
1092 txstate(musb, req);
1093 else
1094 rxstate(musb, req);
1095}
1096
1097static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1098 gfp_t gfp_flags)
1099{
1100 struct musb_ep *musb_ep;
1101 struct musb_request *request;
1102 struct musb *musb;
1103 int status = 0;
1104 unsigned long lockflags;
1105
1106 if (!ep || !req)
1107 return -EINVAL;
1108 if (!req->buf)
1109 return -ENODATA;
1110
1111 musb_ep = to_musb_ep(ep);
1112 musb = musb_ep->musb;
1113
1114 request = to_musb_request(req);
1115 request->musb = musb;
1116
1117 if (request->ep != musb_ep)
1118 return -EINVAL;
1119
1120 DBG(4, "<== to %s request=%p\n", ep->name, req);
1121
1122 /* request is mine now... */
1123 request->request.actual = 0;
1124 request->request.status = -EINPROGRESS;
1125 request->epnum = musb_ep->current_epnum;
1126 request->tx = musb_ep->is_in;
1127
1128 if (is_dma_capable() && musb_ep->dma) {
1129 if (request->request.dma == DMA_ADDR_INVALID) {
1130 request->request.dma = dma_map_single(
1131 musb->controller,
1132 request->request.buf,
1133 request->request.length,
1134 request->tx
1135 ? DMA_TO_DEVICE
1136 : DMA_FROM_DEVICE);
1137 request->mapped = 1;
1138 } else {
1139 dma_sync_single_for_device(musb->controller,
1140 request->request.dma,
1141 request->request.length,
1142 request->tx
1143 ? DMA_TO_DEVICE
1144 : DMA_FROM_DEVICE);
1145 request->mapped = 0;
1146 }
1147 } else if (!req->buf) {
1148 return -ENODATA;
1149 } else
1150 request->mapped = 0;
1151
1152 spin_lock_irqsave(&musb->lock, lockflags);
1153
1154 /* don't queue if the ep is down */
1155 if (!musb_ep->desc) {
1156 DBG(4, "req %p queued to %s while ep %s\n",
1157 req, ep->name, "disabled");
1158 status = -ESHUTDOWN;
1159 goto cleanup;
1160 }
1161
1162 /* add request to the list */
1163 list_add_tail(&(request->request.list), &(musb_ep->req_list));
1164
1165 /* it this is the head of the queue, start i/o ... */
1166 if (!musb_ep->busy && &request->request.list == musb_ep->req_list.next)
1167 musb_ep_restart(musb, request);
1168
1169cleanup:
1170 spin_unlock_irqrestore(&musb->lock, lockflags);
1171 return status;
1172}
1173
1174static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1175{
1176 struct musb_ep *musb_ep = to_musb_ep(ep);
1177 struct usb_request *r;
1178 unsigned long flags;
1179 int status = 0;
1180 struct musb *musb = musb_ep->musb;
1181
1182 if (!ep || !request || to_musb_request(request)->ep != musb_ep)
1183 return -EINVAL;
1184
1185 spin_lock_irqsave(&musb->lock, flags);
1186
1187 list_for_each_entry(r, &musb_ep->req_list, list) {
1188 if (r == request)
1189 break;
1190 }
1191 if (r != request) {
1192 DBG(3, "request %p not queued to %s\n", request, ep->name);
1193 status = -EINVAL;
1194 goto done;
1195 }
1196
1197 /* if the hardware doesn't have the request, easy ... */
1198 if (musb_ep->req_list.next != &request->list || musb_ep->busy)
1199 musb_g_giveback(musb_ep, request, -ECONNRESET);
1200
1201 /* ... else abort the dma transfer ... */
1202 else if (is_dma_capable() && musb_ep->dma) {
1203 struct dma_controller *c = musb->dma_controller;
1204
1205 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1206 if (c->channel_abort)
1207 status = c->channel_abort(musb_ep->dma);
1208 else
1209 status = -EBUSY;
1210 if (status == 0)
1211 musb_g_giveback(musb_ep, request, -ECONNRESET);
1212 } else {
1213 /* NOTE: by sticking to easily tested hardware/driver states,
1214 * we leave counting of in-flight packets imprecise.
1215 */
1216 musb_g_giveback(musb_ep, request, -ECONNRESET);
1217 }
1218
1219done:
1220 spin_unlock_irqrestore(&musb->lock, flags);
1221 return status;
1222}
1223
1224/*
1225 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1226 * data but will queue requests.
1227 *
1228 * exported to ep0 code
1229 */
Felipe Balbi1b6c3b02009-12-04 15:47:46 +02001230static int musb_gadget_set_halt(struct usb_ep *ep, int value)
Felipe Balbi550a7372008-07-24 12:27:36 +03001231{
1232 struct musb_ep *musb_ep = to_musb_ep(ep);
1233 u8 epnum = musb_ep->current_epnum;
1234 struct musb *musb = musb_ep->musb;
1235 void __iomem *epio = musb->endpoints[epnum].regs;
1236 void __iomem *mbase;
1237 unsigned long flags;
1238 u16 csr;
Sergei Shtylyovcea83242009-11-18 22:51:18 +03001239 struct musb_request *request;
Felipe Balbi550a7372008-07-24 12:27:36 +03001240 int status = 0;
1241
1242 if (!ep)
1243 return -EINVAL;
1244 mbase = musb->mregs;
1245
1246 spin_lock_irqsave(&musb->lock, flags);
1247
1248 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1249 status = -EINVAL;
1250 goto done;
1251 }
1252
1253 musb_ep_select(mbase, epnum);
1254
Felipe Balbi550a7372008-07-24 12:27:36 +03001255 request = to_musb_request(next_request(musb_ep));
Sergei Shtylyovcea83242009-11-18 22:51:18 +03001256 if (value) {
1257 if (request) {
1258 DBG(3, "request in progress, cannot halt %s\n",
1259 ep->name);
1260 status = -EAGAIN;
1261 goto done;
Felipe Balbi550a7372008-07-24 12:27:36 +03001262 }
Sergei Shtylyovcea83242009-11-18 22:51:18 +03001263 /* Cannot portably stall with non-empty FIFO */
1264 if (musb_ep->is_in) {
1265 csr = musb_readw(epio, MUSB_TXCSR);
1266 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1267 DBG(3, "FIFO busy, cannot halt %s\n", ep->name);
1268 status = -EAGAIN;
1269 goto done;
1270 }
1271 }
Sergei Shtylyov47e97602009-11-18 22:51:51 +03001272 } else
1273 musb_ep->wedged = 0;
Felipe Balbi550a7372008-07-24 12:27:36 +03001274
1275 /* set/clear the stall and toggle bits */
1276 DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear");
1277 if (musb_ep->is_in) {
1278 csr = musb_readw(epio, MUSB_TXCSR);
Felipe Balbi550a7372008-07-24 12:27:36 +03001279 csr |= MUSB_TXCSR_P_WZC_BITS
1280 | MUSB_TXCSR_CLRDATATOG;
1281 if (value)
1282 csr |= MUSB_TXCSR_P_SENDSTALL;
1283 else
1284 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1285 | MUSB_TXCSR_P_SENTSTALL);
1286 csr &= ~MUSB_TXCSR_TXPKTRDY;
1287 musb_writew(epio, MUSB_TXCSR, csr);
1288 } else {
1289 csr = musb_readw(epio, MUSB_RXCSR);
1290 csr |= MUSB_RXCSR_P_WZC_BITS
1291 | MUSB_RXCSR_FLUSHFIFO
1292 | MUSB_RXCSR_CLRDATATOG;
1293 if (value)
1294 csr |= MUSB_RXCSR_P_SENDSTALL;
1295 else
1296 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1297 | MUSB_RXCSR_P_SENTSTALL);
1298 musb_writew(epio, MUSB_RXCSR, csr);
1299 }
1300
Felipe Balbi550a7372008-07-24 12:27:36 +03001301 /* maybe start the first request in the queue */
1302 if (!musb_ep->busy && !value && request) {
1303 DBG(3, "restarting the request\n");
1304 musb_ep_restart(musb, request);
1305 }
1306
Sergei Shtylyovcea83242009-11-18 22:51:18 +03001307done:
Felipe Balbi550a7372008-07-24 12:27:36 +03001308 spin_unlock_irqrestore(&musb->lock, flags);
1309 return status;
1310}
1311
Sergei Shtylyov47e97602009-11-18 22:51:51 +03001312/*
1313 * Sets the halt feature with the clear requests ignored
1314 */
Felipe Balbi1b6c3b02009-12-04 15:47:46 +02001315static int musb_gadget_set_wedge(struct usb_ep *ep)
Sergei Shtylyov47e97602009-11-18 22:51:51 +03001316{
1317 struct musb_ep *musb_ep = to_musb_ep(ep);
1318
1319 if (!ep)
1320 return -EINVAL;
1321
1322 musb_ep->wedged = 1;
1323
1324 return usb_ep_set_halt(ep);
1325}
1326
Felipe Balbi550a7372008-07-24 12:27:36 +03001327static int musb_gadget_fifo_status(struct usb_ep *ep)
1328{
1329 struct musb_ep *musb_ep = to_musb_ep(ep);
1330 void __iomem *epio = musb_ep->hw_ep->regs;
1331 int retval = -EINVAL;
1332
1333 if (musb_ep->desc && !musb_ep->is_in) {
1334 struct musb *musb = musb_ep->musb;
1335 int epnum = musb_ep->current_epnum;
1336 void __iomem *mbase = musb->mregs;
1337 unsigned long flags;
1338
1339 spin_lock_irqsave(&musb->lock, flags);
1340
1341 musb_ep_select(mbase, epnum);
1342 /* FIXME return zero unless RXPKTRDY is set */
1343 retval = musb_readw(epio, MUSB_RXCOUNT);
1344
1345 spin_unlock_irqrestore(&musb->lock, flags);
1346 }
1347 return retval;
1348}
1349
1350static void musb_gadget_fifo_flush(struct usb_ep *ep)
1351{
1352 struct musb_ep *musb_ep = to_musb_ep(ep);
1353 struct musb *musb = musb_ep->musb;
1354 u8 epnum = musb_ep->current_epnum;
1355 void __iomem *epio = musb->endpoints[epnum].regs;
1356 void __iomem *mbase;
1357 unsigned long flags;
1358 u16 csr, int_txe;
1359
1360 mbase = musb->mregs;
1361
1362 spin_lock_irqsave(&musb->lock, flags);
1363 musb_ep_select(mbase, (u8) epnum);
1364
1365 /* disable interrupts */
1366 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1367 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
1368
1369 if (musb_ep->is_in) {
1370 csr = musb_readw(epio, MUSB_TXCSR);
1371 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1372 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1373 musb_writew(epio, MUSB_TXCSR, csr);
1374 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1375 musb_writew(epio, MUSB_TXCSR, csr);
1376 }
1377 } else {
1378 csr = musb_readw(epio, MUSB_RXCSR);
1379 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1380 musb_writew(epio, MUSB_RXCSR, csr);
1381 musb_writew(epio, MUSB_RXCSR, csr);
1382 }
1383
1384 /* re-enable interrupt */
1385 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1386 spin_unlock_irqrestore(&musb->lock, flags);
1387}
1388
1389static const struct usb_ep_ops musb_ep_ops = {
1390 .enable = musb_gadget_enable,
1391 .disable = musb_gadget_disable,
1392 .alloc_request = musb_alloc_request,
1393 .free_request = musb_free_request,
1394 .queue = musb_gadget_queue,
1395 .dequeue = musb_gadget_dequeue,
1396 .set_halt = musb_gadget_set_halt,
Sergei Shtylyov47e97602009-11-18 22:51:51 +03001397 .set_wedge = musb_gadget_set_wedge,
Felipe Balbi550a7372008-07-24 12:27:36 +03001398 .fifo_status = musb_gadget_fifo_status,
1399 .fifo_flush = musb_gadget_fifo_flush
1400};
1401
1402/* ----------------------------------------------------------------------- */
1403
1404static int musb_gadget_get_frame(struct usb_gadget *gadget)
1405{
1406 struct musb *musb = gadget_to_musb(gadget);
1407
1408 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1409}
1410
1411static int musb_gadget_wakeup(struct usb_gadget *gadget)
1412{
1413 struct musb *musb = gadget_to_musb(gadget);
1414 void __iomem *mregs = musb->mregs;
1415 unsigned long flags;
1416 int status = -EINVAL;
1417 u8 power, devctl;
1418 int retries;
1419
1420 spin_lock_irqsave(&musb->lock, flags);
1421
David Brownell84e250f2009-03-31 12:30:04 -07001422 switch (musb->xceiv->state) {
Felipe Balbi550a7372008-07-24 12:27:36 +03001423 case OTG_STATE_B_PERIPHERAL:
1424 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1425 * that's part of the standard usb 1.1 state machine, and
1426 * doesn't affect OTG transitions.
1427 */
1428 if (musb->may_wakeup && musb->is_suspended)
1429 break;
1430 goto done;
1431 case OTG_STATE_B_IDLE:
1432 /* Start SRP ... OTG not required. */
1433 devctl = musb_readb(mregs, MUSB_DEVCTL);
1434 DBG(2, "Sending SRP: devctl: %02x\n", devctl);
1435 devctl |= MUSB_DEVCTL_SESSION;
1436 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1437 devctl = musb_readb(mregs, MUSB_DEVCTL);
1438 retries = 100;
1439 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1440 devctl = musb_readb(mregs, MUSB_DEVCTL);
1441 if (retries-- < 1)
1442 break;
1443 }
1444 retries = 10000;
1445 while (devctl & MUSB_DEVCTL_SESSION) {
1446 devctl = musb_readb(mregs, MUSB_DEVCTL);
1447 if (retries-- < 1)
1448 break;
1449 }
1450
1451 /* Block idling for at least 1s */
1452 musb_platform_try_idle(musb,
1453 jiffies + msecs_to_jiffies(1 * HZ));
1454
1455 status = 0;
1456 goto done;
1457 default:
1458 DBG(2, "Unhandled wake: %s\n", otg_state_string(musb));
1459 goto done;
1460 }
1461
1462 status = 0;
1463
1464 power = musb_readb(mregs, MUSB_POWER);
1465 power |= MUSB_POWER_RESUME;
1466 musb_writeb(mregs, MUSB_POWER, power);
1467 DBG(2, "issue wakeup\n");
1468
1469 /* FIXME do this next chunk in a timer callback, no udelay */
1470 mdelay(2);
1471
1472 power = musb_readb(mregs, MUSB_POWER);
1473 power &= ~MUSB_POWER_RESUME;
1474 musb_writeb(mregs, MUSB_POWER, power);
1475done:
1476 spin_unlock_irqrestore(&musb->lock, flags);
1477 return status;
1478}
1479
1480static int
1481musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1482{
1483 struct musb *musb = gadget_to_musb(gadget);
1484
1485 musb->is_self_powered = !!is_selfpowered;
1486 return 0;
1487}
1488
1489static void musb_pullup(struct musb *musb, int is_on)
1490{
1491 u8 power;
1492
1493 power = musb_readb(musb->mregs, MUSB_POWER);
1494 if (is_on)
1495 power |= MUSB_POWER_SOFTCONN;
1496 else
1497 power &= ~MUSB_POWER_SOFTCONN;
1498
1499 /* FIXME if on, HdrcStart; if off, HdrcStop */
1500
1501 DBG(3, "gadget %s D+ pullup %s\n",
1502 musb->gadget_driver->function, is_on ? "on" : "off");
1503 musb_writeb(musb->mregs, MUSB_POWER, power);
1504}
1505
1506#if 0
1507static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1508{
1509 DBG(2, "<= %s =>\n", __func__);
1510
1511 /*
1512 * FIXME iff driver's softconnect flag is set (as it is during probe,
1513 * though that can clear it), just musb_pullup().
1514 */
1515
1516 return -EINVAL;
1517}
1518#endif
1519
1520static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1521{
1522 struct musb *musb = gadget_to_musb(gadget);
1523
David Brownell84e250f2009-03-31 12:30:04 -07001524 if (!musb->xceiv->set_power)
Felipe Balbi550a7372008-07-24 12:27:36 +03001525 return -EOPNOTSUPP;
David Brownell84e250f2009-03-31 12:30:04 -07001526 return otg_set_power(musb->xceiv, mA);
Felipe Balbi550a7372008-07-24 12:27:36 +03001527}
1528
1529static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1530{
1531 struct musb *musb = gadget_to_musb(gadget);
1532 unsigned long flags;
1533
1534 is_on = !!is_on;
1535
1536 /* NOTE: this assumes we are sensing vbus; we'd rather
1537 * not pullup unless the B-session is active.
1538 */
1539 spin_lock_irqsave(&musb->lock, flags);
1540 if (is_on != musb->softconnect) {
1541 musb->softconnect = is_on;
1542 musb_pullup(musb, is_on);
1543 }
1544 spin_unlock_irqrestore(&musb->lock, flags);
1545 return 0;
1546}
1547
1548static const struct usb_gadget_ops musb_gadget_operations = {
1549 .get_frame = musb_gadget_get_frame,
1550 .wakeup = musb_gadget_wakeup,
1551 .set_selfpowered = musb_gadget_set_self_powered,
1552 /* .vbus_session = musb_gadget_vbus_session, */
1553 .vbus_draw = musb_gadget_vbus_draw,
1554 .pullup = musb_gadget_pullup,
1555};
1556
1557/* ----------------------------------------------------------------------- */
1558
1559/* Registration */
1560
1561/* Only this registration code "knows" the rule (from USB standards)
1562 * about there being only one external upstream port. It assumes
1563 * all peripheral ports are external...
1564 */
1565static struct musb *the_gadget;
1566
1567static void musb_gadget_release(struct device *dev)
1568{
1569 /* kref_put(WHAT) */
1570 dev_dbg(dev, "%s\n", __func__);
1571}
1572
1573
1574static void __init
1575init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1576{
1577 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1578
1579 memset(ep, 0, sizeof *ep);
1580
1581 ep->current_epnum = epnum;
1582 ep->musb = musb;
1583 ep->hw_ep = hw_ep;
1584 ep->is_in = is_in;
1585
1586 INIT_LIST_HEAD(&ep->req_list);
1587
1588 sprintf(ep->name, "ep%d%s", epnum,
1589 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1590 is_in ? "in" : "out"));
1591 ep->end_point.name = ep->name;
1592 INIT_LIST_HEAD(&ep->end_point.ep_list);
1593 if (!epnum) {
1594 ep->end_point.maxpacket = 64;
1595 ep->end_point.ops = &musb_g_ep0_ops;
1596 musb->g.ep0 = &ep->end_point;
1597 } else {
1598 if (is_in)
1599 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
1600 else
1601 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
1602 ep->end_point.ops = &musb_ep_ops;
1603 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1604 }
1605}
1606
1607/*
1608 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1609 * to the rest of the driver state.
1610 */
1611static inline void __init musb_g_init_endpoints(struct musb *musb)
1612{
1613 u8 epnum;
1614 struct musb_hw_ep *hw_ep;
1615 unsigned count = 0;
1616
1617 /* intialize endpoint list just once */
1618 INIT_LIST_HEAD(&(musb->g.ep_list));
1619
1620 for (epnum = 0, hw_ep = musb->endpoints;
1621 epnum < musb->nr_endpoints;
1622 epnum++, hw_ep++) {
1623 if (hw_ep->is_shared_fifo /* || !epnum */) {
1624 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1625 count++;
1626 } else {
1627 if (hw_ep->max_packet_sz_tx) {
1628 init_peripheral_ep(musb, &hw_ep->ep_in,
1629 epnum, 1);
1630 count++;
1631 }
1632 if (hw_ep->max_packet_sz_rx) {
1633 init_peripheral_ep(musb, &hw_ep->ep_out,
1634 epnum, 0);
1635 count++;
1636 }
1637 }
1638 }
1639}
1640
1641/* called once during driver setup to initialize and link into
1642 * the driver model; memory is zeroed.
1643 */
1644int __init musb_gadget_setup(struct musb *musb)
1645{
1646 int status;
1647
1648 /* REVISIT minor race: if (erroneously) setting up two
1649 * musb peripherals at the same time, only the bus lock
1650 * is probably held.
1651 */
1652 if (the_gadget)
1653 return -EBUSY;
1654 the_gadget = musb;
1655
1656 musb->g.ops = &musb_gadget_operations;
1657 musb->g.is_dualspeed = 1;
1658 musb->g.speed = USB_SPEED_UNKNOWN;
1659
1660 /* this "gadget" abstracts/virtualizes the controller */
Kay Sievers427c4f32008-11-07 01:52:53 +01001661 dev_set_name(&musb->g.dev, "gadget");
Felipe Balbi550a7372008-07-24 12:27:36 +03001662 musb->g.dev.parent = musb->controller;
1663 musb->g.dev.dma_mask = musb->controller->dma_mask;
1664 musb->g.dev.release = musb_gadget_release;
1665 musb->g.name = musb_driver_name;
1666
1667 if (is_otg_enabled(musb))
1668 musb->g.is_otg = 1;
1669
1670 musb_g_init_endpoints(musb);
1671
1672 musb->is_active = 0;
1673 musb_platform_try_idle(musb, 0);
1674
1675 status = device_register(&musb->g.dev);
1676 if (status != 0)
1677 the_gadget = NULL;
1678 return status;
1679}
1680
1681void musb_gadget_cleanup(struct musb *musb)
1682{
1683 if (musb != the_gadget)
1684 return;
1685
1686 device_unregister(&musb->g.dev);
1687 the_gadget = NULL;
1688}
1689
1690/*
1691 * Register the gadget driver. Used by gadget drivers when
1692 * registering themselves with the controller.
1693 *
1694 * -EINVAL something went wrong (not driver)
1695 * -EBUSY another gadget is already using the controller
1696 * -ENOMEM no memeory to perform the operation
1697 *
1698 * @param driver the gadget driver
1699 * @return <0 if error, 0 if everything is fine
1700 */
1701int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1702{
1703 int retval;
1704 unsigned long flags;
1705 struct musb *musb = the_gadget;
1706
1707 if (!driver
1708 || driver->speed != USB_SPEED_HIGH
1709 || !driver->bind
1710 || !driver->setup)
1711 return -EINVAL;
1712
1713 /* driver must be initialized to support peripheral mode */
Roel Kluin08e6c972010-02-02 14:47:17 -08001714 if (!musb) {
Felipe Balbi550a7372008-07-24 12:27:36 +03001715 DBG(1, "%s, no dev??\n", __func__);
1716 return -ENODEV;
1717 }
1718
1719 DBG(3, "registering driver %s\n", driver->function);
1720 spin_lock_irqsave(&musb->lock, flags);
1721
1722 if (musb->gadget_driver) {
1723 DBG(1, "%s is already bound to %s\n",
1724 musb_driver_name,
1725 musb->gadget_driver->driver.name);
1726 retval = -EBUSY;
1727 } else {
1728 musb->gadget_driver = driver;
1729 musb->g.dev.driver = &driver->driver;
1730 driver->driver.bus = NULL;
1731 musb->softconnect = 1;
1732 retval = 0;
1733 }
1734
1735 spin_unlock_irqrestore(&musb->lock, flags);
1736
Felipe Balbi550a7372008-07-24 12:27:36 +03001737 if (retval == 0) {
Felipe Balbif362a472008-08-04 13:53:52 +03001738 retval = driver->bind(&musb->g);
1739 if (retval != 0) {
1740 DBG(3, "bind to driver %s failed --> %d\n",
1741 driver->driver.name, retval);
1742 musb->gadget_driver = NULL;
1743 musb->g.dev.driver = NULL;
1744 }
1745
Felipe Balbi550a7372008-07-24 12:27:36 +03001746 spin_lock_irqsave(&musb->lock, flags);
1747
David Brownell84e250f2009-03-31 12:30:04 -07001748 otg_set_peripheral(musb->xceiv, &musb->g);
Arnaud Mandyd4c433f2009-12-15 13:29:58 +02001749 musb->xceiv->state = OTG_STATE_B_IDLE;
Felipe Balbi550a7372008-07-24 12:27:36 +03001750 musb->is_active = 1;
1751
1752 /* FIXME this ignores the softconnect flag. Drivers are
1753 * allowed hold the peripheral inactive until for example
1754 * userspace hooks up printer hardware or DSP codecs, so
1755 * hosts only see fully functional devices.
1756 */
1757
1758 if (!is_otg_enabled(musb))
1759 musb_start(musb);
1760
David Brownell84e250f2009-03-31 12:30:04 -07001761 otg_set_peripheral(musb->xceiv, &musb->g);
1762
Felipe Balbi550a7372008-07-24 12:27:36 +03001763 spin_unlock_irqrestore(&musb->lock, flags);
1764
1765 if (is_otg_enabled(musb)) {
1766 DBG(3, "OTG startup...\n");
1767
1768 /* REVISIT: funcall to other code, which also
1769 * handles power budgeting ... this way also
1770 * ensures HdrcStart is indirectly called.
1771 */
1772 retval = usb_add_hcd(musb_to_hcd(musb), -1, 0);
1773 if (retval < 0) {
1774 DBG(1, "add_hcd failed, %d\n", retval);
1775 spin_lock_irqsave(&musb->lock, flags);
David Brownell84e250f2009-03-31 12:30:04 -07001776 otg_set_peripheral(musb->xceiv, NULL);
Felipe Balbi550a7372008-07-24 12:27:36 +03001777 musb->gadget_driver = NULL;
1778 musb->g.dev.driver = NULL;
1779 spin_unlock_irqrestore(&musb->lock, flags);
1780 }
1781 }
1782 }
1783
1784 return retval;
1785}
1786EXPORT_SYMBOL(usb_gadget_register_driver);
1787
1788static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
1789{
1790 int i;
1791 struct musb_hw_ep *hw_ep;
1792
1793 /* don't disconnect if it's not connected */
1794 if (musb->g.speed == USB_SPEED_UNKNOWN)
1795 driver = NULL;
1796 else
1797 musb->g.speed = USB_SPEED_UNKNOWN;
1798
1799 /* deactivate the hardware */
1800 if (musb->softconnect) {
1801 musb->softconnect = 0;
1802 musb_pullup(musb, 0);
1803 }
1804 musb_stop(musb);
1805
1806 /* killing any outstanding requests will quiesce the driver;
1807 * then report disconnect
1808 */
1809 if (driver) {
1810 for (i = 0, hw_ep = musb->endpoints;
1811 i < musb->nr_endpoints;
1812 i++, hw_ep++) {
1813 musb_ep_select(musb->mregs, i);
1814 if (hw_ep->is_shared_fifo /* || !epnum */) {
1815 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1816 } else {
1817 if (hw_ep->max_packet_sz_tx)
1818 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1819 if (hw_ep->max_packet_sz_rx)
1820 nuke(&hw_ep->ep_out, -ESHUTDOWN);
1821 }
1822 }
1823
1824 spin_unlock(&musb->lock);
1825 driver->disconnect(&musb->g);
1826 spin_lock(&musb->lock);
1827 }
1828}
1829
1830/*
1831 * Unregister the gadget driver. Used by gadget drivers when
1832 * unregistering themselves from the controller.
1833 *
1834 * @param driver the gadget driver to unregister
1835 */
1836int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1837{
1838 unsigned long flags;
1839 int retval = 0;
1840 struct musb *musb = the_gadget;
1841
1842 if (!driver || !driver->unbind || !musb)
1843 return -EINVAL;
1844
1845 /* REVISIT always use otg_set_peripheral() here too;
1846 * this needs to shut down the OTG engine.
1847 */
1848
1849 spin_lock_irqsave(&musb->lock, flags);
1850
1851#ifdef CONFIG_USB_MUSB_OTG
1852 musb_hnp_stop(musb);
1853#endif
1854
1855 if (musb->gadget_driver == driver) {
1856
1857 (void) musb_gadget_vbus_draw(&musb->g, 0);
1858
David Brownell84e250f2009-03-31 12:30:04 -07001859 musb->xceiv->state = OTG_STATE_UNDEFINED;
Felipe Balbi550a7372008-07-24 12:27:36 +03001860 stop_activity(musb, driver);
David Brownell84e250f2009-03-31 12:30:04 -07001861 otg_set_peripheral(musb->xceiv, NULL);
Felipe Balbi550a7372008-07-24 12:27:36 +03001862
1863 DBG(3, "unregistering driver %s\n", driver->function);
1864 spin_unlock_irqrestore(&musb->lock, flags);
1865 driver->unbind(&musb->g);
1866 spin_lock_irqsave(&musb->lock, flags);
1867
1868 musb->gadget_driver = NULL;
1869 musb->g.dev.driver = NULL;
1870
1871 musb->is_active = 0;
1872 musb_platform_try_idle(musb, 0);
1873 } else
1874 retval = -EINVAL;
1875 spin_unlock_irqrestore(&musb->lock, flags);
1876
1877 if (is_otg_enabled(musb) && retval == 0) {
1878 usb_remove_hcd(musb_to_hcd(musb));
1879 /* FIXME we need to be able to register another
1880 * gadget driver here and have everything work;
1881 * that currently misbehaves.
1882 */
1883 }
1884
1885 return retval;
1886}
1887EXPORT_SYMBOL(usb_gadget_unregister_driver);
1888
1889
1890/* ----------------------------------------------------------------------- */
1891
1892/* lifecycle operations called through plat_uds.c */
1893
1894void musb_g_resume(struct musb *musb)
1895{
1896 musb->is_suspended = 0;
David Brownell84e250f2009-03-31 12:30:04 -07001897 switch (musb->xceiv->state) {
Felipe Balbi550a7372008-07-24 12:27:36 +03001898 case OTG_STATE_B_IDLE:
1899 break;
1900 case OTG_STATE_B_WAIT_ACON:
1901 case OTG_STATE_B_PERIPHERAL:
1902 musb->is_active = 1;
1903 if (musb->gadget_driver && musb->gadget_driver->resume) {
1904 spin_unlock(&musb->lock);
1905 musb->gadget_driver->resume(&musb->g);
1906 spin_lock(&musb->lock);
1907 }
1908 break;
1909 default:
1910 WARNING("unhandled RESUME transition (%s)\n",
1911 otg_state_string(musb));
1912 }
1913}
1914
1915/* called when SOF packets stop for 3+ msec */
1916void musb_g_suspend(struct musb *musb)
1917{
1918 u8 devctl;
1919
1920 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1921 DBG(3, "devctl %02x\n", devctl);
1922
David Brownell84e250f2009-03-31 12:30:04 -07001923 switch (musb->xceiv->state) {
Felipe Balbi550a7372008-07-24 12:27:36 +03001924 case OTG_STATE_B_IDLE:
1925 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
David Brownell84e250f2009-03-31 12:30:04 -07001926 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
Felipe Balbi550a7372008-07-24 12:27:36 +03001927 break;
1928 case OTG_STATE_B_PERIPHERAL:
1929 musb->is_suspended = 1;
1930 if (musb->gadget_driver && musb->gadget_driver->suspend) {
1931 spin_unlock(&musb->lock);
1932 musb->gadget_driver->suspend(&musb->g);
1933 spin_lock(&musb->lock);
1934 }
1935 break;
1936 default:
1937 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
1938 * A_PERIPHERAL may need care too
1939 */
1940 WARNING("unhandled SUSPEND transition (%s)\n",
1941 otg_state_string(musb));
1942 }
1943}
1944
1945/* Called during SRP */
1946void musb_g_wakeup(struct musb *musb)
1947{
1948 musb_gadget_wakeup(&musb->g);
1949}
1950
1951/* called when VBUS drops below session threshold, and in other cases */
1952void musb_g_disconnect(struct musb *musb)
1953{
1954 void __iomem *mregs = musb->mregs;
1955 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
1956
1957 DBG(3, "devctl %02x\n", devctl);
1958
1959 /* clear HR */
1960 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
1961
1962 /* don't draw vbus until new b-default session */
1963 (void) musb_gadget_vbus_draw(&musb->g, 0);
1964
1965 musb->g.speed = USB_SPEED_UNKNOWN;
1966 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
1967 spin_unlock(&musb->lock);
1968 musb->gadget_driver->disconnect(&musb->g);
1969 spin_lock(&musb->lock);
1970 }
1971
David Brownell84e250f2009-03-31 12:30:04 -07001972 switch (musb->xceiv->state) {
Felipe Balbi550a7372008-07-24 12:27:36 +03001973 default:
1974#ifdef CONFIG_USB_MUSB_OTG
1975 DBG(2, "Unhandled disconnect %s, setting a_idle\n",
1976 otg_state_string(musb));
David Brownell84e250f2009-03-31 12:30:04 -07001977 musb->xceiv->state = OTG_STATE_A_IDLE;
David Brownellab983f2a2009-03-31 12:35:09 -07001978 MUSB_HST_MODE(musb);
Felipe Balbi550a7372008-07-24 12:27:36 +03001979 break;
1980 case OTG_STATE_A_PERIPHERAL:
David Brownell1de00da2009-04-02 10:16:11 -07001981 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
David Brownellab983f2a2009-03-31 12:35:09 -07001982 MUSB_HST_MODE(musb);
Felipe Balbi550a7372008-07-24 12:27:36 +03001983 break;
1984 case OTG_STATE_B_WAIT_ACON:
1985 case OTG_STATE_B_HOST:
1986#endif
1987 case OTG_STATE_B_PERIPHERAL:
1988 case OTG_STATE_B_IDLE:
David Brownell84e250f2009-03-31 12:30:04 -07001989 musb->xceiv->state = OTG_STATE_B_IDLE;
Felipe Balbi550a7372008-07-24 12:27:36 +03001990 break;
1991 case OTG_STATE_B_SRP_INIT:
1992 break;
1993 }
1994
1995 musb->is_active = 0;
1996}
1997
1998void musb_g_reset(struct musb *musb)
1999__releases(musb->lock)
2000__acquires(musb->lock)
2001{
2002 void __iomem *mbase = musb->mregs;
2003 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
2004 u8 power;
2005
2006 DBG(3, "<== %s addr=%x driver '%s'\n",
2007 (devctl & MUSB_DEVCTL_BDEVICE)
2008 ? "B-Device" : "A-Device",
2009 musb_readb(mbase, MUSB_FADDR),
2010 musb->gadget_driver
2011 ? musb->gadget_driver->driver.name
2012 : NULL
2013 );
2014
2015 /* report disconnect, if we didn't already (flushing EP state) */
2016 if (musb->g.speed != USB_SPEED_UNKNOWN)
2017 musb_g_disconnect(musb);
2018
2019 /* clear HR */
2020 else if (devctl & MUSB_DEVCTL_HR)
2021 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2022
2023
2024 /* what speed did we negotiate? */
2025 power = musb_readb(mbase, MUSB_POWER);
2026 musb->g.speed = (power & MUSB_POWER_HSMODE)
2027 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2028
2029 /* start in USB_STATE_DEFAULT */
2030 musb->is_active = 1;
2031 musb->is_suspended = 0;
2032 MUSB_DEV_MODE(musb);
2033 musb->address = 0;
2034 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2035
2036 musb->may_wakeup = 0;
2037 musb->g.b_hnp_enable = 0;
2038 musb->g.a_alt_hnp_support = 0;
2039 musb->g.a_hnp_support = 0;
2040
2041 /* Normal reset, as B-Device;
2042 * or else after HNP, as A-Device
2043 */
2044 if (devctl & MUSB_DEVCTL_BDEVICE) {
David Brownell84e250f2009-03-31 12:30:04 -07002045 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
Felipe Balbi550a7372008-07-24 12:27:36 +03002046 musb->g.is_a_peripheral = 0;
2047 } else if (is_otg_enabled(musb)) {
David Brownell84e250f2009-03-31 12:30:04 -07002048 musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
Felipe Balbi550a7372008-07-24 12:27:36 +03002049 musb->g.is_a_peripheral = 1;
2050 } else
2051 WARN_ON(1);
2052
2053 /* start with default limits on VBUS power draw */
2054 (void) musb_gadget_vbus_draw(&musb->g,
2055 is_otg_enabled(musb) ? 8 : 100);
2056}