Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1 | /* |
| 2 | * TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface |
| 3 | * |
| 4 | * Copyright (C) 2006 Nokia Corporation |
| 5 | * Tony Lindgren <tony@atomide.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | #include <linux/module.h> |
| 12 | #include <linux/kernel.h> |
| 13 | #include <linux/errno.h> |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 14 | #include <linux/usb.h> |
| 15 | #include <linux/platform_device.h> |
| 16 | #include <linux/dma-mapping.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 17 | #include <linux/slab.h> |
Tony Lindgren | 45c3eb7 | 2012-11-30 08:41:50 -0800 | [diff] [blame] | 18 | #include <linux/omap-dma.h> |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 19 | |
| 20 | #include "musb_core.h" |
Felipe Balbi | 240a16e | 2011-08-05 13:29:49 +0300 | [diff] [blame] | 21 | #include "tusb6010.h" |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 22 | |
| 23 | #define to_chdat(c) ((struct tusb_omap_dma_ch *)(c)->private_data) |
| 24 | |
| 25 | #define MAX_DMAREQ 5 /* REVISIT: Really 6, but req5 not OK */ |
| 26 | |
Lokesh Vutla | d5e7c86 | 2012-10-15 14:03:51 -0700 | [diff] [blame] | 27 | #define OMAP24XX_DMA_EXT_DMAREQ0 2 |
| 28 | #define OMAP24XX_DMA_EXT_DMAREQ1 3 |
| 29 | #define OMAP242X_DMA_EXT_DMAREQ2 14 |
| 30 | #define OMAP242X_DMA_EXT_DMAREQ3 15 |
| 31 | #define OMAP242X_DMA_EXT_DMAREQ4 16 |
| 32 | #define OMAP242X_DMA_EXT_DMAREQ5 64 |
| 33 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 34 | struct tusb_omap_dma_ch { |
| 35 | struct musb *musb; |
| 36 | void __iomem *tbase; |
| 37 | unsigned long phys_offset; |
| 38 | int epnum; |
| 39 | u8 tx; |
| 40 | struct musb_hw_ep *hw_ep; |
| 41 | |
| 42 | int ch; |
| 43 | s8 dmareq; |
| 44 | s8 sync_dev; |
| 45 | |
| 46 | struct tusb_omap_dma *tusb_dma; |
| 47 | |
Tony Lindgren | 1d0f11b | 2010-04-23 17:41:15 -0700 | [diff] [blame] | 48 | dma_addr_t dma_addr; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 49 | |
| 50 | u32 len; |
| 51 | u16 packet_sz; |
| 52 | u16 transfer_packet_sz; |
| 53 | u32 transfer_len; |
| 54 | u32 completed_len; |
| 55 | }; |
| 56 | |
| 57 | struct tusb_omap_dma { |
| 58 | struct dma_controller controller; |
| 59 | struct musb *musb; |
| 60 | void __iomem *tbase; |
| 61 | |
| 62 | int ch; |
| 63 | s8 dmareq; |
| 64 | s8 sync_dev; |
| 65 | unsigned multichannel:1; |
| 66 | }; |
| 67 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 68 | /* |
| 69 | * Allocate dmareq0 to the current channel unless it's already taken |
| 70 | */ |
| 71 | static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat) |
| 72 | { |
| 73 | u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); |
| 74 | |
| 75 | if (reg != 0) { |
Sergei Trofimovich | 74c6f3a | 2011-07-17 18:28:00 +0300 | [diff] [blame] | 76 | dev_dbg(chdat->musb->controller, "ep%i dmareq0 is busy for ep%i\n", |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 77 | chdat->epnum, reg & 0xf); |
| 78 | return -EAGAIN; |
| 79 | } |
| 80 | |
| 81 | if (chdat->tx) |
| 82 | reg = (1 << 4) | chdat->epnum; |
| 83 | else |
| 84 | reg = chdat->epnum; |
| 85 | |
| 86 | musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); |
| 87 | |
| 88 | return 0; |
| 89 | } |
| 90 | |
| 91 | static inline void tusb_omap_free_shared_dmareq(struct tusb_omap_dma_ch *chdat) |
| 92 | { |
| 93 | u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); |
| 94 | |
| 95 | if ((reg & 0xf) != chdat->epnum) { |
| 96 | printk(KERN_ERR "ep%i trying to release dmareq0 for ep%i\n", |
| 97 | chdat->epnum, reg & 0xf); |
| 98 | return; |
| 99 | } |
| 100 | musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, 0); |
| 101 | } |
| 102 | |
| 103 | /* |
| 104 | * See also musb_dma_completion in plat_uds.c and musb_g_[tx|rx]() in |
| 105 | * musb_gadget.c. |
| 106 | */ |
| 107 | static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data) |
| 108 | { |
| 109 | struct dma_channel *channel = (struct dma_channel *)data; |
| 110 | struct tusb_omap_dma_ch *chdat = to_chdat(channel); |
| 111 | struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; |
| 112 | struct musb *musb = chdat->musb; |
Tony Lindgren | 1d0f11b | 2010-04-23 17:41:15 -0700 | [diff] [blame] | 113 | struct device *dev = musb->controller; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 114 | struct musb_hw_ep *hw_ep = chdat->hw_ep; |
| 115 | void __iomem *ep_conf = hw_ep->conf; |
| 116 | void __iomem *mbase = musb->mregs; |
| 117 | unsigned long remaining, flags, pio; |
| 118 | int ch; |
| 119 | |
| 120 | spin_lock_irqsave(&musb->lock, flags); |
| 121 | |
| 122 | if (tusb_dma->multichannel) |
| 123 | ch = chdat->ch; |
| 124 | else |
| 125 | ch = tusb_dma->ch; |
| 126 | |
| 127 | if (ch_status != OMAP_DMA_BLOCK_IRQ) |
| 128 | printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status); |
| 129 | |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 130 | dev_dbg(musb->controller, "ep%i %s dma callback ch: %i status: %x\n", |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 131 | chdat->epnum, chdat->tx ? "tx" : "rx", |
| 132 | ch, ch_status); |
| 133 | |
| 134 | if (chdat->tx) |
| 135 | remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET); |
| 136 | else |
| 137 | remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET); |
| 138 | |
| 139 | remaining = TUSB_EP_CONFIG_XFR_SIZE(remaining); |
| 140 | |
| 141 | /* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */ |
| 142 | if (unlikely(remaining > chdat->transfer_len)) { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 143 | dev_dbg(musb->controller, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n", |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 144 | chdat->tx ? "tx" : "rx", chdat->ch, |
| 145 | remaining); |
| 146 | remaining = 0; |
| 147 | } |
| 148 | |
| 149 | channel->actual_len = chdat->transfer_len - remaining; |
| 150 | pio = chdat->len - channel->actual_len; |
| 151 | |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 152 | dev_dbg(musb->controller, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 153 | |
| 154 | /* Transfer remaining 1 - 31 bytes */ |
| 155 | if (pio > 0 && pio < 32) { |
| 156 | u8 *buf; |
| 157 | |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 158 | dev_dbg(musb->controller, "Using PIO for remaining %lu bytes\n", pio); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 159 | buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len; |
| 160 | if (chdat->tx) { |
Tony Lindgren | 1d0f11b | 2010-04-23 17:41:15 -0700 | [diff] [blame] | 161 | dma_unmap_single(dev, chdat->dma_addr, |
| 162 | chdat->transfer_len, |
| 163 | DMA_TO_DEVICE); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 164 | musb_write_fifo(hw_ep, pio, buf); |
| 165 | } else { |
Tony Lindgren | 1d0f11b | 2010-04-23 17:41:15 -0700 | [diff] [blame] | 166 | dma_unmap_single(dev, chdat->dma_addr, |
| 167 | chdat->transfer_len, |
| 168 | DMA_FROM_DEVICE); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 169 | musb_read_fifo(hw_ep, pio, buf); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 170 | } |
| 171 | channel->actual_len += pio; |
| 172 | } |
| 173 | |
| 174 | if (!tusb_dma->multichannel) |
| 175 | tusb_omap_free_shared_dmareq(chdat); |
| 176 | |
| 177 | channel->status = MUSB_DMA_STATUS_FREE; |
| 178 | |
| 179 | /* Handle only RX callbacks here. TX callbacks must be handled based |
| 180 | * on the TUSB DMA status interrupt. |
| 181 | * REVISIT: Use both TUSB DMA status interrupt and OMAP DMA callback |
| 182 | * interrupt for RX and TX. |
| 183 | */ |
| 184 | if (!chdat->tx) |
| 185 | musb_dma_completion(musb, chdat->epnum, chdat->tx); |
| 186 | |
| 187 | /* We must terminate short tx transfers manually by setting TXPKTRDY. |
| 188 | * REVISIT: This same problem may occur with other MUSB dma as well. |
| 189 | * Easy to test with g_ether by pinging the MUSB board with ping -s54. |
| 190 | */ |
| 191 | if ((chdat->transfer_len < chdat->packet_sz) |
| 192 | || (chdat->transfer_len % chdat->packet_sz != 0)) { |
| 193 | u16 csr; |
| 194 | |
| 195 | if (chdat->tx) { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 196 | dev_dbg(musb->controller, "terminating short tx packet\n"); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 197 | musb_ep_select(mbase, chdat->epnum); |
| 198 | csr = musb_readw(hw_ep->regs, MUSB_TXCSR); |
| 199 | csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY |
| 200 | | MUSB_TXCSR_P_WZC_BITS; |
| 201 | musb_writew(hw_ep->regs, MUSB_TXCSR, csr); |
| 202 | } |
| 203 | } |
| 204 | |
| 205 | spin_unlock_irqrestore(&musb->lock, flags); |
| 206 | } |
| 207 | |
| 208 | static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz, |
| 209 | u8 rndis_mode, dma_addr_t dma_addr, u32 len) |
| 210 | { |
| 211 | struct tusb_omap_dma_ch *chdat = to_chdat(channel); |
| 212 | struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; |
| 213 | struct musb *musb = chdat->musb; |
Tony Lindgren | 1d0f11b | 2010-04-23 17:41:15 -0700 | [diff] [blame] | 214 | struct device *dev = musb->controller; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 215 | struct musb_hw_ep *hw_ep = chdat->hw_ep; |
| 216 | void __iomem *mbase = musb->mregs; |
| 217 | void __iomem *ep_conf = hw_ep->conf; |
| 218 | dma_addr_t fifo = hw_ep->fifo_sync; |
| 219 | struct omap_dma_channel_params dma_params; |
| 220 | u32 dma_remaining; |
| 221 | int src_burst, dst_burst; |
| 222 | u16 csr; |
Peter Ujfalusi | 08c735a | 2017-05-17 11:23:11 -0500 | [diff] [blame] | 223 | u32 psize; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 224 | int ch; |
| 225 | s8 dmareq; |
| 226 | s8 sync_dev; |
| 227 | |
| 228 | if (unlikely(dma_addr & 0x1) || (len < 32) || (len > packet_sz)) |
| 229 | return false; |
| 230 | |
| 231 | /* |
| 232 | * HW issue #10: Async dma will eventually corrupt the XFR_SIZE |
| 233 | * register which will cause missed DMA interrupt. We could try to |
| 234 | * use a timer for the callback, but it is unsafe as the XFR_SIZE |
| 235 | * register is corrupt, and we won't know if the DMA worked. |
| 236 | */ |
| 237 | if (dma_addr & 0x2) |
| 238 | return false; |
| 239 | |
| 240 | /* |
| 241 | * Because of HW issue #10, it seems like mixing sync DMA and async |
| 242 | * PIO access can confuse the DMA. Make sure XFR_SIZE is reset before |
| 243 | * using the channel for DMA. |
| 244 | */ |
| 245 | if (chdat->tx) |
| 246 | dma_remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET); |
| 247 | else |
| 248 | dma_remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET); |
| 249 | |
| 250 | dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining); |
| 251 | if (dma_remaining) { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 252 | dev_dbg(musb->controller, "Busy %s dma ch%i, not using: %08x\n", |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 253 | chdat->tx ? "tx" : "rx", chdat->ch, |
| 254 | dma_remaining); |
| 255 | return false; |
| 256 | } |
| 257 | |
| 258 | chdat->transfer_len = len & ~0x1f; |
| 259 | |
| 260 | if (len < packet_sz) |
| 261 | chdat->transfer_packet_sz = chdat->transfer_len; |
| 262 | else |
| 263 | chdat->transfer_packet_sz = packet_sz; |
| 264 | |
| 265 | if (tusb_dma->multichannel) { |
| 266 | ch = chdat->ch; |
| 267 | dmareq = chdat->dmareq; |
| 268 | sync_dev = chdat->sync_dev; |
| 269 | } else { |
| 270 | if (tusb_omap_use_shared_dmareq(chdat) != 0) { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 271 | dev_dbg(musb->controller, "could not get dma for ep%i\n", chdat->epnum); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 272 | return false; |
| 273 | } |
| 274 | if (tusb_dma->ch < 0) { |
| 275 | /* REVISIT: This should get blocked earlier, happens |
| 276 | * with MSC ErrorRecoveryTest |
| 277 | */ |
| 278 | WARN_ON(1); |
| 279 | return false; |
| 280 | } |
| 281 | |
| 282 | ch = tusb_dma->ch; |
| 283 | dmareq = tusb_dma->dmareq; |
| 284 | sync_dev = tusb_dma->sync_dev; |
| 285 | omap_set_dma_callback(ch, tusb_omap_dma_cb, channel); |
| 286 | } |
| 287 | |
| 288 | chdat->packet_sz = packet_sz; |
| 289 | chdat->len = len; |
| 290 | channel->actual_len = 0; |
Tony Lindgren | 1d0f11b | 2010-04-23 17:41:15 -0700 | [diff] [blame] | 291 | chdat->dma_addr = dma_addr; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 292 | channel->status = MUSB_DMA_STATUS_BUSY; |
| 293 | |
| 294 | /* Since we're recycling dma areas, we need to clean or invalidate */ |
| 295 | if (chdat->tx) |
Tony Lindgren | 1d0f11b | 2010-04-23 17:41:15 -0700 | [diff] [blame] | 296 | dma_map_single(dev, phys_to_virt(dma_addr), len, |
| 297 | DMA_TO_DEVICE); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 298 | else |
Tony Lindgren | 1d0f11b | 2010-04-23 17:41:15 -0700 | [diff] [blame] | 299 | dma_map_single(dev, phys_to_virt(dma_addr), len, |
| 300 | DMA_FROM_DEVICE); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 301 | |
| 302 | /* Use 16-bit transfer if dma_addr is not 32-bit aligned */ |
| 303 | if ((dma_addr & 0x3) == 0) { |
| 304 | dma_params.data_type = OMAP_DMA_DATA_TYPE_S32; |
| 305 | dma_params.elem_count = 8; /* Elements in frame */ |
| 306 | } else { |
| 307 | dma_params.data_type = OMAP_DMA_DATA_TYPE_S16; |
| 308 | dma_params.elem_count = 16; /* Elements in frame */ |
| 309 | fifo = hw_ep->fifo_async; |
| 310 | } |
| 311 | |
| 312 | dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */ |
| 313 | |
Arnd Bergmann | 3ec08dd | 2016-01-28 17:23:14 +0100 | [diff] [blame] | 314 | dev_dbg(musb->controller, "ep%i %s dma ch%i dma: %pad len: %u(%u) packet_sz: %i(%i)\n", |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 315 | chdat->epnum, chdat->tx ? "tx" : "rx", |
Arnd Bergmann | 3ec08dd | 2016-01-28 17:23:14 +0100 | [diff] [blame] | 316 | ch, &dma_addr, chdat->transfer_len, len, |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 317 | chdat->transfer_packet_sz, packet_sz); |
| 318 | |
| 319 | /* |
| 320 | * Prepare omap DMA for transfer |
| 321 | */ |
| 322 | if (chdat->tx) { |
| 323 | dma_params.src_amode = OMAP_DMA_AMODE_POST_INC; |
| 324 | dma_params.src_start = (unsigned long)dma_addr; |
| 325 | dma_params.src_ei = 0; |
| 326 | dma_params.src_fi = 0; |
| 327 | |
| 328 | dma_params.dst_amode = OMAP_DMA_AMODE_DOUBLE_IDX; |
| 329 | dma_params.dst_start = (unsigned long)fifo; |
| 330 | dma_params.dst_ei = 1; |
| 331 | dma_params.dst_fi = -31; /* Loop 32 byte window */ |
| 332 | |
| 333 | dma_params.trigger = sync_dev; |
| 334 | dma_params.sync_mode = OMAP_DMA_SYNC_FRAME; |
| 335 | dma_params.src_or_dst_synch = 0; /* Dest sync */ |
| 336 | |
| 337 | src_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 read */ |
| 338 | dst_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 write */ |
| 339 | } else { |
| 340 | dma_params.src_amode = OMAP_DMA_AMODE_DOUBLE_IDX; |
| 341 | dma_params.src_start = (unsigned long)fifo; |
| 342 | dma_params.src_ei = 1; |
| 343 | dma_params.src_fi = -31; /* Loop 32 byte window */ |
| 344 | |
| 345 | dma_params.dst_amode = OMAP_DMA_AMODE_POST_INC; |
| 346 | dma_params.dst_start = (unsigned long)dma_addr; |
| 347 | dma_params.dst_ei = 0; |
| 348 | dma_params.dst_fi = 0; |
| 349 | |
| 350 | dma_params.trigger = sync_dev; |
| 351 | dma_params.sync_mode = OMAP_DMA_SYNC_FRAME; |
| 352 | dma_params.src_or_dst_synch = 1; /* Source sync */ |
| 353 | |
| 354 | src_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 read */ |
| 355 | dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */ |
| 356 | } |
| 357 | |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 358 | dev_dbg(musb->controller, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n", |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 359 | chdat->epnum, chdat->tx ? "tx" : "rx", |
| 360 | (dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16, |
| 361 | ((dma_addr & 0x3) == 0) ? "sync" : "async", |
| 362 | dma_params.src_start, dma_params.dst_start); |
| 363 | |
| 364 | omap_set_dma_params(ch, &dma_params); |
| 365 | omap_set_dma_src_burst_mode(ch, src_burst); |
| 366 | omap_set_dma_dest_burst_mode(ch, dst_burst); |
| 367 | omap_set_dma_write_mode(ch, OMAP_DMA_WRITE_LAST_NON_POSTED); |
| 368 | |
| 369 | /* |
| 370 | * Prepare MUSB for DMA transfer |
| 371 | */ |
| 372 | if (chdat->tx) { |
| 373 | musb_ep_select(mbase, chdat->epnum); |
| 374 | csr = musb_readw(hw_ep->regs, MUSB_TXCSR); |
| 375 | csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB |
| 376 | | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE); |
| 377 | csr &= ~MUSB_TXCSR_P_UNDERRUN; |
| 378 | musb_writew(hw_ep->regs, MUSB_TXCSR, csr); |
| 379 | } else { |
| 380 | musb_ep_select(mbase, chdat->epnum); |
| 381 | csr = musb_readw(hw_ep->regs, MUSB_RXCSR); |
| 382 | csr |= MUSB_RXCSR_DMAENAB; |
| 383 | csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE); |
| 384 | musb_writew(hw_ep->regs, MUSB_RXCSR, |
| 385 | csr | MUSB_RXCSR_P_WZC_BITS); |
| 386 | } |
| 387 | |
| 388 | /* |
| 389 | * Start DMA transfer |
| 390 | */ |
| 391 | omap_start_dma(ch); |
| 392 | |
| 393 | if (chdat->tx) { |
| 394 | /* Send transfer_packet_sz packets at a time */ |
Peter Ujfalusi | 08c735a | 2017-05-17 11:23:11 -0500 | [diff] [blame] | 395 | psize = musb_readl(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET); |
| 396 | psize &= ~0x7ff; |
| 397 | psize |= chdat->transfer_packet_sz; |
| 398 | musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, psize); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 399 | |
| 400 | musb_writel(ep_conf, TUSB_EP_TX_OFFSET, |
| 401 | TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len)); |
| 402 | } else { |
| 403 | /* Receive transfer_packet_sz packets at a time */ |
Peter Ujfalusi | 08c735a | 2017-05-17 11:23:11 -0500 | [diff] [blame] | 404 | psize = musb_readl(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET); |
| 405 | psize &= ~(0x7ff << 16); |
| 406 | psize |= (chdat->transfer_packet_sz << 16); |
| 407 | musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, psize); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 408 | |
| 409 | musb_writel(ep_conf, TUSB_EP_RX_OFFSET, |
| 410 | TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len)); |
| 411 | } |
| 412 | |
| 413 | return true; |
| 414 | } |
| 415 | |
| 416 | static int tusb_omap_dma_abort(struct dma_channel *channel) |
| 417 | { |
| 418 | struct tusb_omap_dma_ch *chdat = to_chdat(channel); |
| 419 | struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; |
| 420 | |
| 421 | if (!tusb_dma->multichannel) { |
| 422 | if (tusb_dma->ch >= 0) { |
| 423 | omap_stop_dma(tusb_dma->ch); |
| 424 | omap_free_dma(tusb_dma->ch); |
| 425 | tusb_dma->ch = -1; |
| 426 | } |
| 427 | |
| 428 | tusb_dma->dmareq = -1; |
| 429 | tusb_dma->sync_dev = -1; |
| 430 | } |
| 431 | |
| 432 | channel->status = MUSB_DMA_STATUS_FREE; |
| 433 | |
| 434 | return 0; |
| 435 | } |
| 436 | |
| 437 | static inline int tusb_omap_dma_allocate_dmareq(struct tusb_omap_dma_ch *chdat) |
| 438 | { |
| 439 | u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); |
| 440 | int i, dmareq_nr = -1; |
| 441 | |
| 442 | const int sync_dev[6] = { |
| 443 | OMAP24XX_DMA_EXT_DMAREQ0, |
| 444 | OMAP24XX_DMA_EXT_DMAREQ1, |
| 445 | OMAP242X_DMA_EXT_DMAREQ2, |
| 446 | OMAP242X_DMA_EXT_DMAREQ3, |
| 447 | OMAP242X_DMA_EXT_DMAREQ4, |
| 448 | OMAP242X_DMA_EXT_DMAREQ5, |
| 449 | }; |
| 450 | |
| 451 | for (i = 0; i < MAX_DMAREQ; i++) { |
| 452 | int cur = (reg & (0xf << (i * 5))) >> (i * 5); |
| 453 | if (cur == 0) { |
| 454 | dmareq_nr = i; |
| 455 | break; |
| 456 | } |
| 457 | } |
| 458 | |
| 459 | if (dmareq_nr == -1) |
| 460 | return -EAGAIN; |
| 461 | |
| 462 | reg |= (chdat->epnum << (dmareq_nr * 5)); |
| 463 | if (chdat->tx) |
| 464 | reg |= ((1 << 4) << (dmareq_nr * 5)); |
| 465 | musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); |
| 466 | |
| 467 | chdat->dmareq = dmareq_nr; |
| 468 | chdat->sync_dev = sync_dev[chdat->dmareq]; |
| 469 | |
| 470 | return 0; |
| 471 | } |
| 472 | |
| 473 | static inline void tusb_omap_dma_free_dmareq(struct tusb_omap_dma_ch *chdat) |
| 474 | { |
| 475 | u32 reg; |
| 476 | |
| 477 | if (!chdat || chdat->dmareq < 0) |
| 478 | return; |
| 479 | |
| 480 | reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); |
| 481 | reg &= ~(0x1f << (chdat->dmareq * 5)); |
| 482 | musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); |
| 483 | |
| 484 | chdat->dmareq = -1; |
| 485 | chdat->sync_dev = -1; |
| 486 | } |
| 487 | |
| 488 | static struct dma_channel *dma_channel_pool[MAX_DMAREQ]; |
| 489 | |
| 490 | static struct dma_channel * |
| 491 | tusb_omap_dma_allocate(struct dma_controller *c, |
| 492 | struct musb_hw_ep *hw_ep, |
| 493 | u8 tx) |
| 494 | { |
| 495 | int ret, i; |
| 496 | const char *dev_name; |
| 497 | struct tusb_omap_dma *tusb_dma; |
| 498 | struct musb *musb; |
| 499 | void __iomem *tbase; |
| 500 | struct dma_channel *channel = NULL; |
| 501 | struct tusb_omap_dma_ch *chdat = NULL; |
| 502 | u32 reg; |
| 503 | |
| 504 | tusb_dma = container_of(c, struct tusb_omap_dma, controller); |
| 505 | musb = tusb_dma->musb; |
| 506 | tbase = musb->ctrl_base; |
| 507 | |
| 508 | reg = musb_readl(tbase, TUSB_DMA_INT_MASK); |
| 509 | if (tx) |
| 510 | reg &= ~(1 << hw_ep->epnum); |
| 511 | else |
| 512 | reg &= ~(1 << (hw_ep->epnum + 15)); |
| 513 | musb_writel(tbase, TUSB_DMA_INT_MASK, reg); |
| 514 | |
| 515 | /* REVISIT: Why does dmareq5 not work? */ |
| 516 | if (hw_ep->epnum == 0) { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 517 | dev_dbg(musb->controller, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx"); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 518 | return NULL; |
| 519 | } |
| 520 | |
| 521 | for (i = 0; i < MAX_DMAREQ; i++) { |
| 522 | struct dma_channel *ch = dma_channel_pool[i]; |
| 523 | if (ch->status == MUSB_DMA_STATUS_UNKNOWN) { |
| 524 | ch->status = MUSB_DMA_STATUS_FREE; |
| 525 | channel = ch; |
| 526 | chdat = ch->private_data; |
| 527 | break; |
| 528 | } |
| 529 | } |
| 530 | |
| 531 | if (!channel) |
| 532 | return NULL; |
| 533 | |
| 534 | if (tx) { |
| 535 | chdat->tx = 1; |
| 536 | dev_name = "TUSB transmit"; |
| 537 | } else { |
| 538 | chdat->tx = 0; |
| 539 | dev_name = "TUSB receive"; |
| 540 | } |
| 541 | |
| 542 | chdat->musb = tusb_dma->musb; |
| 543 | chdat->tbase = tusb_dma->tbase; |
| 544 | chdat->hw_ep = hw_ep; |
| 545 | chdat->epnum = hw_ep->epnum; |
| 546 | chdat->dmareq = -1; |
| 547 | chdat->completed_len = 0; |
| 548 | chdat->tusb_dma = tusb_dma; |
| 549 | |
| 550 | channel->max_len = 0x7fffffff; |
| 551 | channel->desired_mode = 0; |
| 552 | channel->actual_len = 0; |
| 553 | |
| 554 | if (tusb_dma->multichannel) { |
| 555 | ret = tusb_omap_dma_allocate_dmareq(chdat); |
| 556 | if (ret != 0) |
| 557 | goto free_dmareq; |
| 558 | |
| 559 | ret = omap_request_dma(chdat->sync_dev, dev_name, |
| 560 | tusb_omap_dma_cb, channel, &chdat->ch); |
| 561 | if (ret != 0) |
| 562 | goto free_dmareq; |
| 563 | } else if (tusb_dma->ch == -1) { |
| 564 | tusb_dma->dmareq = 0; |
| 565 | tusb_dma->sync_dev = OMAP24XX_DMA_EXT_DMAREQ0; |
| 566 | |
| 567 | /* Callback data gets set later in the shared dmareq case */ |
| 568 | ret = omap_request_dma(tusb_dma->sync_dev, "TUSB shared", |
| 569 | tusb_omap_dma_cb, NULL, &tusb_dma->ch); |
| 570 | if (ret != 0) |
| 571 | goto free_dmareq; |
| 572 | |
| 573 | chdat->dmareq = -1; |
| 574 | chdat->ch = -1; |
| 575 | } |
| 576 | |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 577 | dev_dbg(musb->controller, "ep%i %s dma: %s dma%i dmareq%i sync%i\n", |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 578 | chdat->epnum, |
| 579 | chdat->tx ? "tx" : "rx", |
| 580 | chdat->ch >= 0 ? "dedicated" : "shared", |
| 581 | chdat->ch >= 0 ? chdat->ch : tusb_dma->ch, |
| 582 | chdat->dmareq >= 0 ? chdat->dmareq : tusb_dma->dmareq, |
| 583 | chdat->sync_dev >= 0 ? chdat->sync_dev : tusb_dma->sync_dev); |
| 584 | |
| 585 | return channel; |
| 586 | |
| 587 | free_dmareq: |
| 588 | tusb_omap_dma_free_dmareq(chdat); |
| 589 | |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 590 | dev_dbg(musb->controller, "ep%i: Could not get a DMA channel\n", chdat->epnum); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 591 | channel->status = MUSB_DMA_STATUS_UNKNOWN; |
| 592 | |
| 593 | return NULL; |
| 594 | } |
| 595 | |
| 596 | static void tusb_omap_dma_release(struct dma_channel *channel) |
| 597 | { |
| 598 | struct tusb_omap_dma_ch *chdat = to_chdat(channel); |
| 599 | struct musb *musb = chdat->musb; |
| 600 | void __iomem *tbase = musb->ctrl_base; |
| 601 | u32 reg; |
| 602 | |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 603 | dev_dbg(musb->controller, "ep%i ch%i\n", chdat->epnum, chdat->ch); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 604 | |
| 605 | reg = musb_readl(tbase, TUSB_DMA_INT_MASK); |
| 606 | if (chdat->tx) |
| 607 | reg |= (1 << chdat->epnum); |
| 608 | else |
| 609 | reg |= (1 << (chdat->epnum + 15)); |
| 610 | musb_writel(tbase, TUSB_DMA_INT_MASK, reg); |
| 611 | |
| 612 | reg = musb_readl(tbase, TUSB_DMA_INT_CLEAR); |
| 613 | if (chdat->tx) |
| 614 | reg |= (1 << chdat->epnum); |
| 615 | else |
| 616 | reg |= (1 << (chdat->epnum + 15)); |
| 617 | musb_writel(tbase, TUSB_DMA_INT_CLEAR, reg); |
| 618 | |
| 619 | channel->status = MUSB_DMA_STATUS_UNKNOWN; |
| 620 | |
| 621 | if (chdat->ch >= 0) { |
| 622 | omap_stop_dma(chdat->ch); |
| 623 | omap_free_dma(chdat->ch); |
| 624 | chdat->ch = -1; |
| 625 | } |
| 626 | |
| 627 | if (chdat->dmareq >= 0) |
| 628 | tusb_omap_dma_free_dmareq(chdat); |
| 629 | |
| 630 | channel = NULL; |
| 631 | } |
| 632 | |
Tony Lindgren | 7f6283e | 2015-05-01 12:29:28 -0700 | [diff] [blame] | 633 | void tusb_dma_controller_destroy(struct dma_controller *c) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 634 | { |
| 635 | struct tusb_omap_dma *tusb_dma; |
| 636 | int i; |
| 637 | |
| 638 | tusb_dma = container_of(c, struct tusb_omap_dma, controller); |
| 639 | for (i = 0; i < MAX_DMAREQ; i++) { |
| 640 | struct dma_channel *ch = dma_channel_pool[i]; |
| 641 | if (ch) { |
| 642 | kfree(ch->private_data); |
| 643 | kfree(ch); |
| 644 | } |
| 645 | } |
| 646 | |
Roel Kluin | 94089d5 | 2010-01-09 21:57:44 +0100 | [diff] [blame] | 647 | if (tusb_dma && !tusb_dma->multichannel && tusb_dma->ch >= 0) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 648 | omap_free_dma(tusb_dma->ch); |
| 649 | |
| 650 | kfree(tusb_dma); |
| 651 | } |
Tony Lindgren | 7f6283e | 2015-05-01 12:29:28 -0700 | [diff] [blame] | 652 | EXPORT_SYMBOL_GPL(tusb_dma_controller_destroy); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 653 | |
Tony Lindgren | 7f6283e | 2015-05-01 12:29:28 -0700 | [diff] [blame] | 654 | struct dma_controller * |
| 655 | tusb_dma_controller_create(struct musb *musb, void __iomem *base) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 656 | { |
| 657 | void __iomem *tbase = musb->ctrl_base; |
| 658 | struct tusb_omap_dma *tusb_dma; |
| 659 | int i; |
| 660 | |
| 661 | /* REVISIT: Get dmareq lines used from board-*.c */ |
| 662 | |
| 663 | musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff); |
| 664 | musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0); |
| 665 | |
| 666 | musb_writel(tbase, TUSB_DMA_REQ_CONF, |
| 667 | TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
| 668 | | TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
| 669 | | TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2)); |
| 670 | |
| 671 | tusb_dma = kzalloc(sizeof(struct tusb_omap_dma), GFP_KERNEL); |
| 672 | if (!tusb_dma) |
Huzaifa Sidhpurwala | c88ba39 | 2011-03-01 15:54:22 +0530 | [diff] [blame] | 673 | goto out; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 674 | |
| 675 | tusb_dma->musb = musb; |
| 676 | tusb_dma->tbase = musb->ctrl_base; |
| 677 | |
| 678 | tusb_dma->ch = -1; |
| 679 | tusb_dma->dmareq = -1; |
| 680 | tusb_dma->sync_dev = -1; |
| 681 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 682 | tusb_dma->controller.channel_alloc = tusb_omap_dma_allocate; |
| 683 | tusb_dma->controller.channel_release = tusb_omap_dma_release; |
| 684 | tusb_dma->controller.channel_program = tusb_omap_dma_program; |
| 685 | tusb_dma->controller.channel_abort = tusb_omap_dma_abort; |
| 686 | |
Matwey V. Kornilov | 7751b6f | 2014-05-16 18:20:52 +0400 | [diff] [blame] | 687 | if (musb->tusb_revision >= TUSB_REV_30) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 688 | tusb_dma->multichannel = 1; |
| 689 | |
| 690 | for (i = 0; i < MAX_DMAREQ; i++) { |
| 691 | struct dma_channel *ch; |
| 692 | struct tusb_omap_dma_ch *chdat; |
| 693 | |
| 694 | ch = kzalloc(sizeof(struct dma_channel), GFP_KERNEL); |
| 695 | if (!ch) |
| 696 | goto cleanup; |
| 697 | |
| 698 | dma_channel_pool[i] = ch; |
| 699 | |
| 700 | chdat = kzalloc(sizeof(struct tusb_omap_dma_ch), GFP_KERNEL); |
| 701 | if (!chdat) |
| 702 | goto cleanup; |
| 703 | |
| 704 | ch->status = MUSB_DMA_STATUS_UNKNOWN; |
| 705 | ch->private_data = chdat; |
| 706 | } |
| 707 | |
| 708 | return &tusb_dma->controller; |
| 709 | |
| 710 | cleanup: |
Tony Lindgren | 7f6283e | 2015-05-01 12:29:28 -0700 | [diff] [blame] | 711 | musb_dma_controller_destroy(&tusb_dma->controller); |
Huzaifa Sidhpurwala | c88ba39 | 2011-03-01 15:54:22 +0530 | [diff] [blame] | 712 | out: |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 713 | return NULL; |
| 714 | } |
Tony Lindgren | 7f6283e | 2015-05-01 12:29:28 -0700 | [diff] [blame] | 715 | EXPORT_SYMBOL_GPL(tusb_dma_controller_create); |