Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1 | /* |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 2 | * Copyright 2011 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
Ben Skeggs | 51beb42 | 2011-07-05 10:33:08 +1000 | [diff] [blame] | 25 | #include <linux/dma-mapping.h> |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 26 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 27 | #include <drm/drmP.h> |
| 28 | #include <drm/drm_crtc_helper.h> |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 29 | |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 30 | #include "nouveau_drm.h" |
| 31 | #include "nouveau_dma.h" |
| 32 | #include "nouveau_gem.h" |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 33 | #include "nouveau_connector.h" |
| 34 | #include "nouveau_encoder.h" |
| 35 | #include "nouveau_crtc.h" |
Ben Skeggs | f589be8 | 2012-07-22 11:55:54 +1000 | [diff] [blame] | 36 | #include "nouveau_fence.h" |
Ben Skeggs | 3a89cd0 | 2011-07-07 10:47:10 +1000 | [diff] [blame] | 37 | #include "nv50_display.h" |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 38 | |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 39 | #include <core/client.h> |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 40 | #include <core/gpuobj.h> |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 41 | #include <core/class.h> |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 42 | |
| 43 | #include <subdev/timer.h> |
| 44 | #include <subdev/bar.h> |
| 45 | #include <subdev/fb.h> |
Ben Skeggs | 5ed5020 | 2013-02-11 20:15:03 +1000 | [diff] [blame] | 46 | #include <subdev/i2c.h> |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 47 | |
Ben Skeggs | 8a46438 | 2011-11-12 23:52:07 +1000 | [diff] [blame] | 48 | #define EVO_DMA_NR 9 |
| 49 | |
Ben Skeggs | bdb8c21 | 2011-11-12 01:30:24 +1000 | [diff] [blame] | 50 | #define EVO_MASTER (0x00) |
Ben Skeggs | a63a97e | 2011-11-16 15:22:34 +1000 | [diff] [blame] | 51 | #define EVO_FLIP(c) (0x01 + (c)) |
Ben Skeggs | 8a46438 | 2011-11-12 23:52:07 +1000 | [diff] [blame] | 52 | #define EVO_OVLY(c) (0x05 + (c)) |
| 53 | #define EVO_OIMM(c) (0x09 + (c)) |
Ben Skeggs | bdb8c21 | 2011-11-12 01:30:24 +1000 | [diff] [blame] | 54 | #define EVO_CURS(c) (0x0d + (c)) |
| 55 | |
Ben Skeggs | 816af2f | 2011-11-16 15:48:48 +1000 | [diff] [blame] | 56 | /* offsets in shared sync bo of various structures */ |
| 57 | #define EVO_SYNC(c, o) ((c) * 0x0100 + (o)) |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 58 | #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00) |
| 59 | #define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00) |
| 60 | #define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10) |
Ben Skeggs | 816af2f | 2011-11-16 15:48:48 +1000 | [diff] [blame] | 61 | |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 62 | #define EVO_CORE_HANDLE (0xd1500000) |
| 63 | #define EVO_CHAN_HANDLE(t,i) (0xd15c0000 | (((t) & 0x00ff) << 8) | (i)) |
| 64 | #define EVO_CHAN_OCLASS(t,c) ((nv_hclass(c) & 0xff00) | ((t) & 0x00ff)) |
| 65 | #define EVO_PUSH_HANDLE(t,i) (0xd15b0000 | (i) | \ |
| 66 | (((NV50_DISP_##t##_CLASS) & 0x00ff) << 8)) |
| 67 | |
| 68 | /****************************************************************************** |
| 69 | * EVO channel |
| 70 | *****************************************************************************/ |
| 71 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 72 | struct nv50_chan { |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 73 | struct nouveau_object *user; |
| 74 | u32 handle; |
| 75 | }; |
| 76 | |
| 77 | static int |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 78 | nv50_chan_create(struct nouveau_object *core, u32 bclass, u8 head, |
| 79 | void *data, u32 size, struct nv50_chan *chan) |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 80 | { |
| 81 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); |
| 82 | const u32 oclass = EVO_CHAN_OCLASS(bclass, core); |
| 83 | const u32 handle = EVO_CHAN_HANDLE(bclass, head); |
| 84 | int ret; |
| 85 | |
| 86 | ret = nouveau_object_new(client, EVO_CORE_HANDLE, handle, |
| 87 | oclass, data, size, &chan->user); |
| 88 | if (ret) |
| 89 | return ret; |
| 90 | |
| 91 | chan->handle = handle; |
| 92 | return 0; |
| 93 | } |
| 94 | |
| 95 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 96 | nv50_chan_destroy(struct nouveau_object *core, struct nv50_chan *chan) |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 97 | { |
| 98 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); |
| 99 | if (chan->handle) |
| 100 | nouveau_object_del(client, EVO_CORE_HANDLE, chan->handle); |
| 101 | } |
| 102 | |
| 103 | /****************************************************************************** |
| 104 | * PIO EVO channel |
| 105 | *****************************************************************************/ |
| 106 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 107 | struct nv50_pioc { |
| 108 | struct nv50_chan base; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 109 | }; |
| 110 | |
| 111 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 112 | nv50_pioc_destroy(struct nouveau_object *core, struct nv50_pioc *pioc) |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 113 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 114 | nv50_chan_destroy(core, &pioc->base); |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 115 | } |
| 116 | |
| 117 | static int |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 118 | nv50_pioc_create(struct nouveau_object *core, u32 bclass, u8 head, |
| 119 | void *data, u32 size, struct nv50_pioc *pioc) |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 120 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 121 | return nv50_chan_create(core, bclass, head, data, size, &pioc->base); |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 122 | } |
| 123 | |
| 124 | /****************************************************************************** |
| 125 | * DMA EVO channel |
| 126 | *****************************************************************************/ |
| 127 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 128 | struct nv50_dmac { |
| 129 | struct nv50_chan base; |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 130 | dma_addr_t handle; |
| 131 | u32 *ptr; |
Daniel Vetter | 59ad146 | 2012-12-02 14:49:44 +0100 | [diff] [blame] | 132 | |
| 133 | /* Protects against concurrent pushbuf access to this channel, lock is |
| 134 | * grabbed by evo_wait (if the pushbuf reservation is successful) and |
| 135 | * dropped again by evo_kick. */ |
| 136 | struct mutex lock; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 137 | }; |
| 138 | |
| 139 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 140 | nv50_dmac_destroy(struct nouveau_object *core, struct nv50_dmac *dmac) |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 141 | { |
| 142 | if (dmac->ptr) { |
| 143 | struct pci_dev *pdev = nv_device(core)->pdev; |
| 144 | pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle); |
| 145 | } |
| 146 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 147 | nv50_chan_destroy(core, &dmac->base); |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 148 | } |
| 149 | |
| 150 | static int |
Ben Skeggs | 4705730 | 2012-11-16 13:58:48 +1000 | [diff] [blame] | 151 | nv50_dmac_create_fbdma(struct nouveau_object *core, u32 parent) |
| 152 | { |
| 153 | struct nouveau_fb *pfb = nouveau_fb(core); |
| 154 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); |
| 155 | struct nouveau_object *object; |
| 156 | int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP, |
| 157 | NV_DMA_IN_MEMORY_CLASS, |
| 158 | &(struct nv_dma_class) { |
| 159 | .flags = NV_DMA_TARGET_VRAM | |
| 160 | NV_DMA_ACCESS_RDWR, |
| 161 | .start = 0, |
Ben Skeggs | dceef5d | 2013-03-04 13:01:21 +1000 | [diff] [blame] | 162 | .limit = pfb->ram->size - 1, |
Ben Skeggs | 4705730 | 2012-11-16 13:58:48 +1000 | [diff] [blame] | 163 | .conf0 = NV50_DMA_CONF0_ENABLE | |
| 164 | NV50_DMA_CONF0_PART_256, |
| 165 | }, sizeof(struct nv_dma_class), &object); |
| 166 | if (ret) |
| 167 | return ret; |
| 168 | |
| 169 | ret = nouveau_object_new(client, parent, NvEvoFB16, |
| 170 | NV_DMA_IN_MEMORY_CLASS, |
| 171 | &(struct nv_dma_class) { |
| 172 | .flags = NV_DMA_TARGET_VRAM | |
| 173 | NV_DMA_ACCESS_RDWR, |
| 174 | .start = 0, |
Ben Skeggs | dceef5d | 2013-03-04 13:01:21 +1000 | [diff] [blame] | 175 | .limit = pfb->ram->size - 1, |
Ben Skeggs | 4705730 | 2012-11-16 13:58:48 +1000 | [diff] [blame] | 176 | .conf0 = NV50_DMA_CONF0_ENABLE | 0x70 | |
| 177 | NV50_DMA_CONF0_PART_256, |
| 178 | }, sizeof(struct nv_dma_class), &object); |
| 179 | if (ret) |
| 180 | return ret; |
| 181 | |
| 182 | ret = nouveau_object_new(client, parent, NvEvoFB32, |
| 183 | NV_DMA_IN_MEMORY_CLASS, |
| 184 | &(struct nv_dma_class) { |
| 185 | .flags = NV_DMA_TARGET_VRAM | |
| 186 | NV_DMA_ACCESS_RDWR, |
| 187 | .start = 0, |
Ben Skeggs | dceef5d | 2013-03-04 13:01:21 +1000 | [diff] [blame] | 188 | .limit = pfb->ram->size - 1, |
Ben Skeggs | 4705730 | 2012-11-16 13:58:48 +1000 | [diff] [blame] | 189 | .conf0 = NV50_DMA_CONF0_ENABLE | 0x7a | |
| 190 | NV50_DMA_CONF0_PART_256, |
| 191 | }, sizeof(struct nv_dma_class), &object); |
| 192 | return ret; |
| 193 | } |
| 194 | |
| 195 | static int |
| 196 | nvc0_dmac_create_fbdma(struct nouveau_object *core, u32 parent) |
| 197 | { |
| 198 | struct nouveau_fb *pfb = nouveau_fb(core); |
| 199 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); |
| 200 | struct nouveau_object *object; |
| 201 | int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP, |
| 202 | NV_DMA_IN_MEMORY_CLASS, |
| 203 | &(struct nv_dma_class) { |
| 204 | .flags = NV_DMA_TARGET_VRAM | |
| 205 | NV_DMA_ACCESS_RDWR, |
| 206 | .start = 0, |
Ben Skeggs | dceef5d | 2013-03-04 13:01:21 +1000 | [diff] [blame] | 207 | .limit = pfb->ram->size - 1, |
Ben Skeggs | 4705730 | 2012-11-16 13:58:48 +1000 | [diff] [blame] | 208 | .conf0 = NVC0_DMA_CONF0_ENABLE, |
| 209 | }, sizeof(struct nv_dma_class), &object); |
| 210 | if (ret) |
| 211 | return ret; |
| 212 | |
| 213 | ret = nouveau_object_new(client, parent, NvEvoFB16, |
| 214 | NV_DMA_IN_MEMORY_CLASS, |
| 215 | &(struct nv_dma_class) { |
| 216 | .flags = NV_DMA_TARGET_VRAM | |
| 217 | NV_DMA_ACCESS_RDWR, |
| 218 | .start = 0, |
Ben Skeggs | dceef5d | 2013-03-04 13:01:21 +1000 | [diff] [blame] | 219 | .limit = pfb->ram->size - 1, |
Ben Skeggs | 4705730 | 2012-11-16 13:58:48 +1000 | [diff] [blame] | 220 | .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe, |
| 221 | }, sizeof(struct nv_dma_class), &object); |
| 222 | if (ret) |
| 223 | return ret; |
| 224 | |
| 225 | ret = nouveau_object_new(client, parent, NvEvoFB32, |
| 226 | NV_DMA_IN_MEMORY_CLASS, |
| 227 | &(struct nv_dma_class) { |
| 228 | .flags = NV_DMA_TARGET_VRAM | |
| 229 | NV_DMA_ACCESS_RDWR, |
| 230 | .start = 0, |
Ben Skeggs | dceef5d | 2013-03-04 13:01:21 +1000 | [diff] [blame] | 231 | .limit = pfb->ram->size - 1, |
Ben Skeggs | 4705730 | 2012-11-16 13:58:48 +1000 | [diff] [blame] | 232 | .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe, |
| 233 | }, sizeof(struct nv_dma_class), &object); |
| 234 | return ret; |
| 235 | } |
| 236 | |
| 237 | static int |
| 238 | nvd0_dmac_create_fbdma(struct nouveau_object *core, u32 parent) |
| 239 | { |
| 240 | struct nouveau_fb *pfb = nouveau_fb(core); |
| 241 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); |
| 242 | struct nouveau_object *object; |
| 243 | int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP, |
| 244 | NV_DMA_IN_MEMORY_CLASS, |
| 245 | &(struct nv_dma_class) { |
| 246 | .flags = NV_DMA_TARGET_VRAM | |
| 247 | NV_DMA_ACCESS_RDWR, |
| 248 | .start = 0, |
Ben Skeggs | dceef5d | 2013-03-04 13:01:21 +1000 | [diff] [blame] | 249 | .limit = pfb->ram->size - 1, |
Ben Skeggs | 4705730 | 2012-11-16 13:58:48 +1000 | [diff] [blame] | 250 | .conf0 = NVD0_DMA_CONF0_ENABLE | |
| 251 | NVD0_DMA_CONF0_PAGE_LP, |
| 252 | }, sizeof(struct nv_dma_class), &object); |
| 253 | if (ret) |
| 254 | return ret; |
| 255 | |
| 256 | ret = nouveau_object_new(client, parent, NvEvoFB32, |
| 257 | NV_DMA_IN_MEMORY_CLASS, |
| 258 | &(struct nv_dma_class) { |
| 259 | .flags = NV_DMA_TARGET_VRAM | |
| 260 | NV_DMA_ACCESS_RDWR, |
| 261 | .start = 0, |
Ben Skeggs | dceef5d | 2013-03-04 13:01:21 +1000 | [diff] [blame] | 262 | .limit = pfb->ram->size - 1, |
Ben Skeggs | 4705730 | 2012-11-16 13:58:48 +1000 | [diff] [blame] | 263 | .conf0 = NVD0_DMA_CONF0_ENABLE | 0xfe | |
| 264 | NVD0_DMA_CONF0_PAGE_LP, |
| 265 | }, sizeof(struct nv_dma_class), &object); |
| 266 | return ret; |
| 267 | } |
| 268 | |
| 269 | static int |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 270 | nv50_dmac_create(struct nouveau_object *core, u32 bclass, u8 head, |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 271 | void *data, u32 size, u64 syncbuf, |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 272 | struct nv50_dmac *dmac) |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 273 | { |
| 274 | struct nouveau_fb *pfb = nouveau_fb(core); |
| 275 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); |
| 276 | struct nouveau_object *object; |
| 277 | u32 pushbuf = *(u32 *)data; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 278 | int ret; |
| 279 | |
Daniel Vetter | 59ad146 | 2012-12-02 14:49:44 +0100 | [diff] [blame] | 280 | mutex_init(&dmac->lock); |
| 281 | |
Ben Skeggs | 4705730 | 2012-11-16 13:58:48 +1000 | [diff] [blame] | 282 | dmac->ptr = pci_alloc_consistent(nv_device(core)->pdev, PAGE_SIZE, |
| 283 | &dmac->handle); |
| 284 | if (!dmac->ptr) |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 285 | return -ENOMEM; |
| 286 | |
| 287 | ret = nouveau_object_new(client, NVDRM_DEVICE, pushbuf, |
| 288 | NV_DMA_FROM_MEMORY_CLASS, |
| 289 | &(struct nv_dma_class) { |
| 290 | .flags = NV_DMA_TARGET_PCI_US | |
| 291 | NV_DMA_ACCESS_RD, |
Ben Skeggs | 4705730 | 2012-11-16 13:58:48 +1000 | [diff] [blame] | 292 | .start = dmac->handle + 0x0000, |
| 293 | .limit = dmac->handle + 0x0fff, |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 294 | }, sizeof(struct nv_dma_class), &object); |
| 295 | if (ret) |
| 296 | return ret; |
| 297 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 298 | ret = nv50_chan_create(core, bclass, head, data, size, &dmac->base); |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 299 | if (ret) |
| 300 | return ret; |
| 301 | |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 302 | ret = nouveau_object_new(client, dmac->base.handle, NvEvoSync, |
| 303 | NV_DMA_IN_MEMORY_CLASS, |
| 304 | &(struct nv_dma_class) { |
| 305 | .flags = NV_DMA_TARGET_VRAM | |
| 306 | NV_DMA_ACCESS_RDWR, |
| 307 | .start = syncbuf + 0x0000, |
| 308 | .limit = syncbuf + 0x0fff, |
| 309 | }, sizeof(struct nv_dma_class), &object); |
| 310 | if (ret) |
Ben Skeggs | 4705730 | 2012-11-16 13:58:48 +1000 | [diff] [blame] | 311 | return ret; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 312 | |
| 313 | ret = nouveau_object_new(client, dmac->base.handle, NvEvoVRAM, |
| 314 | NV_DMA_IN_MEMORY_CLASS, |
| 315 | &(struct nv_dma_class) { |
| 316 | .flags = NV_DMA_TARGET_VRAM | |
| 317 | NV_DMA_ACCESS_RDWR, |
| 318 | .start = 0, |
Ben Skeggs | dceef5d | 2013-03-04 13:01:21 +1000 | [diff] [blame] | 319 | .limit = pfb->ram->size - 1, |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 320 | }, sizeof(struct nv_dma_class), &object); |
| 321 | if (ret) |
Ben Skeggs | 4705730 | 2012-11-16 13:58:48 +1000 | [diff] [blame] | 322 | return ret; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 323 | |
Ben Skeggs | 4705730 | 2012-11-16 13:58:48 +1000 | [diff] [blame] | 324 | if (nv_device(core)->card_type < NV_C0) |
| 325 | ret = nv50_dmac_create_fbdma(core, dmac->base.handle); |
| 326 | else |
| 327 | if (nv_device(core)->card_type < NV_D0) |
| 328 | ret = nvc0_dmac_create_fbdma(core, dmac->base.handle); |
| 329 | else |
| 330 | ret = nvd0_dmac_create_fbdma(core, dmac->base.handle); |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 331 | return ret; |
| 332 | } |
| 333 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 334 | struct nv50_mast { |
| 335 | struct nv50_dmac base; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 336 | }; |
| 337 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 338 | struct nv50_curs { |
| 339 | struct nv50_pioc base; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 340 | }; |
| 341 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 342 | struct nv50_sync { |
| 343 | struct nv50_dmac base; |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 344 | u32 addr; |
| 345 | u32 data; |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 346 | }; |
| 347 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 348 | struct nv50_ovly { |
| 349 | struct nv50_dmac base; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 350 | }; |
Ben Skeggs | f20ce96 | 2011-07-08 13:17:01 +1000 | [diff] [blame] | 351 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 352 | struct nv50_oimm { |
| 353 | struct nv50_pioc base; |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 354 | }; |
| 355 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 356 | struct nv50_head { |
Ben Skeggs | dd0e3d5 | 2012-10-16 14:00:31 +1000 | [diff] [blame] | 357 | struct nouveau_crtc base; |
Ben Skeggs | 8dda53f | 2013-07-09 12:35:55 +1000 | [diff] [blame] | 358 | struct nouveau_bo *image; |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 359 | struct nv50_curs curs; |
| 360 | struct nv50_sync sync; |
| 361 | struct nv50_ovly ovly; |
| 362 | struct nv50_oimm oimm; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 363 | }; |
| 364 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 365 | #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c)) |
| 366 | #define nv50_curs(c) (&nv50_head(c)->curs) |
| 367 | #define nv50_sync(c) (&nv50_head(c)->sync) |
| 368 | #define nv50_ovly(c) (&nv50_head(c)->ovly) |
| 369 | #define nv50_oimm(c) (&nv50_head(c)->oimm) |
| 370 | #define nv50_chan(c) (&(c)->base.base) |
| 371 | #define nv50_vers(c) nv_mclass(nv50_chan(c)->user) |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 372 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 373 | struct nv50_disp { |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 374 | struct nouveau_object *core; |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 375 | struct nv50_mast mast; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 376 | |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 377 | u32 modeset; |
| 378 | |
| 379 | struct nouveau_bo *sync; |
Ben Skeggs | dd0e3d5 | 2012-10-16 14:00:31 +1000 | [diff] [blame] | 380 | }; |
| 381 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 382 | static struct nv50_disp * |
| 383 | nv50_disp(struct drm_device *dev) |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 384 | { |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 385 | return nouveau_display(dev)->priv; |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 386 | } |
| 387 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 388 | #define nv50_mast(d) (&nv50_disp(d)->mast) |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 389 | |
Ben Skeggs | bdb8c21 | 2011-11-12 01:30:24 +1000 | [diff] [blame] | 390 | static struct drm_crtc * |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 391 | nv50_display_crtc_get(struct drm_encoder *encoder) |
Ben Skeggs | bdb8c21 | 2011-11-12 01:30:24 +1000 | [diff] [blame] | 392 | { |
| 393 | return nouveau_encoder(encoder)->crtc; |
| 394 | } |
| 395 | |
| 396 | /****************************************************************************** |
| 397 | * EVO channel helpers |
| 398 | *****************************************************************************/ |
Ben Skeggs | 51beb42 | 2011-07-05 10:33:08 +1000 | [diff] [blame] | 399 | static u32 * |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 400 | evo_wait(void *evoc, int nr) |
Ben Skeggs | 51beb42 | 2011-07-05 10:33:08 +1000 | [diff] [blame] | 401 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 402 | struct nv50_dmac *dmac = evoc; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 403 | u32 put = nv_ro32(dmac->base.user, 0x0000) / 4; |
Ben Skeggs | 51beb42 | 2011-07-05 10:33:08 +1000 | [diff] [blame] | 404 | |
Daniel Vetter | 59ad146 | 2012-12-02 14:49:44 +0100 | [diff] [blame] | 405 | mutex_lock(&dmac->lock); |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 406 | if (put + nr >= (PAGE_SIZE / 4) - 8) { |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 407 | dmac->ptr[put] = 0x20000000; |
Ben Skeggs | 51beb42 | 2011-07-05 10:33:08 +1000 | [diff] [blame] | 408 | |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 409 | nv_wo32(dmac->base.user, 0x0000, 0x00000000); |
| 410 | if (!nv_wait(dmac->base.user, 0x0004, ~0, 0x00000000)) { |
Daniel Vetter | 59ad146 | 2012-12-02 14:49:44 +0100 | [diff] [blame] | 411 | mutex_unlock(&dmac->lock); |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 412 | NV_ERROR(dmac->base.user, "channel stalled\n"); |
Ben Skeggs | 51beb42 | 2011-07-05 10:33:08 +1000 | [diff] [blame] | 413 | return NULL; |
| 414 | } |
| 415 | |
| 416 | put = 0; |
| 417 | } |
| 418 | |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 419 | return dmac->ptr + put; |
Ben Skeggs | 51beb42 | 2011-07-05 10:33:08 +1000 | [diff] [blame] | 420 | } |
| 421 | |
| 422 | static void |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 423 | evo_kick(u32 *push, void *evoc) |
Ben Skeggs | 51beb42 | 2011-07-05 10:33:08 +1000 | [diff] [blame] | 424 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 425 | struct nv50_dmac *dmac = evoc; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 426 | nv_wo32(dmac->base.user, 0x0000, (push - dmac->ptr) << 2); |
Daniel Vetter | 59ad146 | 2012-12-02 14:49:44 +0100 | [diff] [blame] | 427 | mutex_unlock(&dmac->lock); |
Ben Skeggs | 51beb42 | 2011-07-05 10:33:08 +1000 | [diff] [blame] | 428 | } |
| 429 | |
| 430 | #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m)) |
| 431 | #define evo_data(p,d) *((p)++) = (d) |
| 432 | |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 433 | static bool |
| 434 | evo_sync_wait(void *data) |
| 435 | { |
Ben Skeggs | 5cc027f | 2013-02-18 17:50:51 -0500 | [diff] [blame] | 436 | if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000) |
| 437 | return true; |
| 438 | usleep_range(1, 2); |
| 439 | return false; |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 440 | } |
| 441 | |
| 442 | static int |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 443 | evo_sync(struct drm_device *dev) |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 444 | { |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 445 | struct nouveau_device *device = nouveau_dev(dev); |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 446 | struct nv50_disp *disp = nv50_disp(dev); |
| 447 | struct nv50_mast *mast = nv50_mast(dev); |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 448 | u32 *push = evo_wait(mast, 8); |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 449 | if (push) { |
Ben Skeggs | 816af2f | 2011-11-16 15:48:48 +1000 | [diff] [blame] | 450 | nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000); |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 451 | evo_mthd(push, 0x0084, 1); |
Ben Skeggs | 816af2f | 2011-11-16 15:48:48 +1000 | [diff] [blame] | 452 | evo_data(push, 0x80000000 | EVO_MAST_NTFY); |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 453 | evo_mthd(push, 0x0080, 2); |
| 454 | evo_data(push, 0x00000000); |
| 455 | evo_data(push, 0x00000000); |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 456 | evo_kick(push, mast); |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 457 | if (nv_wait_cb(device, evo_sync_wait, disp->sync)) |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 458 | return 0; |
| 459 | } |
| 460 | |
| 461 | return -EBUSY; |
| 462 | } |
| 463 | |
| 464 | /****************************************************************************** |
Ben Skeggs | a63a97e | 2011-11-16 15:22:34 +1000 | [diff] [blame] | 465 | * Page flipping channel |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 466 | *****************************************************************************/ |
| 467 | struct nouveau_bo * |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 468 | nv50_display_crtc_sema(struct drm_device *dev, int crtc) |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 469 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 470 | return nv50_disp(dev)->sync; |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 471 | } |
| 472 | |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 473 | struct nv50_display_flip { |
| 474 | struct nv50_disp *disp; |
| 475 | struct nv50_sync *chan; |
| 476 | }; |
| 477 | |
| 478 | static bool |
| 479 | nv50_display_flip_wait(void *data) |
| 480 | { |
| 481 | struct nv50_display_flip *flip = data; |
| 482 | if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) == |
Calvin Owens | b1ea3e6 | 2013-04-07 21:01:19 -0500 | [diff] [blame] | 483 | flip->chan->data) |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 484 | return true; |
| 485 | usleep_range(1, 2); |
| 486 | return false; |
| 487 | } |
| 488 | |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 489 | void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 490 | nv50_display_flip_stop(struct drm_crtc *crtc) |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 491 | { |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 492 | struct nouveau_device *device = nouveau_dev(crtc->dev); |
| 493 | struct nv50_display_flip flip = { |
| 494 | .disp = nv50_disp(crtc->dev), |
| 495 | .chan = nv50_sync(crtc), |
| 496 | }; |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 497 | u32 *push; |
| 498 | |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 499 | push = evo_wait(flip.chan, 8); |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 500 | if (push) { |
| 501 | evo_mthd(push, 0x0084, 1); |
| 502 | evo_data(push, 0x00000000); |
| 503 | evo_mthd(push, 0x0094, 1); |
| 504 | evo_data(push, 0x00000000); |
| 505 | evo_mthd(push, 0x00c0, 1); |
| 506 | evo_data(push, 0x00000000); |
| 507 | evo_mthd(push, 0x0080, 1); |
| 508 | evo_data(push, 0x00000000); |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 509 | evo_kick(push, flip.chan); |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 510 | } |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 511 | |
| 512 | nv_wait_cb(device, nv50_display_flip_wait, &flip); |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 513 | } |
| 514 | |
| 515 | int |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 516 | nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 517 | struct nouveau_channel *chan, u32 swap_interval) |
| 518 | { |
| 519 | struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 520 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
Ben Skeggs | 8dda53f | 2013-07-09 12:35:55 +1000 | [diff] [blame] | 521 | struct nv50_head *head = nv50_head(crtc); |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 522 | struct nv50_sync *sync = nv50_sync(crtc); |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 523 | u32 *push; |
Ben Skeggs | 8dda53f | 2013-07-09 12:35:55 +1000 | [diff] [blame] | 524 | int ret; |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 525 | |
| 526 | swap_interval <<= 4; |
| 527 | if (swap_interval == 0) |
| 528 | swap_interval |= 0x100; |
Ben Skeggs | f60b6e7 | 2013-03-19 15:20:00 +1000 | [diff] [blame] | 529 | if (chan == NULL) |
| 530 | evo_sync(crtc->dev); |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 531 | |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 532 | push = evo_wait(sync, 128); |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 533 | if (unlikely(push == NULL)) |
| 534 | return -EBUSY; |
| 535 | |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 536 | if (chan && nv_mclass(chan->object) < NV84_CHANNEL_IND_CLASS) { |
| 537 | ret = RING_SPACE(chan, 8); |
| 538 | if (ret) |
| 539 | return ret; |
Ben Skeggs | 67f9718 | 2013-02-26 12:02:54 +1000 | [diff] [blame] | 540 | |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 541 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2); |
Ben Skeggs | 8dda53f | 2013-07-09 12:35:55 +1000 | [diff] [blame] | 542 | OUT_RING (chan, NvEvoSema0 + nv_crtc->index); |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 543 | OUT_RING (chan, sync->addr ^ 0x10); |
| 544 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1); |
| 545 | OUT_RING (chan, sync->data + 1); |
| 546 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2); |
| 547 | OUT_RING (chan, sync->addr); |
| 548 | OUT_RING (chan, sync->data); |
| 549 | } else |
| 550 | if (chan && nv_mclass(chan->object) < NVC0_CHANNEL_IND_CLASS) { |
Ben Skeggs | 8dda53f | 2013-07-09 12:35:55 +1000 | [diff] [blame] | 551 | u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr; |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 552 | ret = RING_SPACE(chan, 12); |
| 553 | if (ret) |
| 554 | return ret; |
Ben Skeggs | a34caf7 | 2013-02-14 09:28:37 +1000 | [diff] [blame] | 555 | |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 556 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); |
| 557 | OUT_RING (chan, chan->vram); |
| 558 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); |
| 559 | OUT_RING (chan, upper_32_bits(addr ^ 0x10)); |
| 560 | OUT_RING (chan, lower_32_bits(addr ^ 0x10)); |
| 561 | OUT_RING (chan, sync->data + 1); |
| 562 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); |
| 563 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); |
| 564 | OUT_RING (chan, upper_32_bits(addr)); |
| 565 | OUT_RING (chan, lower_32_bits(addr)); |
| 566 | OUT_RING (chan, sync->data); |
| 567 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL); |
| 568 | } else |
| 569 | if (chan) { |
Ben Skeggs | 8dda53f | 2013-07-09 12:35:55 +1000 | [diff] [blame] | 570 | u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr; |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 571 | ret = RING_SPACE(chan, 10); |
| 572 | if (ret) |
| 573 | return ret; |
Ben Skeggs | 67f9718 | 2013-02-26 12:02:54 +1000 | [diff] [blame] | 574 | |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 575 | BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); |
| 576 | OUT_RING (chan, upper_32_bits(addr ^ 0x10)); |
| 577 | OUT_RING (chan, lower_32_bits(addr ^ 0x10)); |
| 578 | OUT_RING (chan, sync->data + 1); |
| 579 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG | |
| 580 | NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD); |
| 581 | BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); |
| 582 | OUT_RING (chan, upper_32_bits(addr)); |
| 583 | OUT_RING (chan, lower_32_bits(addr)); |
| 584 | OUT_RING (chan, sync->data); |
| 585 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL | |
| 586 | NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD); |
| 587 | } |
Ben Skeggs | 35bcf5d | 2012-04-30 11:34:10 -0500 | [diff] [blame] | 588 | |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 589 | if (chan) { |
| 590 | sync->addr ^= 0x10; |
| 591 | sync->data++; |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 592 | FIRE_RING (chan); |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 593 | } |
| 594 | |
| 595 | /* queue the flip */ |
| 596 | evo_mthd(push, 0x0100, 1); |
| 597 | evo_data(push, 0xfffe0000); |
| 598 | evo_mthd(push, 0x0084, 1); |
| 599 | evo_data(push, swap_interval); |
| 600 | if (!(swap_interval & 0x00000100)) { |
| 601 | evo_mthd(push, 0x00e0, 1); |
| 602 | evo_data(push, 0x40000000); |
| 603 | } |
| 604 | evo_mthd(push, 0x0088, 4); |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 605 | evo_data(push, sync->addr); |
| 606 | evo_data(push, sync->data++); |
| 607 | evo_data(push, sync->data); |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 608 | evo_data(push, NvEvoSync); |
| 609 | evo_mthd(push, 0x00a0, 2); |
| 610 | evo_data(push, 0x00000000); |
| 611 | evo_data(push, 0x00000000); |
| 612 | evo_mthd(push, 0x00c0, 1); |
| 613 | evo_data(push, nv_fb->r_dma); |
| 614 | evo_mthd(push, 0x0110, 2); |
| 615 | evo_data(push, 0x00000000); |
| 616 | evo_data(push, 0x00000000); |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 617 | if (nv50_vers(sync) < NVD0_DISP_SYNC_CLASS) { |
Ben Skeggs | ed5085a5 | 2012-11-16 13:16:51 +1000 | [diff] [blame] | 618 | evo_mthd(push, 0x0800, 5); |
| 619 | evo_data(push, nv_fb->nvbo->bo.offset >> 8); |
| 620 | evo_data(push, 0); |
| 621 | evo_data(push, (fb->height << 16) | fb->width); |
| 622 | evo_data(push, nv_fb->r_pitch); |
| 623 | evo_data(push, nv_fb->r_format); |
| 624 | } else { |
| 625 | evo_mthd(push, 0x0400, 5); |
| 626 | evo_data(push, nv_fb->nvbo->bo.offset >> 8); |
| 627 | evo_data(push, 0); |
| 628 | evo_data(push, (fb->height << 16) | fb->width); |
| 629 | evo_data(push, nv_fb->r_pitch); |
| 630 | evo_data(push, nv_fb->r_format); |
| 631 | } |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 632 | evo_mthd(push, 0x0080, 1); |
| 633 | evo_data(push, 0x00000000); |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 634 | evo_kick(push, sync); |
Ben Skeggs | 8dda53f | 2013-07-09 12:35:55 +1000 | [diff] [blame] | 635 | |
| 636 | nouveau_bo_ref(nv_fb->nvbo, &head->image); |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 637 | return 0; |
| 638 | } |
| 639 | |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 640 | /****************************************************************************** |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 641 | * CRTC |
| 642 | *****************************************************************************/ |
| 643 | static int |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 644 | nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update) |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 645 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 646 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
Ben Skeggs | de69185 | 2011-10-17 12:23:41 +1000 | [diff] [blame] | 647 | struct nouveau_connector *nv_connector; |
| 648 | struct drm_connector *connector; |
| 649 | u32 *push, mode = 0x00; |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 650 | |
Ben Skeggs | 488ff20 | 2011-10-17 10:38:10 +1000 | [diff] [blame] | 651 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
Ben Skeggs | de69185 | 2011-10-17 12:23:41 +1000 | [diff] [blame] | 652 | connector = &nv_connector->base; |
| 653 | if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) { |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 654 | if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3) |
Ben Skeggs | de69185 | 2011-10-17 12:23:41 +1000 | [diff] [blame] | 655 | mode = DITHERING_MODE_DYNAMIC2X2; |
| 656 | } else { |
| 657 | mode = nv_connector->dithering_mode; |
| 658 | } |
| 659 | |
| 660 | if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) { |
| 661 | if (connector->display_info.bpc >= 8) |
| 662 | mode |= DITHERING_DEPTH_8BPC; |
| 663 | } else { |
| 664 | mode |= nv_connector->dithering_depth; |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 665 | } |
| 666 | |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 667 | push = evo_wait(mast, 4); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 668 | if (push) { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 669 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 670 | evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1); |
| 671 | evo_data(push, mode); |
| 672 | } else |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 673 | if (nv50_vers(mast) < NVE0_DISP_MAST_CLASS) { |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 674 | evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1); |
| 675 | evo_data(push, mode); |
| 676 | } else { |
| 677 | evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1); |
| 678 | evo_data(push, mode); |
| 679 | } |
| 680 | |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 681 | if (update) { |
| 682 | evo_mthd(push, 0x0080, 1); |
| 683 | evo_data(push, 0x00000000); |
| 684 | } |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 685 | evo_kick(push, mast); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 686 | } |
| 687 | |
| 688 | return 0; |
| 689 | } |
| 690 | |
| 691 | static int |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 692 | nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update) |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 693 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 694 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
Ben Skeggs | 9285462 | 2011-11-11 23:49:06 +1000 | [diff] [blame] | 695 | struct drm_display_mode *omode, *umode = &nv_crtc->base.mode; |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 696 | struct drm_crtc *crtc = &nv_crtc->base; |
Ben Skeggs | f3fdc52 | 2011-07-07 16:01:57 +1000 | [diff] [blame] | 697 | struct nouveau_connector *nv_connector; |
Ben Skeggs | 9285462 | 2011-11-11 23:49:06 +1000 | [diff] [blame] | 698 | int mode = DRM_MODE_SCALE_NONE; |
| 699 | u32 oX, oY, *push; |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 700 | |
Ben Skeggs | 9285462 | 2011-11-11 23:49:06 +1000 | [diff] [blame] | 701 | /* start off at the resolution we programmed the crtc for, this |
| 702 | * effectively handles NONE/FULL scaling |
| 703 | */ |
Ben Skeggs | f3fdc52 | 2011-07-07 16:01:57 +1000 | [diff] [blame] | 704 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
Ben Skeggs | 9285462 | 2011-11-11 23:49:06 +1000 | [diff] [blame] | 705 | if (nv_connector && nv_connector->native_mode) |
| 706 | mode = nv_connector->scaling_mode; |
Ben Skeggs | f3fdc52 | 2011-07-07 16:01:57 +1000 | [diff] [blame] | 707 | |
Ben Skeggs | 9285462 | 2011-11-11 23:49:06 +1000 | [diff] [blame] | 708 | if (mode != DRM_MODE_SCALE_NONE) |
| 709 | omode = nv_connector->native_mode; |
| 710 | else |
| 711 | omode = umode; |
| 712 | |
| 713 | oX = omode->hdisplay; |
| 714 | oY = omode->vdisplay; |
| 715 | if (omode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 716 | oY *= 2; |
| 717 | |
| 718 | /* add overscan compensation if necessary, will keep the aspect |
| 719 | * ratio the same as the backend mode unless overridden by the |
| 720 | * user setting both hborder and vborder properties. |
| 721 | */ |
| 722 | if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON || |
| 723 | (nv_connector->underscan == UNDERSCAN_AUTO && |
| 724 | nv_connector->edid && |
| 725 | drm_detect_hdmi_monitor(nv_connector->edid)))) { |
| 726 | u32 bX = nv_connector->underscan_hborder; |
| 727 | u32 bY = nv_connector->underscan_vborder; |
| 728 | u32 aspect = (oY << 19) / oX; |
| 729 | |
| 730 | if (bX) { |
| 731 | oX -= (bX * 2); |
| 732 | if (bY) oY -= (bY * 2); |
| 733 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; |
| 734 | } else { |
| 735 | oX -= (oX >> 4) + 32; |
| 736 | if (bY) oY -= (bY * 2); |
| 737 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; |
Ben Skeggs | f3fdc52 | 2011-07-07 16:01:57 +1000 | [diff] [blame] | 738 | } |
| 739 | } |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 740 | |
Ben Skeggs | 9285462 | 2011-11-11 23:49:06 +1000 | [diff] [blame] | 741 | /* handle CENTER/ASPECT scaling, taking into account the areas |
| 742 | * removed already for overscan compensation |
| 743 | */ |
| 744 | switch (mode) { |
| 745 | case DRM_MODE_SCALE_CENTER: |
| 746 | oX = min((u32)umode->hdisplay, oX); |
| 747 | oY = min((u32)umode->vdisplay, oY); |
| 748 | /* fall-through */ |
| 749 | case DRM_MODE_SCALE_ASPECT: |
| 750 | if (oY < oX) { |
| 751 | u32 aspect = (umode->hdisplay << 19) / umode->vdisplay; |
| 752 | oX = ((oY * aspect) + (aspect / 2)) >> 19; |
| 753 | } else { |
| 754 | u32 aspect = (umode->vdisplay << 19) / umode->hdisplay; |
| 755 | oY = ((oX * aspect) + (aspect / 2)) >> 19; |
| 756 | } |
| 757 | break; |
| 758 | default: |
| 759 | break; |
| 760 | } |
| 761 | |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 762 | push = evo_wait(mast, 8); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 763 | if (push) { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 764 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 765 | /*XXX: SCALE_CTRL_ACTIVE??? */ |
| 766 | evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2); |
| 767 | evo_data(push, (oY << 16) | oX); |
| 768 | evo_data(push, (oY << 16) | oX); |
| 769 | evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1); |
| 770 | evo_data(push, 0x00000000); |
| 771 | evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1); |
| 772 | evo_data(push, umode->vdisplay << 16 | umode->hdisplay); |
| 773 | } else { |
| 774 | evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3); |
| 775 | evo_data(push, (oY << 16) | oX); |
| 776 | evo_data(push, (oY << 16) | oX); |
| 777 | evo_data(push, (oY << 16) | oX); |
| 778 | evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1); |
| 779 | evo_data(push, 0x00000000); |
| 780 | evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1); |
| 781 | evo_data(push, umode->vdisplay << 16 | umode->hdisplay); |
| 782 | } |
| 783 | |
| 784 | evo_kick(push, mast); |
| 785 | |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 786 | if (update) { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 787 | nv50_display_flip_stop(crtc); |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 788 | nv50_display_flip_next(crtc, crtc->primary->fb, |
| 789 | NULL, 1); |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 790 | } |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 791 | } |
| 792 | |
| 793 | return 0; |
| 794 | } |
| 795 | |
| 796 | static int |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 797 | nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update) |
Ben Skeggs | f9887d0 | 2012-11-21 13:03:42 +1000 | [diff] [blame] | 798 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 799 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
Ben Skeggs | f9887d0 | 2012-11-21 13:03:42 +1000 | [diff] [blame] | 800 | u32 *push, hue, vib; |
| 801 | int adj; |
| 802 | |
| 803 | adj = (nv_crtc->color_vibrance > 0) ? 50 : 0; |
| 804 | vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff; |
| 805 | hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff; |
| 806 | |
| 807 | push = evo_wait(mast, 16); |
| 808 | if (push) { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 809 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
Ben Skeggs | f9887d0 | 2012-11-21 13:03:42 +1000 | [diff] [blame] | 810 | evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1); |
| 811 | evo_data(push, (hue << 20) | (vib << 8)); |
| 812 | } else { |
| 813 | evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1); |
| 814 | evo_data(push, (hue << 20) | (vib << 8)); |
| 815 | } |
| 816 | |
| 817 | if (update) { |
| 818 | evo_mthd(push, 0x0080, 1); |
| 819 | evo_data(push, 0x00000000); |
| 820 | } |
| 821 | evo_kick(push, mast); |
| 822 | } |
| 823 | |
| 824 | return 0; |
| 825 | } |
| 826 | |
| 827 | static int |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 828 | nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb, |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 829 | int x, int y, bool update) |
| 830 | { |
| 831 | struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb); |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 832 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 833 | u32 *push; |
| 834 | |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 835 | push = evo_wait(mast, 16); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 836 | if (push) { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 837 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 838 | evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1); |
| 839 | evo_data(push, nvfb->nvbo->bo.offset >> 8); |
| 840 | evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3); |
| 841 | evo_data(push, (fb->height << 16) | fb->width); |
| 842 | evo_data(push, nvfb->r_pitch); |
| 843 | evo_data(push, nvfb->r_format); |
| 844 | evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1); |
| 845 | evo_data(push, (y << 16) | x); |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 846 | if (nv50_vers(mast) > NV50_DISP_MAST_CLASS) { |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 847 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
| 848 | evo_data(push, nvfb->r_dma); |
| 849 | } |
| 850 | } else { |
| 851 | evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1); |
| 852 | evo_data(push, nvfb->nvbo->bo.offset >> 8); |
| 853 | evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4); |
| 854 | evo_data(push, (fb->height << 16) | fb->width); |
| 855 | evo_data(push, nvfb->r_pitch); |
| 856 | evo_data(push, nvfb->r_format); |
| 857 | evo_data(push, nvfb->r_dma); |
| 858 | evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1); |
| 859 | evo_data(push, (y << 16) | x); |
| 860 | } |
| 861 | |
Ben Skeggs | a46232e | 2011-07-07 15:23:48 +1000 | [diff] [blame] | 862 | if (update) { |
| 863 | evo_mthd(push, 0x0080, 1); |
| 864 | evo_data(push, 0x00000000); |
| 865 | } |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 866 | evo_kick(push, mast); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 867 | } |
| 868 | |
Ben Skeggs | c0cc92a | 2011-07-06 11:40:45 +1000 | [diff] [blame] | 869 | nv_crtc->fb.tile_flags = nvfb->r_dma; |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 870 | return 0; |
| 871 | } |
| 872 | |
| 873 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 874 | nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc) |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 875 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 876 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 877 | u32 *push = evo_wait(mast, 16); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 878 | if (push) { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 879 | if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) { |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 880 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2); |
| 881 | evo_data(push, 0x85000000); |
| 882 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); |
| 883 | } else |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 884 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 885 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2); |
| 886 | evo_data(push, 0x85000000); |
| 887 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); |
| 888 | evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1); |
| 889 | evo_data(push, NvEvoVRAM); |
| 890 | } else { |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 891 | evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2); |
| 892 | evo_data(push, 0x85000000); |
| 893 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); |
| 894 | evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1); |
Ben Skeggs | 37b034a | 2011-07-08 14:43:19 +1000 | [diff] [blame] | 895 | evo_data(push, NvEvoVRAM); |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 896 | } |
| 897 | evo_kick(push, mast); |
| 898 | } |
| 899 | } |
| 900 | |
| 901 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 902 | nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc) |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 903 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 904 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 905 | u32 *push = evo_wait(mast, 16); |
| 906 | if (push) { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 907 | if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) { |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 908 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1); |
| 909 | evo_data(push, 0x05000000); |
| 910 | } else |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 911 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 912 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1); |
| 913 | evo_data(push, 0x05000000); |
| 914 | evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1); |
| 915 | evo_data(push, 0x00000000); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 916 | } else { |
| 917 | evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1); |
| 918 | evo_data(push, 0x05000000); |
| 919 | evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1); |
| 920 | evo_data(push, 0x00000000); |
| 921 | } |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 922 | evo_kick(push, mast); |
| 923 | } |
| 924 | } |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 925 | |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 926 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 927 | nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update) |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 928 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 929 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 930 | |
| 931 | if (show) |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 932 | nv50_crtc_cursor_show(nv_crtc); |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 933 | else |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 934 | nv50_crtc_cursor_hide(nv_crtc); |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 935 | |
| 936 | if (update) { |
| 937 | u32 *push = evo_wait(mast, 2); |
| 938 | if (push) { |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 939 | evo_mthd(push, 0x0080, 1); |
| 940 | evo_data(push, 0x00000000); |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 941 | evo_kick(push, mast); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 942 | } |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 943 | } |
| 944 | } |
| 945 | |
| 946 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 947 | nv50_crtc_dpms(struct drm_crtc *crtc, int mode) |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 948 | { |
| 949 | } |
| 950 | |
| 951 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 952 | nv50_crtc_prepare(struct drm_crtc *crtc) |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 953 | { |
| 954 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 955 | struct nv50_mast *mast = nv50_mast(crtc->dev); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 956 | u32 *push; |
| 957 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 958 | nv50_display_flip_stop(crtc); |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 959 | |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 960 | push = evo_wait(mast, 2); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 961 | if (push) { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 962 | if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) { |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 963 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
| 964 | evo_data(push, 0x00000000); |
| 965 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1); |
| 966 | evo_data(push, 0x40000000); |
| 967 | } else |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 968 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 969 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
| 970 | evo_data(push, 0x00000000); |
| 971 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1); |
| 972 | evo_data(push, 0x40000000); |
| 973 | evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1); |
| 974 | evo_data(push, 0x00000000); |
| 975 | } else { |
| 976 | evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1); |
| 977 | evo_data(push, 0x00000000); |
| 978 | evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1); |
| 979 | evo_data(push, 0x03000000); |
| 980 | evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1); |
| 981 | evo_data(push, 0x00000000); |
| 982 | } |
| 983 | |
| 984 | evo_kick(push, mast); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 985 | } |
| 986 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 987 | nv50_crtc_cursor_show_hide(nv_crtc, false, false); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 988 | } |
| 989 | |
| 990 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 991 | nv50_crtc_commit(struct drm_crtc *crtc) |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 992 | { |
| 993 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 994 | struct nv50_mast *mast = nv50_mast(crtc->dev); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 995 | u32 *push; |
| 996 | |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 997 | push = evo_wait(mast, 32); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 998 | if (push) { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 999 | if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) { |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 1000 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
| 1001 | evo_data(push, NvEvoVRAM_LP); |
| 1002 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2); |
| 1003 | evo_data(push, 0xc0000000); |
| 1004 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); |
| 1005 | } else |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1006 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 1007 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
| 1008 | evo_data(push, nv_crtc->fb.tile_flags); |
| 1009 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2); |
| 1010 | evo_data(push, 0xc0000000); |
| 1011 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); |
| 1012 | evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1); |
| 1013 | evo_data(push, NvEvoVRAM); |
| 1014 | } else { |
| 1015 | evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1); |
| 1016 | evo_data(push, nv_crtc->fb.tile_flags); |
| 1017 | evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4); |
| 1018 | evo_data(push, 0x83000000); |
| 1019 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); |
| 1020 | evo_data(push, 0x00000000); |
| 1021 | evo_data(push, 0x00000000); |
| 1022 | evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1); |
| 1023 | evo_data(push, NvEvoVRAM); |
| 1024 | evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1); |
| 1025 | evo_data(push, 0xffffff00); |
| 1026 | } |
| 1027 | |
| 1028 | evo_kick(push, mast); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1029 | } |
| 1030 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1031 | nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true); |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1032 | nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1033 | } |
| 1034 | |
| 1035 | static bool |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1036 | nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1037 | struct drm_display_mode *adjusted_mode) |
| 1038 | { |
Ben Skeggs | eb2e968 | 2014-01-24 10:13:23 +1000 | [diff] [blame] | 1039 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1040 | return true; |
| 1041 | } |
| 1042 | |
| 1043 | static int |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1044 | nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1045 | { |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1046 | struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb); |
Ben Skeggs | 8dda53f | 2013-07-09 12:35:55 +1000 | [diff] [blame] | 1047 | struct nv50_head *head = nv50_head(crtc); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1048 | int ret; |
| 1049 | |
| 1050 | ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM); |
Ben Skeggs | 8dda53f | 2013-07-09 12:35:55 +1000 | [diff] [blame] | 1051 | if (ret == 0) { |
| 1052 | if (head->image) |
| 1053 | nouveau_bo_unpin(head->image); |
| 1054 | nouveau_bo_ref(nvfb->nvbo, &head->image); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1055 | } |
| 1056 | |
Ben Skeggs | 8dda53f | 2013-07-09 12:35:55 +1000 | [diff] [blame] | 1057 | return ret; |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1058 | } |
| 1059 | |
| 1060 | static int |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1061 | nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode, |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1062 | struct drm_display_mode *mode, int x, int y, |
| 1063 | struct drm_framebuffer *old_fb) |
| 1064 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1065 | struct nv50_mast *mast = nv50_mast(crtc->dev); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1066 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 1067 | struct nouveau_connector *nv_connector; |
Ben Skeggs | 2d1d898 | 2011-11-11 23:39:22 +1000 | [diff] [blame] | 1068 | u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1; |
| 1069 | u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1; |
| 1070 | u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks; |
| 1071 | u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks; |
| 1072 | u32 vblan2e = 0, vblan2s = 1; |
Ben Skeggs | 3488c57 | 2012-03-12 11:42:20 +1000 | [diff] [blame] | 1073 | u32 *push; |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1074 | int ret; |
| 1075 | |
Ben Skeggs | 2d1d898 | 2011-11-11 23:39:22 +1000 | [diff] [blame] | 1076 | hactive = mode->htotal; |
| 1077 | hsynce = mode->hsync_end - mode->hsync_start - 1; |
| 1078 | hbackp = mode->htotal - mode->hsync_end; |
| 1079 | hblanke = hsynce + hbackp; |
| 1080 | hfrontp = mode->hsync_start - mode->hdisplay; |
| 1081 | hblanks = mode->htotal - hfrontp - 1; |
| 1082 | |
| 1083 | vactive = mode->vtotal * vscan / ilace; |
| 1084 | vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1; |
| 1085 | vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace; |
| 1086 | vblanke = vsynce + vbackp; |
| 1087 | vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace; |
| 1088 | vblanks = vactive - vfrontp - 1; |
| 1089 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
| 1090 | vblan2e = vactive + vsynce + vbackp; |
| 1091 | vblan2s = vblan2e + (mode->vdisplay * vscan / ilace); |
| 1092 | vactive = (vactive * 2) + 1; |
Ben Skeggs | 2d1d898 | 2011-11-11 23:39:22 +1000 | [diff] [blame] | 1093 | } |
| 1094 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1095 | ret = nv50_crtc_swap_fbs(crtc, old_fb); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1096 | if (ret) |
| 1097 | return ret; |
| 1098 | |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 1099 | push = evo_wait(mast, 64); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1100 | if (push) { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1101 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 1102 | evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2); |
| 1103 | evo_data(push, 0x00800000 | mode->clock); |
| 1104 | evo_data(push, (ilace == 2) ? 2 : 0); |
| 1105 | evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6); |
| 1106 | evo_data(push, 0x00000000); |
| 1107 | evo_data(push, (vactive << 16) | hactive); |
| 1108 | evo_data(push, ( vsynce << 16) | hsynce); |
| 1109 | evo_data(push, (vblanke << 16) | hblanke); |
| 1110 | evo_data(push, (vblanks << 16) | hblanks); |
| 1111 | evo_data(push, (vblan2e << 16) | vblan2s); |
| 1112 | evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1); |
| 1113 | evo_data(push, 0x00000000); |
| 1114 | evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2); |
| 1115 | evo_data(push, 0x00000311); |
| 1116 | evo_data(push, 0x00000100); |
| 1117 | } else { |
| 1118 | evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6); |
| 1119 | evo_data(push, 0x00000000); |
| 1120 | evo_data(push, (vactive << 16) | hactive); |
| 1121 | evo_data(push, ( vsynce << 16) | hsynce); |
| 1122 | evo_data(push, (vblanke << 16) | hblanke); |
| 1123 | evo_data(push, (vblanks << 16) | hblanks); |
| 1124 | evo_data(push, (vblan2e << 16) | vblan2s); |
| 1125 | evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1); |
| 1126 | evo_data(push, 0x00000000); /* ??? */ |
| 1127 | evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3); |
| 1128 | evo_data(push, mode->clock * 1000); |
| 1129 | evo_data(push, 0x00200000); /* ??? */ |
| 1130 | evo_data(push, mode->clock * 1000); |
| 1131 | evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2); |
| 1132 | evo_data(push, 0x00000311); |
| 1133 | evo_data(push, 0x00000100); |
| 1134 | } |
| 1135 | |
| 1136 | evo_kick(push, mast); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1137 | } |
| 1138 | |
| 1139 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1140 | nv50_crtc_set_dither(nv_crtc, false); |
| 1141 | nv50_crtc_set_scale(nv_crtc, false); |
| 1142 | nv50_crtc_set_color_vibrance(nv_crtc, false); |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1143 | nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, false); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1144 | return 0; |
| 1145 | } |
| 1146 | |
| 1147 | static int |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1148 | nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1149 | struct drm_framebuffer *old_fb) |
| 1150 | { |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 1151 | struct nouveau_drm *drm = nouveau_drm(crtc->dev); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1152 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 1153 | int ret; |
| 1154 | |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1155 | if (!crtc->primary->fb) { |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 1156 | NV_DEBUG(drm, "No FB bound\n"); |
Ben Skeggs | 84e2ad8 | 2011-08-26 09:40:39 +1000 | [diff] [blame] | 1157 | return 0; |
| 1158 | } |
| 1159 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1160 | ret = nv50_crtc_swap_fbs(crtc, old_fb); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1161 | if (ret) |
| 1162 | return ret; |
| 1163 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1164 | nv50_display_flip_stop(crtc); |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1165 | nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, true); |
| 1166 | nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1167 | return 0; |
| 1168 | } |
| 1169 | |
| 1170 | static int |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1171 | nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc, |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1172 | struct drm_framebuffer *fb, int x, int y, |
| 1173 | enum mode_set_atomic state) |
| 1174 | { |
| 1175 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1176 | nv50_display_flip_stop(crtc); |
| 1177 | nv50_crtc_set_image(nv_crtc, fb, x, y, true); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1178 | return 0; |
| 1179 | } |
| 1180 | |
| 1181 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1182 | nv50_crtc_lut_load(struct drm_crtc *crtc) |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1183 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1184 | struct nv50_disp *disp = nv50_disp(crtc->dev); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1185 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 1186 | void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo); |
| 1187 | int i; |
| 1188 | |
| 1189 | for (i = 0; i < 256; i++) { |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 1190 | u16 r = nv_crtc->lut.r[i] >> 2; |
| 1191 | u16 g = nv_crtc->lut.g[i] >> 2; |
| 1192 | u16 b = nv_crtc->lut.b[i] >> 2; |
| 1193 | |
| 1194 | if (nv_mclass(disp->core) < NVD0_DISP_CLASS) { |
| 1195 | writew(r + 0x0000, lut + (i * 0x08) + 0); |
| 1196 | writew(g + 0x0000, lut + (i * 0x08) + 2); |
| 1197 | writew(b + 0x0000, lut + (i * 0x08) + 4); |
| 1198 | } else { |
| 1199 | writew(r + 0x6000, lut + (i * 0x20) + 0); |
| 1200 | writew(g + 0x6000, lut + (i * 0x20) + 2); |
| 1201 | writew(b + 0x6000, lut + (i * 0x20) + 4); |
| 1202 | } |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1203 | } |
| 1204 | } |
| 1205 | |
Ben Skeggs | 8dda53f | 2013-07-09 12:35:55 +1000 | [diff] [blame] | 1206 | static void |
| 1207 | nv50_crtc_disable(struct drm_crtc *crtc) |
| 1208 | { |
| 1209 | struct nv50_head *head = nv50_head(crtc); |
| 1210 | if (head->image) |
| 1211 | nouveau_bo_unpin(head->image); |
| 1212 | nouveau_bo_ref(NULL, &head->image); |
| 1213 | } |
| 1214 | |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1215 | static int |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1216 | nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1217 | uint32_t handle, uint32_t width, uint32_t height) |
| 1218 | { |
| 1219 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 1220 | struct drm_device *dev = crtc->dev; |
| 1221 | struct drm_gem_object *gem; |
| 1222 | struct nouveau_bo *nvbo; |
| 1223 | bool visible = (handle != 0); |
| 1224 | int i, ret = 0; |
| 1225 | |
| 1226 | if (visible) { |
| 1227 | if (width != 64 || height != 64) |
| 1228 | return -EINVAL; |
| 1229 | |
| 1230 | gem = drm_gem_object_lookup(dev, file_priv, handle); |
| 1231 | if (unlikely(!gem)) |
| 1232 | return -ENOENT; |
| 1233 | nvbo = nouveau_gem_object(gem); |
| 1234 | |
| 1235 | ret = nouveau_bo_map(nvbo); |
| 1236 | if (ret == 0) { |
| 1237 | for (i = 0; i < 64 * 64; i++) { |
| 1238 | u32 v = nouveau_bo_rd32(nvbo, i); |
| 1239 | nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v); |
| 1240 | } |
| 1241 | nouveau_bo_unmap(nvbo); |
| 1242 | } |
| 1243 | |
| 1244 | drm_gem_object_unreference_unlocked(gem); |
| 1245 | } |
| 1246 | |
| 1247 | if (visible != nv_crtc->cursor.visible) { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1248 | nv50_crtc_cursor_show_hide(nv_crtc, visible, true); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1249 | nv_crtc->cursor.visible = visible; |
| 1250 | } |
| 1251 | |
| 1252 | return ret; |
| 1253 | } |
| 1254 | |
| 1255 | static int |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1256 | nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1257 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1258 | struct nv50_curs *curs = nv50_curs(crtc); |
| 1259 | struct nv50_chan *chan = nv50_chan(curs); |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 1260 | nv_wo32(chan->user, 0x0084, (y << 16) | (x & 0xffff)); |
| 1261 | nv_wo32(chan->user, 0x0080, 0x00000000); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1262 | return 0; |
| 1263 | } |
| 1264 | |
| 1265 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1266 | nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1267 | uint32_t start, uint32_t size) |
| 1268 | { |
| 1269 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
Dan Carpenter | bdefc8c | 2013-11-28 01:18:47 +0300 | [diff] [blame] | 1270 | u32 end = min_t(u32, start + size, 256); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1271 | u32 i; |
| 1272 | |
| 1273 | for (i = start; i < end; i++) { |
| 1274 | nv_crtc->lut.r[i] = r[i]; |
| 1275 | nv_crtc->lut.g[i] = g[i]; |
| 1276 | nv_crtc->lut.b[i] = b[i]; |
| 1277 | } |
| 1278 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1279 | nv50_crtc_lut_load(crtc); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1280 | } |
| 1281 | |
| 1282 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1283 | nv50_crtc_destroy(struct drm_crtc *crtc) |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1284 | { |
| 1285 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1286 | struct nv50_disp *disp = nv50_disp(crtc->dev); |
| 1287 | struct nv50_head *head = nv50_head(crtc); |
Ben Skeggs | 8dda53f | 2013-07-09 12:35:55 +1000 | [diff] [blame] | 1288 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1289 | nv50_dmac_destroy(disp->core, &head->ovly.base); |
| 1290 | nv50_pioc_destroy(disp->core, &head->oimm.base); |
| 1291 | nv50_dmac_destroy(disp->core, &head->sync.base); |
| 1292 | nv50_pioc_destroy(disp->core, &head->curs.base); |
Ben Skeggs | 8dda53f | 2013-07-09 12:35:55 +1000 | [diff] [blame] | 1293 | |
| 1294 | /*XXX: this shouldn't be necessary, but the core doesn't call |
| 1295 | * disconnect() during the cleanup paths |
| 1296 | */ |
| 1297 | if (head->image) |
| 1298 | nouveau_bo_unpin(head->image); |
| 1299 | nouveau_bo_ref(NULL, &head->image); |
| 1300 | |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1301 | nouveau_bo_unmap(nv_crtc->cursor.nvbo); |
Marcin Slusarz | 04c8c21 | 2012-11-25 23:04:23 +0100 | [diff] [blame] | 1302 | if (nv_crtc->cursor.nvbo) |
| 1303 | nouveau_bo_unpin(nv_crtc->cursor.nvbo); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1304 | nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); |
Ben Skeggs | 8dda53f | 2013-07-09 12:35:55 +1000 | [diff] [blame] | 1305 | |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1306 | nouveau_bo_unmap(nv_crtc->lut.nvbo); |
Marcin Slusarz | 04c8c21 | 2012-11-25 23:04:23 +0100 | [diff] [blame] | 1307 | if (nv_crtc->lut.nvbo) |
| 1308 | nouveau_bo_unpin(nv_crtc->lut.nvbo); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1309 | nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); |
Ben Skeggs | 8dda53f | 2013-07-09 12:35:55 +1000 | [diff] [blame] | 1310 | |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1311 | drm_crtc_cleanup(crtc); |
| 1312 | kfree(crtc); |
| 1313 | } |
| 1314 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1315 | static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = { |
| 1316 | .dpms = nv50_crtc_dpms, |
| 1317 | .prepare = nv50_crtc_prepare, |
| 1318 | .commit = nv50_crtc_commit, |
| 1319 | .mode_fixup = nv50_crtc_mode_fixup, |
| 1320 | .mode_set = nv50_crtc_mode_set, |
| 1321 | .mode_set_base = nv50_crtc_mode_set_base, |
| 1322 | .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic, |
| 1323 | .load_lut = nv50_crtc_lut_load, |
Ben Skeggs | 8dda53f | 2013-07-09 12:35:55 +1000 | [diff] [blame] | 1324 | .disable = nv50_crtc_disable, |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1325 | }; |
| 1326 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1327 | static const struct drm_crtc_funcs nv50_crtc_func = { |
| 1328 | .cursor_set = nv50_crtc_cursor_set, |
| 1329 | .cursor_move = nv50_crtc_cursor_move, |
| 1330 | .gamma_set = nv50_crtc_gamma_set, |
Dave Airlie | 5addcf0 | 2012-09-10 14:20:51 +1000 | [diff] [blame] | 1331 | .set_config = nouveau_crtc_set_config, |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1332 | .destroy = nv50_crtc_destroy, |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 1333 | .page_flip = nouveau_crtc_page_flip, |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1334 | }; |
| 1335 | |
Ben Skeggs | c20ab3e | 2011-08-25 14:09:43 +1000 | [diff] [blame] | 1336 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1337 | nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y) |
Ben Skeggs | c20ab3e | 2011-08-25 14:09:43 +1000 | [diff] [blame] | 1338 | { |
| 1339 | } |
| 1340 | |
| 1341 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1342 | nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset) |
Ben Skeggs | c20ab3e | 2011-08-25 14:09:43 +1000 | [diff] [blame] | 1343 | { |
| 1344 | } |
| 1345 | |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1346 | static int |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1347 | nv50_crtc_create(struct drm_device *dev, struct nouveau_object *core, int index) |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1348 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1349 | struct nv50_disp *disp = nv50_disp(dev); |
| 1350 | struct nv50_head *head; |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1351 | struct drm_crtc *crtc; |
| 1352 | int ret, i; |
| 1353 | |
Ben Skeggs | dd0e3d5 | 2012-10-16 14:00:31 +1000 | [diff] [blame] | 1354 | head = kzalloc(sizeof(*head), GFP_KERNEL); |
| 1355 | if (!head) |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1356 | return -ENOMEM; |
| 1357 | |
Ben Skeggs | dd0e3d5 | 2012-10-16 14:00:31 +1000 | [diff] [blame] | 1358 | head->base.index = index; |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1359 | head->base.set_dither = nv50_crtc_set_dither; |
| 1360 | head->base.set_scale = nv50_crtc_set_scale; |
| 1361 | head->base.set_color_vibrance = nv50_crtc_set_color_vibrance; |
Ben Skeggs | f9887d0 | 2012-11-21 13:03:42 +1000 | [diff] [blame] | 1362 | head->base.color_vibrance = 50; |
| 1363 | head->base.vibrant_hue = 0; |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1364 | head->base.cursor.set_offset = nv50_cursor_set_offset; |
| 1365 | head->base.cursor.set_pos = nv50_cursor_set_pos; |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1366 | for (i = 0; i < 256; i++) { |
Ben Skeggs | dd0e3d5 | 2012-10-16 14:00:31 +1000 | [diff] [blame] | 1367 | head->base.lut.r[i] = i << 8; |
| 1368 | head->base.lut.g[i] = i << 8; |
| 1369 | head->base.lut.b[i] = i << 8; |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1370 | } |
| 1371 | |
Ben Skeggs | dd0e3d5 | 2012-10-16 14:00:31 +1000 | [diff] [blame] | 1372 | crtc = &head->base.base; |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1373 | drm_crtc_init(dev, crtc, &nv50_crtc_func); |
| 1374 | drm_crtc_helper_add(crtc, &nv50_crtc_hfunc); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1375 | drm_mode_crtc_set_gamma_size(crtc, 256); |
| 1376 | |
Ben Skeggs | 8ea0d4a | 2011-07-07 14:49:24 +1000 | [diff] [blame] | 1377 | ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM, |
Ben Skeggs | dd0e3d5 | 2012-10-16 14:00:31 +1000 | [diff] [blame] | 1378 | 0, 0x0000, NULL, &head->base.lut.nvbo); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1379 | if (!ret) { |
Ben Skeggs | dd0e3d5 | 2012-10-16 14:00:31 +1000 | [diff] [blame] | 1380 | ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM); |
Marcin Slusarz | 04c8c21 | 2012-11-25 23:04:23 +0100 | [diff] [blame] | 1381 | if (!ret) { |
Ben Skeggs | dd0e3d5 | 2012-10-16 14:00:31 +1000 | [diff] [blame] | 1382 | ret = nouveau_bo_map(head->base.lut.nvbo); |
Marcin Slusarz | 04c8c21 | 2012-11-25 23:04:23 +0100 | [diff] [blame] | 1383 | if (ret) |
| 1384 | nouveau_bo_unpin(head->base.lut.nvbo); |
| 1385 | } |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1386 | if (ret) |
Ben Skeggs | dd0e3d5 | 2012-10-16 14:00:31 +1000 | [diff] [blame] | 1387 | nouveau_bo_ref(NULL, &head->base.lut.nvbo); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1388 | } |
| 1389 | |
| 1390 | if (ret) |
| 1391 | goto out; |
| 1392 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1393 | nv50_crtc_lut_load(crtc); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1394 | |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 1395 | /* allocate cursor resources */ |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1396 | ret = nv50_pioc_create(disp->core, NV50_DISP_CURS_CLASS, index, |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 1397 | &(struct nv50_display_curs_class) { |
| 1398 | .head = index, |
| 1399 | }, sizeof(struct nv50_display_curs_class), |
| 1400 | &head->curs.base); |
| 1401 | if (ret) |
| 1402 | goto out; |
| 1403 | |
| 1404 | ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM, |
| 1405 | 0, 0x0000, NULL, &head->base.cursor.nvbo); |
| 1406 | if (!ret) { |
| 1407 | ret = nouveau_bo_pin(head->base.cursor.nvbo, TTM_PL_FLAG_VRAM); |
Marcin Slusarz | 04c8c21 | 2012-11-25 23:04:23 +0100 | [diff] [blame] | 1408 | if (!ret) { |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 1409 | ret = nouveau_bo_map(head->base.cursor.nvbo); |
Marcin Slusarz | 04c8c21 | 2012-11-25 23:04:23 +0100 | [diff] [blame] | 1410 | if (ret) |
| 1411 | nouveau_bo_unpin(head->base.lut.nvbo); |
| 1412 | } |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 1413 | if (ret) |
| 1414 | nouveau_bo_ref(NULL, &head->base.cursor.nvbo); |
| 1415 | } |
| 1416 | |
| 1417 | if (ret) |
| 1418 | goto out; |
| 1419 | |
| 1420 | /* allocate page flip / sync resources */ |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1421 | ret = nv50_dmac_create(disp->core, NV50_DISP_SYNC_CLASS, index, |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 1422 | &(struct nv50_display_sync_class) { |
| 1423 | .pushbuf = EVO_PUSH_HANDLE(SYNC, index), |
| 1424 | .head = index, |
| 1425 | }, sizeof(struct nv50_display_sync_class), |
| 1426 | disp->sync->bo.offset, &head->sync.base); |
| 1427 | if (ret) |
| 1428 | goto out; |
| 1429 | |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 1430 | head->sync.addr = EVO_FLIP_SEM0(index); |
| 1431 | head->sync.data = 0x00000000; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 1432 | |
| 1433 | /* allocate overlay resources */ |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1434 | ret = nv50_pioc_create(disp->core, NV50_DISP_OIMM_CLASS, index, |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 1435 | &(struct nv50_display_oimm_class) { |
| 1436 | .head = index, |
| 1437 | }, sizeof(struct nv50_display_oimm_class), |
| 1438 | &head->oimm.base); |
| 1439 | if (ret) |
| 1440 | goto out; |
| 1441 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1442 | ret = nv50_dmac_create(disp->core, NV50_DISP_OVLY_CLASS, index, |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 1443 | &(struct nv50_display_ovly_class) { |
| 1444 | .pushbuf = EVO_PUSH_HANDLE(OVLY, index), |
| 1445 | .head = index, |
| 1446 | }, sizeof(struct nv50_display_ovly_class), |
| 1447 | disp->sync->bo.offset, &head->ovly.base); |
| 1448 | if (ret) |
| 1449 | goto out; |
| 1450 | |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1451 | out: |
| 1452 | if (ret) |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1453 | nv50_crtc_destroy(crtc); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 1454 | return ret; |
| 1455 | } |
| 1456 | |
| 1457 | /****************************************************************************** |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 1458 | * DAC |
| 1459 | *****************************************************************************/ |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1460 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1461 | nv50_dac_dpms(struct drm_encoder *encoder, int mode) |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1462 | { |
| 1463 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1464 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1465 | int or = nv_encoder->or; |
| 1466 | u32 dpms_ctrl; |
| 1467 | |
Ben Skeggs | 35b21d3 | 2012-11-08 12:08:55 +1000 | [diff] [blame] | 1468 | dpms_ctrl = 0x00000000; |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1469 | if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF) |
| 1470 | dpms_ctrl |= 0x00000001; |
| 1471 | if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF) |
| 1472 | dpms_ctrl |= 0x00000004; |
| 1473 | |
Ben Skeggs | 35b21d3 | 2012-11-08 12:08:55 +1000 | [diff] [blame] | 1474 | nv_call(disp->core, NV50_DISP_DAC_PWR + or, dpms_ctrl); |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1475 | } |
| 1476 | |
| 1477 | static bool |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1478 | nv50_dac_mode_fixup(struct drm_encoder *encoder, |
Laurent Pinchart | e811f5a | 2012-07-17 17:56:50 +0200 | [diff] [blame] | 1479 | const struct drm_display_mode *mode, |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1480 | struct drm_display_mode *adjusted_mode) |
| 1481 | { |
| 1482 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 1483 | struct nouveau_connector *nv_connector; |
| 1484 | |
| 1485 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
| 1486 | if (nv_connector && nv_connector->native_mode) { |
| 1487 | if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { |
| 1488 | int id = adjusted_mode->base.id; |
| 1489 | *adjusted_mode = *nv_connector->native_mode; |
| 1490 | adjusted_mode->base.id = id; |
| 1491 | } |
| 1492 | } |
| 1493 | |
| 1494 | return true; |
| 1495 | } |
| 1496 | |
| 1497 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1498 | nv50_dac_commit(struct drm_encoder *encoder) |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1499 | { |
| 1500 | } |
| 1501 | |
| 1502 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1503 | nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1504 | struct drm_display_mode *adjusted_mode) |
| 1505 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1506 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1507 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 1508 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); |
Ben Skeggs | 97b19b5 | 2012-11-16 11:21:37 +1000 | [diff] [blame] | 1509 | u32 *push; |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1510 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1511 | nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON); |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1512 | |
Ben Skeggs | 97b19b5 | 2012-11-16 11:21:37 +1000 | [diff] [blame] | 1513 | push = evo_wait(mast, 8); |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1514 | if (push) { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1515 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
Ben Skeggs | 97b19b5 | 2012-11-16 11:21:37 +1000 | [diff] [blame] | 1516 | u32 syncs = 0x00000000; |
| 1517 | |
| 1518 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 1519 | syncs |= 0x00000001; |
| 1520 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 1521 | syncs |= 0x00000002; |
| 1522 | |
| 1523 | evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2); |
| 1524 | evo_data(push, 1 << nv_crtc->index); |
| 1525 | evo_data(push, syncs); |
| 1526 | } else { |
| 1527 | u32 magic = 0x31ec6000 | (nv_crtc->index << 25); |
| 1528 | u32 syncs = 0x00000001; |
| 1529 | |
| 1530 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 1531 | syncs |= 0x00000008; |
| 1532 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 1533 | syncs |= 0x00000010; |
| 1534 | |
| 1535 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 1536 | magic |= 0x00000001; |
| 1537 | |
| 1538 | evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2); |
| 1539 | evo_data(push, syncs); |
| 1540 | evo_data(push, magic); |
| 1541 | evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1); |
| 1542 | evo_data(push, 1 << nv_crtc->index); |
| 1543 | } |
| 1544 | |
| 1545 | evo_kick(push, mast); |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1546 | } |
| 1547 | |
| 1548 | nv_encoder->crtc = encoder->crtc; |
| 1549 | } |
| 1550 | |
| 1551 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1552 | nv50_dac_disconnect(struct drm_encoder *encoder) |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1553 | { |
| 1554 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1555 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
Ben Skeggs | 97b19b5 | 2012-11-16 11:21:37 +1000 | [diff] [blame] | 1556 | const int or = nv_encoder->or; |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1557 | u32 *push; |
| 1558 | |
| 1559 | if (nv_encoder->crtc) { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1560 | nv50_crtc_prepare(nv_encoder->crtc); |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1561 | |
Ben Skeggs | 97b19b5 | 2012-11-16 11:21:37 +1000 | [diff] [blame] | 1562 | push = evo_wait(mast, 4); |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1563 | if (push) { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1564 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
Ben Skeggs | 97b19b5 | 2012-11-16 11:21:37 +1000 | [diff] [blame] | 1565 | evo_mthd(push, 0x0400 + (or * 0x080), 1); |
| 1566 | evo_data(push, 0x00000000); |
| 1567 | } else { |
| 1568 | evo_mthd(push, 0x0180 + (or * 0x020), 1); |
| 1569 | evo_data(push, 0x00000000); |
| 1570 | } |
Ben Skeggs | 97b19b5 | 2012-11-16 11:21:37 +1000 | [diff] [blame] | 1571 | evo_kick(push, mast); |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1572 | } |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1573 | } |
Ben Skeggs | 97b19b5 | 2012-11-16 11:21:37 +1000 | [diff] [blame] | 1574 | |
| 1575 | nv_encoder->crtc = NULL; |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1576 | } |
| 1577 | |
Ben Skeggs | b6d8e7e | 2011-07-07 09:51:29 +1000 | [diff] [blame] | 1578 | static enum drm_connector_status |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1579 | nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
Ben Skeggs | b6d8e7e | 2011-07-07 09:51:29 +1000 | [diff] [blame] | 1580 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1581 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
Ben Skeggs | 35b21d3 | 2012-11-08 12:08:55 +1000 | [diff] [blame] | 1582 | int ret, or = nouveau_encoder(encoder)->or; |
Ben Skeggs | d40ee48 | 2013-06-03 16:40:14 +1000 | [diff] [blame] | 1583 | u32 load = nouveau_drm(encoder->dev)->vbios.dactestval; |
| 1584 | if (load == 0) |
| 1585 | load = 340; |
Ben Skeggs | b681993 | 2011-07-08 11:14:50 +1000 | [diff] [blame] | 1586 | |
Ben Skeggs | 35b21d3 | 2012-11-08 12:08:55 +1000 | [diff] [blame] | 1587 | ret = nv_exec(disp->core, NV50_DISP_DAC_LOAD + or, &load, sizeof(load)); |
Ben Skeggs | 4b31ebc | 2013-09-04 11:01:42 +1000 | [diff] [blame] | 1588 | if (ret || !load) |
Ben Skeggs | 35b21d3 | 2012-11-08 12:08:55 +1000 | [diff] [blame] | 1589 | return connector_status_disconnected; |
Ben Skeggs | b681993 | 2011-07-08 11:14:50 +1000 | [diff] [blame] | 1590 | |
Ben Skeggs | 35b21d3 | 2012-11-08 12:08:55 +1000 | [diff] [blame] | 1591 | return connector_status_connected; |
Ben Skeggs | b6d8e7e | 2011-07-07 09:51:29 +1000 | [diff] [blame] | 1592 | } |
| 1593 | |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1594 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1595 | nv50_dac_destroy(struct drm_encoder *encoder) |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1596 | { |
| 1597 | drm_encoder_cleanup(encoder); |
| 1598 | kfree(encoder); |
| 1599 | } |
| 1600 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1601 | static const struct drm_encoder_helper_funcs nv50_dac_hfunc = { |
| 1602 | .dpms = nv50_dac_dpms, |
| 1603 | .mode_fixup = nv50_dac_mode_fixup, |
| 1604 | .prepare = nv50_dac_disconnect, |
| 1605 | .commit = nv50_dac_commit, |
| 1606 | .mode_set = nv50_dac_mode_set, |
| 1607 | .disable = nv50_dac_disconnect, |
| 1608 | .get_crtc = nv50_display_crtc_get, |
| 1609 | .detect = nv50_dac_detect |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1610 | }; |
| 1611 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1612 | static const struct drm_encoder_funcs nv50_dac_func = { |
| 1613 | .destroy = nv50_dac_destroy, |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1614 | }; |
| 1615 | |
| 1616 | static int |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1617 | nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1618 | { |
Ben Skeggs | 5ed5020 | 2013-02-11 20:15:03 +1000 | [diff] [blame] | 1619 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
| 1620 | struct nouveau_i2c *i2c = nouveau_i2c(drm->device); |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1621 | struct nouveau_encoder *nv_encoder; |
| 1622 | struct drm_encoder *encoder; |
Ben Skeggs | 5ed5020 | 2013-02-11 20:15:03 +1000 | [diff] [blame] | 1623 | int type = DRM_MODE_ENCODER_DAC; |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1624 | |
| 1625 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); |
| 1626 | if (!nv_encoder) |
| 1627 | return -ENOMEM; |
| 1628 | nv_encoder->dcb = dcbe; |
| 1629 | nv_encoder->or = ffs(dcbe->or) - 1; |
Ben Skeggs | 5ed5020 | 2013-02-11 20:15:03 +1000 | [diff] [blame] | 1630 | nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index); |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1631 | |
| 1632 | encoder = to_drm_encoder(nv_encoder); |
| 1633 | encoder->possible_crtcs = dcbe->heads; |
| 1634 | encoder->possible_clones = 0; |
Ben Skeggs | 5ed5020 | 2013-02-11 20:15:03 +1000 | [diff] [blame] | 1635 | drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type); |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1636 | drm_encoder_helper_add(encoder, &nv50_dac_hfunc); |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 1637 | |
| 1638 | drm_mode_connector_attach_encoder(connector, encoder); |
| 1639 | return 0; |
| 1640 | } |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 1641 | |
| 1642 | /****************************************************************************** |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 1643 | * Audio |
| 1644 | *****************************************************************************/ |
| 1645 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1646 | nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode) |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 1647 | { |
| 1648 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 1649 | struct nouveau_connector *nv_connector; |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1650 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 1651 | |
| 1652 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
| 1653 | if (!drm_detect_monitor_audio(nv_connector->edid)) |
| 1654 | return; |
| 1655 | |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 1656 | drm_edid_to_eld(&nv_connector->base, nv_connector->edid); |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 1657 | |
Ben Skeggs | 0a9e2b95 | 2012-11-08 14:03:56 +1000 | [diff] [blame] | 1658 | nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or, |
| 1659 | nv_connector->base.eld, |
| 1660 | nv_connector->base.eld[2] * 4); |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 1661 | } |
| 1662 | |
| 1663 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1664 | nv50_audio_disconnect(struct drm_encoder *encoder) |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 1665 | { |
| 1666 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1667 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 1668 | |
Ben Skeggs | 0a9e2b95 | 2012-11-08 14:03:56 +1000 | [diff] [blame] | 1669 | nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or, NULL, 0); |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 1670 | } |
| 1671 | |
| 1672 | /****************************************************************************** |
| 1673 | * HDMI |
| 1674 | *****************************************************************************/ |
| 1675 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1676 | nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode) |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 1677 | { |
Ben Skeggs | 64d9cc0 | 2011-11-11 19:51:20 +1000 | [diff] [blame] | 1678 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 1679 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); |
| 1680 | struct nouveau_connector *nv_connector; |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1681 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
Ben Skeggs | 1c30cd0 | 2012-11-08 14:22:28 +1000 | [diff] [blame] | 1682 | const u32 moff = (nv_crtc->index << 3) | nv_encoder->or; |
Ben Skeggs | 64d9cc0 | 2011-11-11 19:51:20 +1000 | [diff] [blame] | 1683 | u32 rekey = 56; /* binary driver, and tegra constant */ |
| 1684 | u32 max_ac_packet; |
| 1685 | |
| 1686 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
| 1687 | if (!drm_detect_hdmi_monitor(nv_connector->edid)) |
| 1688 | return; |
| 1689 | |
| 1690 | max_ac_packet = mode->htotal - mode->hdisplay; |
| 1691 | max_ac_packet -= rekey; |
| 1692 | max_ac_packet -= 18; /* constant from tegra */ |
| 1693 | max_ac_packet /= 32; |
| 1694 | |
Ben Skeggs | 1c30cd0 | 2012-11-08 14:22:28 +1000 | [diff] [blame] | 1695 | nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff, |
| 1696 | NV84_DISP_SOR_HDMI_PWR_STATE_ON | |
| 1697 | (max_ac_packet << 16) | rekey); |
Ben Skeggs | 091e40c | 2011-11-11 20:46:00 +1000 | [diff] [blame] | 1698 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1699 | nv50_audio_mode_set(encoder, mode); |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 1700 | } |
| 1701 | |
| 1702 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1703 | nv50_hdmi_disconnect(struct drm_encoder *encoder) |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 1704 | { |
Ben Skeggs | 64d9cc0 | 2011-11-11 19:51:20 +1000 | [diff] [blame] | 1705 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 1706 | struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1707 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
Ben Skeggs | 1c30cd0 | 2012-11-08 14:22:28 +1000 | [diff] [blame] | 1708 | const u32 moff = (nv_crtc->index << 3) | nv_encoder->or; |
Ben Skeggs | 64d9cc0 | 2011-11-11 19:51:20 +1000 | [diff] [blame] | 1709 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1710 | nv50_audio_disconnect(encoder); |
Ben Skeggs | 64d9cc0 | 2011-11-11 19:51:20 +1000 | [diff] [blame] | 1711 | |
Ben Skeggs | 1c30cd0 | 2012-11-08 14:22:28 +1000 | [diff] [blame] | 1712 | nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff, 0x00000000); |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 1713 | } |
| 1714 | |
| 1715 | /****************************************************************************** |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 1716 | * SOR |
| 1717 | *****************************************************************************/ |
Ben Skeggs | 6e83fda | 2012-03-11 01:28:48 +1000 | [diff] [blame] | 1718 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1719 | nv50_sor_dpms(struct drm_encoder *encoder, int mode) |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 1720 | { |
| 1721 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 1722 | struct drm_device *dev = encoder->dev; |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1723 | struct nv50_disp *disp = nv50_disp(dev); |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 1724 | struct drm_encoder *partner; |
| 1725 | int or = nv_encoder->or; |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 1726 | |
| 1727 | nv_encoder->last_dpms = mode; |
| 1728 | |
| 1729 | list_for_each_entry(partner, &dev->mode_config.encoder_list, head) { |
| 1730 | struct nouveau_encoder *nv_partner = nouveau_encoder(partner); |
| 1731 | |
| 1732 | if (partner->encoder_type != DRM_MODE_ENCODER_TMDS) |
| 1733 | continue; |
| 1734 | |
| 1735 | if (nv_partner != nv_encoder && |
Ben Skeggs | 26cfa81 | 2011-11-17 09:10:02 +1000 | [diff] [blame] | 1736 | nv_partner->dcb->or == nv_encoder->dcb->or) { |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 1737 | if (nv_partner->last_dpms == DRM_MODE_DPMS_ON) |
| 1738 | return; |
| 1739 | break; |
| 1740 | } |
| 1741 | } |
| 1742 | |
Ben Skeggs | 74b6685 | 2012-11-08 12:01:39 +1000 | [diff] [blame] | 1743 | nv_call(disp->core, NV50_DISP_SOR_PWR + or, (mode == DRM_MODE_DPMS_ON)); |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 1744 | } |
| 1745 | |
| 1746 | static bool |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1747 | nv50_sor_mode_fixup(struct drm_encoder *encoder, |
Laurent Pinchart | e811f5a | 2012-07-17 17:56:50 +0200 | [diff] [blame] | 1748 | const struct drm_display_mode *mode, |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 1749 | struct drm_display_mode *adjusted_mode) |
| 1750 | { |
| 1751 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 1752 | struct nouveau_connector *nv_connector; |
| 1753 | |
| 1754 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
| 1755 | if (nv_connector && nv_connector->native_mode) { |
| 1756 | if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { |
| 1757 | int id = adjusted_mode->base.id; |
| 1758 | *adjusted_mode = *nv_connector->native_mode; |
| 1759 | adjusted_mode->base.id = id; |
| 1760 | } |
| 1761 | } |
| 1762 | |
| 1763 | return true; |
| 1764 | } |
| 1765 | |
| 1766 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1767 | nv50_sor_disconnect(struct drm_encoder *encoder) |
Ben Skeggs | 4cbb0f8 | 2012-03-12 15:23:44 +1000 | [diff] [blame] | 1768 | { |
| 1769 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1770 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1771 | const int or = nv_encoder->or; |
Ben Skeggs | 4cbb0f8 | 2012-03-12 15:23:44 +1000 | [diff] [blame] | 1772 | u32 *push; |
| 1773 | |
| 1774 | if (nv_encoder->crtc) { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1775 | nv50_crtc_prepare(nv_encoder->crtc); |
Ben Skeggs | 4cbb0f8 | 2012-03-12 15:23:44 +1000 | [diff] [blame] | 1776 | |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1777 | push = evo_wait(mast, 4); |
Ben Skeggs | 4cbb0f8 | 2012-03-12 15:23:44 +1000 | [diff] [blame] | 1778 | if (push) { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1779 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1780 | evo_mthd(push, 0x0600 + (or * 0x40), 1); |
| 1781 | evo_data(push, 0x00000000); |
| 1782 | } else { |
| 1783 | evo_mthd(push, 0x0200 + (or * 0x20), 1); |
| 1784 | evo_data(push, 0x00000000); |
| 1785 | } |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1786 | evo_kick(push, mast); |
Ben Skeggs | 4cbb0f8 | 2012-03-12 15:23:44 +1000 | [diff] [blame] | 1787 | } |
| 1788 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1789 | nv50_hdmi_disconnect(encoder); |
Ben Skeggs | 4cbb0f8 | 2012-03-12 15:23:44 +1000 | [diff] [blame] | 1790 | } |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1791 | |
| 1792 | nv_encoder->last_dpms = DRM_MODE_DPMS_OFF; |
| 1793 | nv_encoder->crtc = NULL; |
Ben Skeggs | 4cbb0f8 | 2012-03-12 15:23:44 +1000 | [diff] [blame] | 1794 | } |
| 1795 | |
| 1796 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1797 | nv50_sor_commit(struct drm_encoder *encoder) |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 1798 | { |
| 1799 | } |
| 1800 | |
| 1801 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1802 | nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode, |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 1803 | struct drm_display_mode *mode) |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 1804 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1805 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
| 1806 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 1807 | struct drm_device *dev = encoder->dev; |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 1808 | struct nouveau_drm *drm = nouveau_drm(dev); |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 1809 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 1810 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 1811 | struct nouveau_connector *nv_connector; |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 1812 | struct nvbios *bios = &drm->vbios; |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1813 | u32 *push, lvds = 0; |
| 1814 | u8 owner = 1 << nv_crtc->index; |
| 1815 | u8 proto = 0xf; |
| 1816 | u8 depth = 0x0; |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 1817 | |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 1818 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
| 1819 | switch (nv_encoder->dcb->type) { |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 1820 | case DCB_OUTPUT_TMDS: |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 1821 | if (nv_encoder->dcb->sorconf.link & 1) { |
| 1822 | if (mode->clock < 165000) |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1823 | proto = 0x1; |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 1824 | else |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1825 | proto = 0x5; |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 1826 | } else { |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1827 | proto = 0x2; |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 1828 | } |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 1829 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1830 | nv50_hdmi_mode_set(encoder, mode); |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 1831 | break; |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 1832 | case DCB_OUTPUT_LVDS: |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1833 | proto = 0x0; |
| 1834 | |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 1835 | if (bios->fp_no_ddc) { |
| 1836 | if (bios->fp.dual_link) |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1837 | lvds |= 0x0100; |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 1838 | if (bios->fp.if_is_24bit) |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1839 | lvds |= 0x0200; |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 1840 | } else { |
Ben Skeggs | befb51e | 2011-11-18 10:23:59 +1000 | [diff] [blame] | 1841 | if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 1842 | if (((u8 *)nv_connector->edid)[121] == 2) |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1843 | lvds |= 0x0100; |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 1844 | } else |
| 1845 | if (mode->clock >= bios->fp.duallink_transition_clk) { |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1846 | lvds |= 0x0100; |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 1847 | } |
| 1848 | |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1849 | if (lvds & 0x0100) { |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 1850 | if (bios->fp.strapless_is_24bit & 2) |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1851 | lvds |= 0x0200; |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 1852 | } else { |
| 1853 | if (bios->fp.strapless_is_24bit & 1) |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1854 | lvds |= 0x0200; |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 1855 | } |
| 1856 | |
| 1857 | if (nv_connector->base.display_info.bpc == 8) |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1858 | lvds |= 0x0200; |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 1859 | } |
Ben Skeggs | 4a230fa | 2012-11-09 11:25:37 +1000 | [diff] [blame] | 1860 | |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1861 | nv_call(disp->core, NV50_DISP_SOR_LVDS_SCRIPT + nv_encoder->or, lvds); |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 1862 | break; |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 1863 | case DCB_OUTPUT_DP: |
Ben Skeggs | 3488c57 | 2012-03-12 11:42:20 +1000 | [diff] [blame] | 1864 | if (nv_connector->base.display_info.bpc == 6) { |
Ben Skeggs | 6e83fda | 2012-03-11 01:28:48 +1000 | [diff] [blame] | 1865 | nv_encoder->dp.datarate = mode->clock * 18 / 8; |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1866 | depth = 0x2; |
Ben Skeggs | bf2c886 | 2012-11-21 14:49:54 +1000 | [diff] [blame] | 1867 | } else |
| 1868 | if (nv_connector->base.display_info.bpc == 8) { |
Ben Skeggs | 6e83fda | 2012-03-11 01:28:48 +1000 | [diff] [blame] | 1869 | nv_encoder->dp.datarate = mode->clock * 24 / 8; |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1870 | depth = 0x5; |
Ben Skeggs | bf2c886 | 2012-11-21 14:49:54 +1000 | [diff] [blame] | 1871 | } else { |
| 1872 | nv_encoder->dp.datarate = mode->clock * 30 / 8; |
| 1873 | depth = 0x6; |
Ben Skeggs | 3488c57 | 2012-03-12 11:42:20 +1000 | [diff] [blame] | 1874 | } |
Ben Skeggs | 6e83fda | 2012-03-11 01:28:48 +1000 | [diff] [blame] | 1875 | |
| 1876 | if (nv_encoder->dcb->sorconf.link & 1) |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1877 | proto = 0x8; |
Ben Skeggs | 6e83fda | 2012-03-11 01:28:48 +1000 | [diff] [blame] | 1878 | else |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1879 | proto = 0x9; |
Ben Skeggs | 6e83fda | 2012-03-11 01:28:48 +1000 | [diff] [blame] | 1880 | break; |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 1881 | default: |
| 1882 | BUG_ON(1); |
| 1883 | break; |
| 1884 | } |
Ben Skeggs | ff8ff50 | 2011-07-08 11:53:37 +1000 | [diff] [blame] | 1885 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1886 | nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON); |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 1887 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1888 | push = evo_wait(nv50_mast(dev), 8); |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 1889 | if (push) { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1890 | if (nv50_vers(mast) < NVD0_DISP_CLASS) { |
Ben Skeggs | e2de179 | 2013-02-11 13:56:31 +1000 | [diff] [blame] | 1891 | u32 ctrl = (depth << 16) | (proto << 8) | owner; |
| 1892 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 1893 | ctrl |= 0x00001000; |
| 1894 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 1895 | ctrl |= 0x00002000; |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1896 | evo_mthd(push, 0x0600 + (nv_encoder->or * 0x040), 1); |
Ben Skeggs | e2de179 | 2013-02-11 13:56:31 +1000 | [diff] [blame] | 1897 | evo_data(push, ctrl); |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 1898 | } else { |
| 1899 | u32 magic = 0x31ec6000 | (nv_crtc->index << 25); |
| 1900 | u32 syncs = 0x00000001; |
| 1901 | |
| 1902 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 1903 | syncs |= 0x00000008; |
| 1904 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 1905 | syncs |= 0x00000010; |
| 1906 | |
| 1907 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 1908 | magic |= 0x00000001; |
| 1909 | |
| 1910 | evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2); |
| 1911 | evo_data(push, syncs | (depth << 6)); |
| 1912 | evo_data(push, magic); |
| 1913 | evo_mthd(push, 0x0200 + (nv_encoder->or * 0x020), 1); |
| 1914 | evo_data(push, owner | (proto << 8)); |
| 1915 | } |
| 1916 | |
| 1917 | evo_kick(push, mast); |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 1918 | } |
| 1919 | |
| 1920 | nv_encoder->crtc = encoder->crtc; |
| 1921 | } |
| 1922 | |
| 1923 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1924 | nv50_sor_destroy(struct drm_encoder *encoder) |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 1925 | { |
| 1926 | drm_encoder_cleanup(encoder); |
| 1927 | kfree(encoder); |
| 1928 | } |
| 1929 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1930 | static const struct drm_encoder_helper_funcs nv50_sor_hfunc = { |
| 1931 | .dpms = nv50_sor_dpms, |
| 1932 | .mode_fixup = nv50_sor_mode_fixup, |
Ben Skeggs | 5a885f0 | 2013-02-20 14:34:18 +1000 | [diff] [blame] | 1933 | .prepare = nv50_sor_disconnect, |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1934 | .commit = nv50_sor_commit, |
| 1935 | .mode_set = nv50_sor_mode_set, |
| 1936 | .disable = nv50_sor_disconnect, |
| 1937 | .get_crtc = nv50_display_crtc_get, |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 1938 | }; |
| 1939 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1940 | static const struct drm_encoder_funcs nv50_sor_func = { |
| 1941 | .destroy = nv50_sor_destroy, |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 1942 | }; |
| 1943 | |
| 1944 | static int |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1945 | nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 1946 | { |
Ben Skeggs | 5ed5020 | 2013-02-11 20:15:03 +1000 | [diff] [blame] | 1947 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
| 1948 | struct nouveau_i2c *i2c = nouveau_i2c(drm->device); |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 1949 | struct nouveau_encoder *nv_encoder; |
| 1950 | struct drm_encoder *encoder; |
Ben Skeggs | 5ed5020 | 2013-02-11 20:15:03 +1000 | [diff] [blame] | 1951 | int type; |
| 1952 | |
| 1953 | switch (dcbe->type) { |
| 1954 | case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; |
| 1955 | case DCB_OUTPUT_TMDS: |
| 1956 | case DCB_OUTPUT_DP: |
| 1957 | default: |
| 1958 | type = DRM_MODE_ENCODER_TMDS; |
| 1959 | break; |
| 1960 | } |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 1961 | |
| 1962 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); |
| 1963 | if (!nv_encoder) |
| 1964 | return -ENOMEM; |
| 1965 | nv_encoder->dcb = dcbe; |
| 1966 | nv_encoder->or = ffs(dcbe->or) - 1; |
Ben Skeggs | 5ed5020 | 2013-02-11 20:15:03 +1000 | [diff] [blame] | 1967 | nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index); |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 1968 | nv_encoder->last_dpms = DRM_MODE_DPMS_OFF; |
| 1969 | |
| 1970 | encoder = to_drm_encoder(nv_encoder); |
| 1971 | encoder->possible_crtcs = dcbe->heads; |
| 1972 | encoder->possible_clones = 0; |
Ben Skeggs | 5ed5020 | 2013-02-11 20:15:03 +1000 | [diff] [blame] | 1973 | drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type); |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 1974 | drm_encoder_helper_add(encoder, &nv50_sor_hfunc); |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 1975 | |
| 1976 | drm_mode_connector_attach_encoder(connector, encoder); |
| 1977 | return 0; |
| 1978 | } |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 1979 | |
| 1980 | /****************************************************************************** |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 1981 | * PIOR |
| 1982 | *****************************************************************************/ |
| 1983 | |
| 1984 | static void |
| 1985 | nv50_pior_dpms(struct drm_encoder *encoder, int mode) |
| 1986 | { |
| 1987 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 1988 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
| 1989 | u32 mthd = (nv_encoder->dcb->type << 12) | nv_encoder->or; |
| 1990 | u32 ctrl = (mode == DRM_MODE_DPMS_ON); |
| 1991 | nv_call(disp->core, NV50_DISP_PIOR_PWR + mthd, ctrl); |
| 1992 | } |
| 1993 | |
| 1994 | static bool |
| 1995 | nv50_pior_mode_fixup(struct drm_encoder *encoder, |
| 1996 | const struct drm_display_mode *mode, |
| 1997 | struct drm_display_mode *adjusted_mode) |
| 1998 | { |
| 1999 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 2000 | struct nouveau_connector *nv_connector; |
| 2001 | |
| 2002 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
| 2003 | if (nv_connector && nv_connector->native_mode) { |
| 2004 | if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { |
| 2005 | int id = adjusted_mode->base.id; |
| 2006 | *adjusted_mode = *nv_connector->native_mode; |
| 2007 | adjusted_mode->base.id = id; |
| 2008 | } |
| 2009 | } |
| 2010 | |
| 2011 | adjusted_mode->clock *= 2; |
| 2012 | return true; |
| 2013 | } |
| 2014 | |
| 2015 | static void |
| 2016 | nv50_pior_commit(struct drm_encoder *encoder) |
| 2017 | { |
| 2018 | } |
| 2019 | |
| 2020 | static void |
| 2021 | nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |
| 2022 | struct drm_display_mode *adjusted_mode) |
| 2023 | { |
| 2024 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
| 2025 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 2026 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); |
| 2027 | struct nouveau_connector *nv_connector; |
| 2028 | u8 owner = 1 << nv_crtc->index; |
| 2029 | u8 proto, depth; |
| 2030 | u32 *push; |
| 2031 | |
| 2032 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
| 2033 | switch (nv_connector->base.display_info.bpc) { |
| 2034 | case 10: depth = 0x6; break; |
| 2035 | case 8: depth = 0x5; break; |
| 2036 | case 6: depth = 0x2; break; |
| 2037 | default: depth = 0x0; break; |
| 2038 | } |
| 2039 | |
| 2040 | switch (nv_encoder->dcb->type) { |
| 2041 | case DCB_OUTPUT_TMDS: |
| 2042 | case DCB_OUTPUT_DP: |
| 2043 | proto = 0x0; |
| 2044 | break; |
| 2045 | default: |
| 2046 | BUG_ON(1); |
| 2047 | break; |
| 2048 | } |
| 2049 | |
| 2050 | nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON); |
| 2051 | |
| 2052 | push = evo_wait(mast, 8); |
| 2053 | if (push) { |
| 2054 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
| 2055 | u32 ctrl = (depth << 16) | (proto << 8) | owner; |
| 2056 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 2057 | ctrl |= 0x00001000; |
| 2058 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 2059 | ctrl |= 0x00002000; |
| 2060 | evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1); |
| 2061 | evo_data(push, ctrl); |
| 2062 | } |
| 2063 | |
| 2064 | evo_kick(push, mast); |
| 2065 | } |
| 2066 | |
| 2067 | nv_encoder->crtc = encoder->crtc; |
| 2068 | } |
| 2069 | |
| 2070 | static void |
| 2071 | nv50_pior_disconnect(struct drm_encoder *encoder) |
| 2072 | { |
| 2073 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 2074 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
| 2075 | const int or = nv_encoder->or; |
| 2076 | u32 *push; |
| 2077 | |
| 2078 | if (nv_encoder->crtc) { |
| 2079 | nv50_crtc_prepare(nv_encoder->crtc); |
| 2080 | |
| 2081 | push = evo_wait(mast, 4); |
| 2082 | if (push) { |
| 2083 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
| 2084 | evo_mthd(push, 0x0700 + (or * 0x040), 1); |
| 2085 | evo_data(push, 0x00000000); |
| 2086 | } |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 2087 | evo_kick(push, mast); |
| 2088 | } |
| 2089 | } |
| 2090 | |
| 2091 | nv_encoder->crtc = NULL; |
| 2092 | } |
| 2093 | |
| 2094 | static void |
| 2095 | nv50_pior_destroy(struct drm_encoder *encoder) |
| 2096 | { |
| 2097 | drm_encoder_cleanup(encoder); |
| 2098 | kfree(encoder); |
| 2099 | } |
| 2100 | |
| 2101 | static const struct drm_encoder_helper_funcs nv50_pior_hfunc = { |
| 2102 | .dpms = nv50_pior_dpms, |
| 2103 | .mode_fixup = nv50_pior_mode_fixup, |
| 2104 | .prepare = nv50_pior_disconnect, |
| 2105 | .commit = nv50_pior_commit, |
| 2106 | .mode_set = nv50_pior_mode_set, |
| 2107 | .disable = nv50_pior_disconnect, |
| 2108 | .get_crtc = nv50_display_crtc_get, |
| 2109 | }; |
| 2110 | |
| 2111 | static const struct drm_encoder_funcs nv50_pior_func = { |
| 2112 | .destroy = nv50_pior_destroy, |
| 2113 | }; |
| 2114 | |
| 2115 | static int |
| 2116 | nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) |
| 2117 | { |
| 2118 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
| 2119 | struct nouveau_i2c *i2c = nouveau_i2c(drm->device); |
| 2120 | struct nouveau_i2c_port *ddc = NULL; |
| 2121 | struct nouveau_encoder *nv_encoder; |
| 2122 | struct drm_encoder *encoder; |
| 2123 | int type; |
| 2124 | |
| 2125 | switch (dcbe->type) { |
| 2126 | case DCB_OUTPUT_TMDS: |
| 2127 | ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev)); |
| 2128 | type = DRM_MODE_ENCODER_TMDS; |
| 2129 | break; |
| 2130 | case DCB_OUTPUT_DP: |
| 2131 | ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev)); |
| 2132 | type = DRM_MODE_ENCODER_TMDS; |
| 2133 | break; |
| 2134 | default: |
| 2135 | return -ENODEV; |
| 2136 | } |
| 2137 | |
| 2138 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); |
| 2139 | if (!nv_encoder) |
| 2140 | return -ENOMEM; |
| 2141 | nv_encoder->dcb = dcbe; |
| 2142 | nv_encoder->or = ffs(dcbe->or) - 1; |
| 2143 | nv_encoder->i2c = ddc; |
| 2144 | |
| 2145 | encoder = to_drm_encoder(nv_encoder); |
| 2146 | encoder->possible_crtcs = dcbe->heads; |
| 2147 | encoder->possible_clones = 0; |
| 2148 | drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type); |
| 2149 | drm_encoder_helper_add(encoder, &nv50_pior_hfunc); |
| 2150 | |
| 2151 | drm_mode_connector_attach_encoder(connector, encoder); |
| 2152 | return 0; |
| 2153 | } |
| 2154 | |
| 2155 | /****************************************************************************** |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 2156 | * Init |
| 2157 | *****************************************************************************/ |
Ben Skeggs | 2a44e49 | 2011-11-09 11:36:33 +1000 | [diff] [blame] | 2158 | void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2159 | nv50_display_fini(struct drm_device *dev) |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 2160 | { |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 2161 | } |
| 2162 | |
| 2163 | int |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2164 | nv50_display_init(struct drm_device *dev) |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 2165 | { |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 2166 | struct nv50_disp *disp = nv50_disp(dev); |
| 2167 | struct drm_crtc *crtc; |
| 2168 | u32 *push; |
| 2169 | |
| 2170 | push = evo_wait(nv50_mast(dev), 32); |
| 2171 | if (!push) |
| 2172 | return -EBUSY; |
| 2173 | |
| 2174 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 2175 | struct nv50_sync *sync = nv50_sync(crtc); |
| 2176 | nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data); |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 2177 | } |
| 2178 | |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 2179 | evo_mthd(push, 0x0088, 1); |
| 2180 | evo_data(push, NvEvoSync); |
| 2181 | evo_kick(push, nv50_mast(dev)); |
| 2182 | return 0; |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 2183 | } |
| 2184 | |
| 2185 | void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2186 | nv50_display_destroy(struct drm_device *dev) |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 2187 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2188 | struct nv50_disp *disp = nv50_disp(dev); |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 2189 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2190 | nv50_dmac_destroy(disp->core, &disp->mast.base); |
Ben Skeggs | bdb8c21 | 2011-11-12 01:30:24 +1000 | [diff] [blame] | 2191 | |
Ben Skeggs | 816af2f | 2011-11-16 15:48:48 +1000 | [diff] [blame] | 2192 | nouveau_bo_unmap(disp->sync); |
Marcin Slusarz | 04c8c21 | 2012-11-25 23:04:23 +0100 | [diff] [blame] | 2193 | if (disp->sync) |
| 2194 | nouveau_bo_unpin(disp->sync); |
Ben Skeggs | 816af2f | 2011-11-16 15:48:48 +1000 | [diff] [blame] | 2195 | nouveau_bo_ref(NULL, &disp->sync); |
Ben Skeggs | 51beb42 | 2011-07-05 10:33:08 +1000 | [diff] [blame] | 2196 | |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 2197 | nouveau_display(dev)->priv = NULL; |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 2198 | kfree(disp); |
| 2199 | } |
| 2200 | |
| 2201 | int |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2202 | nv50_display_create(struct drm_device *dev) |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 2203 | { |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 2204 | struct nouveau_device *device = nouveau_dev(dev); |
| 2205 | struct nouveau_drm *drm = nouveau_drm(dev); |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 2206 | struct dcb_table *dcb = &drm->vbios.dcb; |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 2207 | struct drm_connector *connector, *tmp; |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2208 | struct nv50_disp *disp; |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 2209 | struct dcb_output *dcbe; |
Ben Skeggs | 7c5f6a8 | 2012-03-04 16:25:59 +1000 | [diff] [blame] | 2210 | int crtcs, ret, i; |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 2211 | |
| 2212 | disp = kzalloc(sizeof(*disp), GFP_KERNEL); |
| 2213 | if (!disp) |
| 2214 | return -ENOMEM; |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 2215 | |
| 2216 | nouveau_display(dev)->priv = disp; |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2217 | nouveau_display(dev)->dtor = nv50_display_destroy; |
| 2218 | nouveau_display(dev)->init = nv50_display_init; |
| 2219 | nouveau_display(dev)->fini = nv50_display_fini; |
Ben Skeggs | 2332b31 | 2014-01-22 12:58:12 +1000 | [diff] [blame] | 2220 | disp->core = nouveau_display(dev)->core; |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 2221 | |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 2222 | /* small shared memory area we use for notifiers and semaphores */ |
| 2223 | ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, |
| 2224 | 0, 0x0000, NULL, &disp->sync); |
| 2225 | if (!ret) { |
| 2226 | ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM); |
Marcin Slusarz | 04c8c21 | 2012-11-25 23:04:23 +0100 | [diff] [blame] | 2227 | if (!ret) { |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 2228 | ret = nouveau_bo_map(disp->sync); |
Marcin Slusarz | 04c8c21 | 2012-11-25 23:04:23 +0100 | [diff] [blame] | 2229 | if (ret) |
| 2230 | nouveau_bo_unpin(disp->sync); |
| 2231 | } |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 2232 | if (ret) |
| 2233 | nouveau_bo_ref(NULL, &disp->sync); |
| 2234 | } |
| 2235 | |
| 2236 | if (ret) |
| 2237 | goto out; |
| 2238 | |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 2239 | /* allocate master evo channel */ |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2240 | ret = nv50_dmac_create(disp->core, NV50_DISP_MAST_CLASS, 0, |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 2241 | &(struct nv50_display_mast_class) { |
| 2242 | .pushbuf = EVO_PUSH_HANDLE(MAST, 0), |
| 2243 | }, sizeof(struct nv50_display_mast_class), |
| 2244 | disp->sync->bo.offset, &disp->mast.base); |
| 2245 | if (ret) |
| 2246 | goto out; |
| 2247 | |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 2248 | /* create crtc objects to represent the hw heads */ |
Ben Skeggs | 63718a0 | 2012-11-16 11:44:14 +1000 | [diff] [blame] | 2249 | if (nv_mclass(disp->core) >= NVD0_DISP_CLASS) |
| 2250 | crtcs = nv_rd32(device, 0x022448); |
| 2251 | else |
| 2252 | crtcs = 2; |
| 2253 | |
Ben Skeggs | 7c5f6a8 | 2012-03-04 16:25:59 +1000 | [diff] [blame] | 2254 | for (i = 0; i < crtcs; i++) { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2255 | ret = nv50_crtc_create(dev, disp->core, i); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 2256 | if (ret) |
| 2257 | goto out; |
| 2258 | } |
| 2259 | |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 2260 | /* create encoder/connector objects based on VBIOS DCB table */ |
| 2261 | for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { |
| 2262 | connector = nouveau_connector_create(dev, dcbe->connector); |
| 2263 | if (IS_ERR(connector)) |
| 2264 | continue; |
| 2265 | |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 2266 | if (dcbe->location == DCB_LOC_ON_CHIP) { |
| 2267 | switch (dcbe->type) { |
| 2268 | case DCB_OUTPUT_TMDS: |
| 2269 | case DCB_OUTPUT_LVDS: |
| 2270 | case DCB_OUTPUT_DP: |
| 2271 | ret = nv50_sor_create(connector, dcbe); |
| 2272 | break; |
| 2273 | case DCB_OUTPUT_ANALOG: |
| 2274 | ret = nv50_dac_create(connector, dcbe); |
| 2275 | break; |
| 2276 | default: |
| 2277 | ret = -ENODEV; |
| 2278 | break; |
| 2279 | } |
| 2280 | } else { |
| 2281 | ret = nv50_pior_create(connector, dcbe); |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 2282 | } |
| 2283 | |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 2284 | if (ret) { |
| 2285 | NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", |
| 2286 | dcbe->location, dcbe->type, |
| 2287 | ffs(dcbe->or) - 1, ret); |
Ben Skeggs | 94f54f5 | 2013-03-05 22:26:06 +1000 | [diff] [blame] | 2288 | ret = 0; |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 2289 | } |
| 2290 | } |
| 2291 | |
| 2292 | /* cull any connectors we created that don't have an encoder */ |
| 2293 | list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { |
| 2294 | if (connector->encoder_ids[0]) |
| 2295 | continue; |
| 2296 | |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 2297 | NV_WARN(drm, "%s has no encoders, removing\n", |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 2298 | drm_get_connector_name(connector)); |
| 2299 | connector->funcs->destroy(connector); |
| 2300 | } |
| 2301 | |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 2302 | out: |
| 2303 | if (ret) |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2304 | nv50_display_destroy(dev); |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 2305 | return ret; |
| 2306 | } |