Thierry Reding | dec7273 | 2013-09-03 08:45:46 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 NVIDIA Corporation |
| 3 | * |
Thierry Reding | 9a2ac2d | 2014-02-11 15:52:01 +0100 | [diff] [blame] | 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
Thierry Reding | dec7273 | 2013-09-03 08:45:46 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <linux/clk.h> |
| 10 | #include <linux/debugfs.h> |
| 11 | #include <linux/host1x.h> |
| 12 | #include <linux/module.h> |
| 13 | #include <linux/of.h> |
| 14 | #include <linux/platform_device.h> |
| 15 | #include <linux/reset.h> |
| 16 | |
| 17 | #include <drm/drm_mipi_dsi.h> |
| 18 | #include <drm/drm_panel.h> |
| 19 | |
| 20 | #include <video/mipi_display.h> |
| 21 | |
| 22 | #include "dc.h" |
| 23 | #include "drm.h" |
| 24 | #include "dsi.h" |
| 25 | #include "mipi-phy.h" |
| 26 | |
| 27 | #define DSI_VIDEO_FIFO_DEPTH (1920 / 4) |
| 28 | #define DSI_HOST_FIFO_DEPTH 64 |
| 29 | |
| 30 | struct tegra_dsi { |
| 31 | struct host1x_client client; |
| 32 | struct tegra_output output; |
| 33 | struct device *dev; |
| 34 | |
| 35 | void __iomem *regs; |
| 36 | |
| 37 | struct reset_control *rst; |
| 38 | struct clk *clk_parent; |
| 39 | struct clk *clk_lp; |
| 40 | struct clk *clk; |
| 41 | |
| 42 | struct drm_info_list *debugfs_files; |
| 43 | struct drm_minor *minor; |
| 44 | struct dentry *debugfs; |
| 45 | |
| 46 | enum mipi_dsi_pixel_format format; |
| 47 | unsigned int lanes; |
| 48 | |
| 49 | struct tegra_mipi_device *mipi; |
| 50 | struct mipi_dsi_host host; |
| 51 | }; |
| 52 | |
| 53 | static inline struct tegra_dsi * |
| 54 | host1x_client_to_dsi(struct host1x_client *client) |
| 55 | { |
| 56 | return container_of(client, struct tegra_dsi, client); |
| 57 | } |
| 58 | |
| 59 | static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host) |
| 60 | { |
| 61 | return container_of(host, struct tegra_dsi, host); |
| 62 | } |
| 63 | |
| 64 | static inline struct tegra_dsi *to_dsi(struct tegra_output *output) |
| 65 | { |
| 66 | return container_of(output, struct tegra_dsi, output); |
| 67 | } |
| 68 | |
| 69 | static inline unsigned long tegra_dsi_readl(struct tegra_dsi *dsi, |
| 70 | unsigned long reg) |
| 71 | { |
| 72 | return readl(dsi->regs + (reg << 2)); |
| 73 | } |
| 74 | |
| 75 | static inline void tegra_dsi_writel(struct tegra_dsi *dsi, unsigned long value, |
| 76 | unsigned long reg) |
| 77 | { |
| 78 | writel(value, dsi->regs + (reg << 2)); |
| 79 | } |
| 80 | |
| 81 | static int tegra_dsi_show_regs(struct seq_file *s, void *data) |
| 82 | { |
| 83 | struct drm_info_node *node = s->private; |
| 84 | struct tegra_dsi *dsi = node->info_ent->data; |
| 85 | |
| 86 | #define DUMP_REG(name) \ |
| 87 | seq_printf(s, "%-32s %#05x %08lx\n", #name, name, \ |
| 88 | tegra_dsi_readl(dsi, name)) |
| 89 | |
| 90 | DUMP_REG(DSI_INCR_SYNCPT); |
| 91 | DUMP_REG(DSI_INCR_SYNCPT_CONTROL); |
| 92 | DUMP_REG(DSI_INCR_SYNCPT_ERROR); |
| 93 | DUMP_REG(DSI_CTXSW); |
| 94 | DUMP_REG(DSI_RD_DATA); |
| 95 | DUMP_REG(DSI_WR_DATA); |
| 96 | DUMP_REG(DSI_POWER_CONTROL); |
| 97 | DUMP_REG(DSI_INT_ENABLE); |
| 98 | DUMP_REG(DSI_INT_STATUS); |
| 99 | DUMP_REG(DSI_INT_MASK); |
| 100 | DUMP_REG(DSI_HOST_CONTROL); |
| 101 | DUMP_REG(DSI_CONTROL); |
| 102 | DUMP_REG(DSI_SOL_DELAY); |
| 103 | DUMP_REG(DSI_MAX_THRESHOLD); |
| 104 | DUMP_REG(DSI_TRIGGER); |
| 105 | DUMP_REG(DSI_TX_CRC); |
| 106 | DUMP_REG(DSI_STATUS); |
| 107 | |
| 108 | DUMP_REG(DSI_INIT_SEQ_CONTROL); |
| 109 | DUMP_REG(DSI_INIT_SEQ_DATA_0); |
| 110 | DUMP_REG(DSI_INIT_SEQ_DATA_1); |
| 111 | DUMP_REG(DSI_INIT_SEQ_DATA_2); |
| 112 | DUMP_REG(DSI_INIT_SEQ_DATA_3); |
| 113 | DUMP_REG(DSI_INIT_SEQ_DATA_4); |
| 114 | DUMP_REG(DSI_INIT_SEQ_DATA_5); |
| 115 | DUMP_REG(DSI_INIT_SEQ_DATA_6); |
| 116 | DUMP_REG(DSI_INIT_SEQ_DATA_7); |
| 117 | |
| 118 | DUMP_REG(DSI_PKT_SEQ_0_LO); |
| 119 | DUMP_REG(DSI_PKT_SEQ_0_HI); |
| 120 | DUMP_REG(DSI_PKT_SEQ_1_LO); |
| 121 | DUMP_REG(DSI_PKT_SEQ_1_HI); |
| 122 | DUMP_REG(DSI_PKT_SEQ_2_LO); |
| 123 | DUMP_REG(DSI_PKT_SEQ_2_HI); |
| 124 | DUMP_REG(DSI_PKT_SEQ_3_LO); |
| 125 | DUMP_REG(DSI_PKT_SEQ_3_HI); |
| 126 | DUMP_REG(DSI_PKT_SEQ_4_LO); |
| 127 | DUMP_REG(DSI_PKT_SEQ_4_HI); |
| 128 | DUMP_REG(DSI_PKT_SEQ_5_LO); |
| 129 | DUMP_REG(DSI_PKT_SEQ_5_HI); |
| 130 | |
| 131 | DUMP_REG(DSI_DCS_CMDS); |
| 132 | |
| 133 | DUMP_REG(DSI_PKT_LEN_0_1); |
| 134 | DUMP_REG(DSI_PKT_LEN_2_3); |
| 135 | DUMP_REG(DSI_PKT_LEN_4_5); |
| 136 | DUMP_REG(DSI_PKT_LEN_6_7); |
| 137 | |
| 138 | DUMP_REG(DSI_PHY_TIMING_0); |
| 139 | DUMP_REG(DSI_PHY_TIMING_1); |
| 140 | DUMP_REG(DSI_PHY_TIMING_2); |
| 141 | DUMP_REG(DSI_BTA_TIMING); |
| 142 | |
| 143 | DUMP_REG(DSI_TIMEOUT_0); |
| 144 | DUMP_REG(DSI_TIMEOUT_1); |
| 145 | DUMP_REG(DSI_TO_TALLY); |
| 146 | |
| 147 | DUMP_REG(DSI_PAD_CONTROL_0); |
| 148 | DUMP_REG(DSI_PAD_CONTROL_CD); |
| 149 | DUMP_REG(DSI_PAD_CD_STATUS); |
| 150 | DUMP_REG(DSI_VIDEO_MODE_CONTROL); |
| 151 | DUMP_REG(DSI_PAD_CONTROL_1); |
| 152 | DUMP_REG(DSI_PAD_CONTROL_2); |
| 153 | DUMP_REG(DSI_PAD_CONTROL_3); |
| 154 | DUMP_REG(DSI_PAD_CONTROL_4); |
| 155 | |
| 156 | DUMP_REG(DSI_GANGED_MODE_CONTROL); |
| 157 | DUMP_REG(DSI_GANGED_MODE_START); |
| 158 | DUMP_REG(DSI_GANGED_MODE_SIZE); |
| 159 | |
| 160 | DUMP_REG(DSI_RAW_DATA_BYTE_COUNT); |
| 161 | DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL); |
| 162 | |
| 163 | DUMP_REG(DSI_INIT_SEQ_DATA_8); |
| 164 | DUMP_REG(DSI_INIT_SEQ_DATA_9); |
| 165 | DUMP_REG(DSI_INIT_SEQ_DATA_10); |
| 166 | DUMP_REG(DSI_INIT_SEQ_DATA_11); |
| 167 | DUMP_REG(DSI_INIT_SEQ_DATA_12); |
| 168 | DUMP_REG(DSI_INIT_SEQ_DATA_13); |
| 169 | DUMP_REG(DSI_INIT_SEQ_DATA_14); |
| 170 | DUMP_REG(DSI_INIT_SEQ_DATA_15); |
| 171 | |
| 172 | #undef DUMP_REG |
| 173 | |
| 174 | return 0; |
| 175 | } |
| 176 | |
| 177 | static struct drm_info_list debugfs_files[] = { |
| 178 | { "regs", tegra_dsi_show_regs, 0, NULL }, |
| 179 | }; |
| 180 | |
| 181 | static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi, |
| 182 | struct drm_minor *minor) |
| 183 | { |
| 184 | const char *name = dev_name(dsi->dev); |
| 185 | unsigned int i; |
| 186 | int err; |
| 187 | |
| 188 | dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root); |
| 189 | if (!dsi->debugfs) |
| 190 | return -ENOMEM; |
| 191 | |
| 192 | dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), |
| 193 | GFP_KERNEL); |
| 194 | if (!dsi->debugfs_files) { |
| 195 | err = -ENOMEM; |
| 196 | goto remove; |
| 197 | } |
| 198 | |
| 199 | for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) |
| 200 | dsi->debugfs_files[i].data = dsi; |
| 201 | |
| 202 | err = drm_debugfs_create_files(dsi->debugfs_files, |
| 203 | ARRAY_SIZE(debugfs_files), |
| 204 | dsi->debugfs, minor); |
| 205 | if (err < 0) |
| 206 | goto free; |
| 207 | |
| 208 | dsi->minor = minor; |
| 209 | |
| 210 | return 0; |
| 211 | |
| 212 | free: |
| 213 | kfree(dsi->debugfs_files); |
| 214 | dsi->debugfs_files = NULL; |
| 215 | remove: |
| 216 | debugfs_remove(dsi->debugfs); |
| 217 | dsi->debugfs = NULL; |
| 218 | |
| 219 | return err; |
| 220 | } |
| 221 | |
| 222 | static int tegra_dsi_debugfs_exit(struct tegra_dsi *dsi) |
| 223 | { |
| 224 | drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files), |
| 225 | dsi->minor); |
| 226 | dsi->minor = NULL; |
| 227 | |
| 228 | kfree(dsi->debugfs_files); |
| 229 | dsi->debugfs_files = NULL; |
| 230 | |
| 231 | debugfs_remove(dsi->debugfs); |
| 232 | dsi->debugfs = NULL; |
| 233 | |
| 234 | return 0; |
| 235 | } |
| 236 | |
| 237 | #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9)) |
| 238 | #define PKT_LEN0(len) (((len) & 0x07) << 0) |
| 239 | #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19)) |
| 240 | #define PKT_LEN1(len) (((len) & 0x07) << 10) |
| 241 | #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29)) |
| 242 | #define PKT_LEN2(len) (((len) & 0x07) << 20) |
| 243 | |
| 244 | #define PKT_LP (1 << 30) |
| 245 | #define NUM_PKT_SEQ 12 |
| 246 | |
| 247 | /* non-burst mode with sync-end */ |
| 248 | static const u32 pkt_seq_vnb_syne[NUM_PKT_SEQ] = { |
| 249 | [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | |
| 250 | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | |
| 251 | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | |
| 252 | PKT_LP, |
| 253 | [ 1] = 0, |
| 254 | [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) | |
| 255 | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | |
| 256 | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | |
| 257 | PKT_LP, |
| 258 | [ 3] = 0, |
| 259 | [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | |
| 260 | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | |
| 261 | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | |
| 262 | PKT_LP, |
| 263 | [ 5] = 0, |
| 264 | [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | |
| 265 | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | |
| 266 | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), |
| 267 | [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | |
| 268 | PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | |
| 269 | PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), |
| 270 | [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | |
| 271 | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | |
| 272 | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | |
| 273 | PKT_LP, |
| 274 | [ 9] = 0, |
| 275 | [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | |
| 276 | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | |
| 277 | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), |
| 278 | [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | |
| 279 | PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | |
| 280 | PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), |
| 281 | }; |
| 282 | |
| 283 | static int tegra_dsi_set_phy_timing(struct tegra_dsi *dsi) |
| 284 | { |
| 285 | struct mipi_dphy_timing timing; |
| 286 | unsigned long value, period; |
| 287 | long rate; |
| 288 | int err; |
| 289 | |
| 290 | rate = clk_get_rate(dsi->clk); |
| 291 | if (rate < 0) |
| 292 | return rate; |
| 293 | |
| 294 | period = DIV_ROUND_CLOSEST(1000000000UL, rate * 2); |
| 295 | |
| 296 | err = mipi_dphy_timing_get_default(&timing, period); |
| 297 | if (err < 0) |
| 298 | return err; |
| 299 | |
| 300 | err = mipi_dphy_timing_validate(&timing, period); |
| 301 | if (err < 0) { |
| 302 | dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err); |
| 303 | return err; |
| 304 | } |
| 305 | |
| 306 | /* |
| 307 | * The D-PHY timing fields below are expressed in byte-clock cycles, |
| 308 | * so multiply the period by 8. |
| 309 | */ |
| 310 | period *= 8; |
| 311 | |
| 312 | value = DSI_TIMING_FIELD(timing.hsexit, period, 1) << 24 | |
| 313 | DSI_TIMING_FIELD(timing.hstrail, period, 0) << 16 | |
| 314 | DSI_TIMING_FIELD(timing.hszero, period, 3) << 8 | |
| 315 | DSI_TIMING_FIELD(timing.hsprepare, period, 1); |
| 316 | tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0); |
| 317 | |
| 318 | value = DSI_TIMING_FIELD(timing.clktrail, period, 1) << 24 | |
| 319 | DSI_TIMING_FIELD(timing.clkpost, period, 1) << 16 | |
| 320 | DSI_TIMING_FIELD(timing.clkzero, period, 1) << 8 | |
| 321 | DSI_TIMING_FIELD(timing.lpx, period, 1); |
| 322 | tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1); |
| 323 | |
| 324 | value = DSI_TIMING_FIELD(timing.clkprepare, period, 1) << 16 | |
| 325 | DSI_TIMING_FIELD(timing.clkpre, period, 1) << 8 | |
| 326 | DSI_TIMING_FIELD(0xff * period, period, 0) << 0; |
| 327 | tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2); |
| 328 | |
| 329 | value = DSI_TIMING_FIELD(timing.taget, period, 1) << 16 | |
| 330 | DSI_TIMING_FIELD(timing.tasure, period, 1) << 8 | |
| 331 | DSI_TIMING_FIELD(timing.tago, period, 1); |
| 332 | tegra_dsi_writel(dsi, value, DSI_BTA_TIMING); |
| 333 | |
| 334 | return 0; |
| 335 | } |
| 336 | |
| 337 | static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format, |
| 338 | unsigned int *mulp, unsigned int *divp) |
| 339 | { |
| 340 | switch (format) { |
| 341 | case MIPI_DSI_FMT_RGB666_PACKED: |
| 342 | case MIPI_DSI_FMT_RGB888: |
| 343 | *mulp = 3; |
| 344 | *divp = 1; |
| 345 | break; |
| 346 | |
| 347 | case MIPI_DSI_FMT_RGB565: |
| 348 | *mulp = 2; |
| 349 | *divp = 1; |
| 350 | break; |
| 351 | |
| 352 | case MIPI_DSI_FMT_RGB666: |
| 353 | *mulp = 9; |
| 354 | *divp = 4; |
| 355 | break; |
| 356 | |
| 357 | default: |
| 358 | return -EINVAL; |
| 359 | } |
| 360 | |
| 361 | return 0; |
| 362 | } |
| 363 | |
| 364 | static int tegra_output_dsi_enable(struct tegra_output *output) |
| 365 | { |
| 366 | struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); |
| 367 | struct drm_display_mode *mode = &dc->base.mode; |
| 368 | unsigned int hact, hsw, hbp, hfp, i, mul, div; |
| 369 | struct tegra_dsi *dsi = to_dsi(output); |
| 370 | /* FIXME: don't hardcode this */ |
| 371 | const u32 *pkt_seq = pkt_seq_vnb_syne; |
| 372 | unsigned long value; |
| 373 | int err; |
| 374 | |
| 375 | err = tegra_dsi_get_muldiv(dsi->format, &mul, &div); |
| 376 | if (err < 0) |
| 377 | return err; |
| 378 | |
| 379 | err = clk_enable(dsi->clk); |
| 380 | if (err < 0) |
| 381 | return err; |
| 382 | |
| 383 | reset_control_deassert(dsi->rst); |
| 384 | |
| 385 | value = DSI_CONTROL_CHANNEL(0) | DSI_CONTROL_FORMAT(dsi->format) | |
| 386 | DSI_CONTROL_LANES(dsi->lanes - 1) | |
| 387 | DSI_CONTROL_SOURCE(dc->pipe); |
| 388 | tegra_dsi_writel(dsi, value, DSI_CONTROL); |
| 389 | |
| 390 | tegra_dsi_writel(dsi, DSI_VIDEO_FIFO_DEPTH, DSI_MAX_THRESHOLD); |
| 391 | |
| 392 | value = DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS | |
| 393 | DSI_HOST_CONTROL_ECC; |
| 394 | tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); |
| 395 | |
| 396 | value = tegra_dsi_readl(dsi, DSI_CONTROL); |
| 397 | value |= DSI_CONTROL_HS_CLK_CTRL; |
| 398 | value &= ~DSI_CONTROL_TX_TRIG(3); |
| 399 | value &= ~DSI_CONTROL_DCS_ENABLE; |
| 400 | value |= DSI_CONTROL_VIDEO_ENABLE; |
| 401 | value &= ~DSI_CONTROL_HOST_ENABLE; |
| 402 | tegra_dsi_writel(dsi, value, DSI_CONTROL); |
| 403 | |
| 404 | err = tegra_dsi_set_phy_timing(dsi); |
| 405 | if (err < 0) |
| 406 | return err; |
| 407 | |
| 408 | for (i = 0; i < NUM_PKT_SEQ; i++) |
| 409 | tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i); |
| 410 | |
| 411 | /* horizontal active pixels */ |
| 412 | hact = mode->hdisplay * mul / div; |
| 413 | |
| 414 | /* horizontal sync width */ |
| 415 | hsw = (mode->hsync_end - mode->hsync_start) * mul / div; |
| 416 | hsw -= 10; |
| 417 | |
| 418 | /* horizontal back porch */ |
| 419 | hbp = (mode->htotal - mode->hsync_end) * mul / div; |
| 420 | hbp -= 14; |
| 421 | |
| 422 | /* horizontal front porch */ |
| 423 | hfp = (mode->hsync_start - mode->hdisplay) * mul / div; |
| 424 | hfp -= 8; |
| 425 | |
| 426 | tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1); |
| 427 | tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3); |
| 428 | tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5); |
| 429 | tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7); |
| 430 | |
| 431 | /* set SOL delay */ |
| 432 | tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY); |
| 433 | |
| 434 | /* enable display controller */ |
| 435 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); |
| 436 | value |= DSI_ENABLE; |
| 437 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); |
| 438 | |
Thierry Reding | dec7273 | 2013-09-03 08:45:46 +0200 | [diff] [blame] | 439 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); |
| 440 | value &= ~DISP_CTRL_MODE_MASK; |
| 441 | value |= DISP_CTRL_MODE_C_DISPLAY; |
| 442 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); |
| 443 | |
Thierry Reding | 72d3028 | 2013-12-12 11:06:55 +0100 | [diff] [blame] | 444 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); |
| 445 | value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | |
| 446 | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; |
| 447 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); |
| 448 | |
Thierry Reding | dec7273 | 2013-09-03 08:45:46 +0200 | [diff] [blame] | 449 | tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); |
| 450 | tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); |
| 451 | |
| 452 | /* enable DSI controller */ |
| 453 | value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); |
| 454 | value |= DSI_POWER_CONTROL_ENABLE; |
| 455 | tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); |
| 456 | |
| 457 | return 0; |
| 458 | } |
| 459 | |
| 460 | static int tegra_output_dsi_disable(struct tegra_output *output) |
| 461 | { |
| 462 | struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); |
| 463 | struct tegra_dsi *dsi = to_dsi(output); |
| 464 | unsigned long value; |
| 465 | |
| 466 | /* disable DSI controller */ |
| 467 | value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); |
| 468 | value &= DSI_POWER_CONTROL_ENABLE; |
| 469 | tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); |
| 470 | |
| 471 | /* |
Thierry Reding | 72d3028 | 2013-12-12 11:06:55 +0100 | [diff] [blame] | 472 | * The following accesses registers of the display controller, so make |
| 473 | * sure it's only executed when the output is attached to one. |
Thierry Reding | dec7273 | 2013-09-03 08:45:46 +0200 | [diff] [blame] | 474 | */ |
| 475 | if (dc) { |
Thierry Reding | 72d3028 | 2013-12-12 11:06:55 +0100 | [diff] [blame] | 476 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); |
| 477 | value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | |
| 478 | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); |
| 479 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); |
| 480 | |
Thierry Reding | dec7273 | 2013-09-03 08:45:46 +0200 | [diff] [blame] | 481 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); |
| 482 | value &= ~DISP_CTRL_MODE_MASK; |
| 483 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); |
| 484 | |
| 485 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); |
| 486 | value &= ~DSI_ENABLE; |
| 487 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); |
Thierry Reding | 72d3028 | 2013-12-12 11:06:55 +0100 | [diff] [blame] | 488 | |
| 489 | tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); |
| 490 | tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); |
Thierry Reding | dec7273 | 2013-09-03 08:45:46 +0200 | [diff] [blame] | 491 | } |
| 492 | |
| 493 | clk_disable(dsi->clk); |
| 494 | |
| 495 | return 0; |
| 496 | } |
| 497 | |
| 498 | static int tegra_output_dsi_setup_clock(struct tegra_output *output, |
| 499 | struct clk *clk, unsigned long pclk) |
| 500 | { |
| 501 | struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); |
| 502 | struct drm_display_mode *mode = &dc->base.mode; |
| 503 | unsigned int timeout, mul, div, vrefresh; |
| 504 | struct tegra_dsi *dsi = to_dsi(output); |
| 505 | unsigned long bclk, plld, value; |
| 506 | struct clk *base; |
| 507 | int err; |
| 508 | |
| 509 | err = tegra_dsi_get_muldiv(dsi->format, &mul, &div); |
| 510 | if (err < 0) |
| 511 | return err; |
| 512 | |
| 513 | vrefresh = drm_mode_vrefresh(mode); |
| 514 | |
| 515 | pclk = mode->htotal * mode->vtotal * vrefresh; |
| 516 | bclk = (pclk * mul) / (div * dsi->lanes); |
| 517 | plld = DIV_ROUND_UP(bclk * 8, 1000000); |
| 518 | pclk = (plld * 1000000) / 2; |
| 519 | |
| 520 | err = clk_set_parent(clk, dsi->clk_parent); |
| 521 | if (err < 0) { |
| 522 | dev_err(dsi->dev, "failed to set parent clock: %d\n", err); |
| 523 | return err; |
| 524 | } |
| 525 | |
| 526 | base = clk_get_parent(dsi->clk_parent); |
| 527 | |
| 528 | /* |
| 529 | * This assumes that the parent clock is pll_d_out0 or pll_d2_out |
| 530 | * respectively, each of which divides the base pll_d by 2. |
| 531 | */ |
| 532 | err = clk_set_rate(base, pclk * 2); |
| 533 | if (err < 0) { |
| 534 | dev_err(dsi->dev, "failed to set base clock rate to %lu Hz\n", |
| 535 | pclk * 2); |
| 536 | return err; |
| 537 | } |
| 538 | |
| 539 | /* |
| 540 | * XXX: Move the below somewhere else so that we don't need to have |
| 541 | * access to the vrefresh in this function? |
| 542 | */ |
| 543 | |
| 544 | /* one frame high-speed transmission timeout */ |
| 545 | timeout = (bclk / vrefresh) / 512; |
| 546 | value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout); |
| 547 | tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0); |
| 548 | |
| 549 | /* 2 ms peripheral timeout for panel */ |
| 550 | timeout = 2 * bclk / 512 * 1000; |
| 551 | value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000); |
| 552 | tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1); |
| 553 | |
| 554 | value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0); |
| 555 | tegra_dsi_writel(dsi, value, DSI_TO_TALLY); |
| 556 | |
| 557 | return 0; |
| 558 | } |
| 559 | |
| 560 | static int tegra_output_dsi_check_mode(struct tegra_output *output, |
| 561 | struct drm_display_mode *mode, |
| 562 | enum drm_mode_status *status) |
| 563 | { |
| 564 | /* |
| 565 | * FIXME: For now, always assume that the mode is okay. |
| 566 | */ |
| 567 | |
| 568 | *status = MODE_OK; |
| 569 | |
| 570 | return 0; |
| 571 | } |
| 572 | |
| 573 | static const struct tegra_output_ops dsi_ops = { |
| 574 | .enable = tegra_output_dsi_enable, |
| 575 | .disable = tegra_output_dsi_disable, |
| 576 | .setup_clock = tegra_output_dsi_setup_clock, |
| 577 | .check_mode = tegra_output_dsi_check_mode, |
| 578 | }; |
| 579 | |
| 580 | static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) |
| 581 | { |
| 582 | unsigned long value; |
| 583 | |
| 584 | value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0); |
| 585 | tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); |
| 586 | |
| 587 | return 0; |
| 588 | } |
| 589 | |
| 590 | static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) |
| 591 | { |
| 592 | unsigned long value; |
| 593 | |
| 594 | tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); |
| 595 | tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); |
| 596 | tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); |
| 597 | tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); |
| 598 | tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); |
| 599 | |
| 600 | /* start calibration */ |
| 601 | tegra_dsi_pad_enable(dsi); |
| 602 | |
| 603 | value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | |
| 604 | DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) | |
| 605 | DSI_PAD_OUT_CLK(0x0); |
| 606 | tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); |
| 607 | |
| 608 | return tegra_mipi_calibrate(dsi->mipi); |
| 609 | } |
| 610 | |
| 611 | static int tegra_dsi_init(struct host1x_client *client) |
| 612 | { |
| 613 | struct tegra_drm *tegra = dev_get_drvdata(client->parent); |
| 614 | struct tegra_dsi *dsi = host1x_client_to_dsi(client); |
| 615 | unsigned long value, i; |
| 616 | int err; |
| 617 | |
| 618 | dsi->output.type = TEGRA_OUTPUT_DSI; |
| 619 | dsi->output.dev = client->dev; |
| 620 | dsi->output.ops = &dsi_ops; |
| 621 | |
| 622 | err = tegra_output_init(tegra->drm, &dsi->output); |
| 623 | if (err < 0) { |
| 624 | dev_err(client->dev, "output setup failed: %d\n", err); |
| 625 | return err; |
| 626 | } |
| 627 | |
| 628 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
| 629 | err = tegra_dsi_debugfs_init(dsi, tegra->drm->primary); |
| 630 | if (err < 0) |
| 631 | dev_err(dsi->dev, "debugfs setup failed: %d\n", err); |
| 632 | } |
| 633 | |
| 634 | /* |
| 635 | * enable high-speed mode, checksum generation, ECC generation and |
| 636 | * disable raw mode |
| 637 | */ |
| 638 | value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL); |
| 639 | value |= DSI_HOST_CONTROL_ECC | DSI_HOST_CONTROL_CS | |
| 640 | DSI_HOST_CONTROL_HS; |
| 641 | value &= ~DSI_HOST_CONTROL_RAW; |
| 642 | tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); |
| 643 | |
| 644 | tegra_dsi_writel(dsi, 0, DSI_SOL_DELAY); |
| 645 | tegra_dsi_writel(dsi, 0, DSI_MAX_THRESHOLD); |
| 646 | |
| 647 | tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_CONTROL); |
| 648 | |
| 649 | for (i = 0; i < 8; i++) { |
| 650 | tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + i); |
| 651 | tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_8 + i); |
| 652 | } |
| 653 | |
| 654 | for (i = 0; i < 12; i++) |
| 655 | tegra_dsi_writel(dsi, 0, DSI_PKT_SEQ_0_LO + i); |
| 656 | |
| 657 | tegra_dsi_writel(dsi, 0, DSI_DCS_CMDS); |
| 658 | |
| 659 | err = tegra_dsi_pad_calibrate(dsi); |
| 660 | if (err < 0) { |
| 661 | dev_err(dsi->dev, "MIPI calibration failed: %d\n", err); |
| 662 | return err; |
| 663 | } |
| 664 | |
| 665 | tegra_dsi_writel(dsi, DSI_POWER_CONTROL_ENABLE, DSI_POWER_CONTROL); |
| 666 | usleep_range(300, 1000); |
| 667 | |
| 668 | return 0; |
| 669 | } |
| 670 | |
| 671 | static int tegra_dsi_exit(struct host1x_client *client) |
| 672 | { |
| 673 | struct tegra_dsi *dsi = host1x_client_to_dsi(client); |
| 674 | int err; |
| 675 | |
| 676 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
| 677 | err = tegra_dsi_debugfs_exit(dsi); |
| 678 | if (err < 0) |
| 679 | dev_err(dsi->dev, "debugfs cleanup failed: %d\n", err); |
| 680 | } |
| 681 | |
| 682 | err = tegra_output_disable(&dsi->output); |
| 683 | if (err < 0) { |
| 684 | dev_err(client->dev, "output failed to disable: %d\n", err); |
| 685 | return err; |
| 686 | } |
| 687 | |
| 688 | err = tegra_output_exit(&dsi->output); |
| 689 | if (err < 0) { |
| 690 | dev_err(client->dev, "output cleanup failed: %d\n", err); |
| 691 | return err; |
| 692 | } |
| 693 | |
| 694 | return 0; |
| 695 | } |
| 696 | |
| 697 | static const struct host1x_client_ops dsi_client_ops = { |
| 698 | .init = tegra_dsi_init, |
| 699 | .exit = tegra_dsi_exit, |
| 700 | }; |
| 701 | |
| 702 | static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi) |
| 703 | { |
| 704 | struct clk *parent; |
| 705 | int err; |
| 706 | |
| 707 | parent = clk_get_parent(dsi->clk); |
| 708 | if (!parent) |
| 709 | return -EINVAL; |
| 710 | |
| 711 | err = clk_set_parent(parent, dsi->clk_parent); |
| 712 | if (err < 0) |
| 713 | return err; |
| 714 | |
| 715 | return 0; |
| 716 | } |
| 717 | |
| 718 | static void tegra_dsi_initialize(struct tegra_dsi *dsi) |
| 719 | { |
| 720 | unsigned int i; |
| 721 | |
| 722 | tegra_dsi_writel(dsi, 0, DSI_POWER_CONTROL); |
| 723 | |
| 724 | tegra_dsi_writel(dsi, 0, DSI_INT_ENABLE); |
| 725 | tegra_dsi_writel(dsi, 0, DSI_INT_STATUS); |
| 726 | tegra_dsi_writel(dsi, 0, DSI_INT_MASK); |
| 727 | |
| 728 | tegra_dsi_writel(dsi, 0, DSI_HOST_CONTROL); |
| 729 | tegra_dsi_writel(dsi, 0, DSI_CONTROL); |
| 730 | |
| 731 | tegra_dsi_writel(dsi, 0, DSI_SOL_DELAY); |
| 732 | tegra_dsi_writel(dsi, 0, DSI_MAX_THRESHOLD); |
| 733 | |
| 734 | tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_CONTROL); |
| 735 | |
| 736 | for (i = 0; i < 8; i++) { |
| 737 | tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + i); |
| 738 | tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_8 + i); |
| 739 | } |
| 740 | |
| 741 | for (i = 0; i < 12; i++) |
| 742 | tegra_dsi_writel(dsi, 0, DSI_PKT_SEQ_0_LO + i); |
| 743 | |
| 744 | tegra_dsi_writel(dsi, 0, DSI_DCS_CMDS); |
| 745 | |
| 746 | for (i = 0; i < 4; i++) |
| 747 | tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1 + i); |
| 748 | |
| 749 | tegra_dsi_writel(dsi, 0x00000000, DSI_PHY_TIMING_0); |
| 750 | tegra_dsi_writel(dsi, 0x00000000, DSI_PHY_TIMING_1); |
| 751 | tegra_dsi_writel(dsi, 0x000000ff, DSI_PHY_TIMING_2); |
| 752 | tegra_dsi_writel(dsi, 0x00000000, DSI_BTA_TIMING); |
| 753 | |
| 754 | tegra_dsi_writel(dsi, 0, DSI_TIMEOUT_0); |
| 755 | tegra_dsi_writel(dsi, 0, DSI_TIMEOUT_1); |
| 756 | tegra_dsi_writel(dsi, 0, DSI_TO_TALLY); |
| 757 | |
| 758 | tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); |
| 759 | tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_CD); |
| 760 | tegra_dsi_writel(dsi, 0, DSI_PAD_CD_STATUS); |
| 761 | tegra_dsi_writel(dsi, 0, DSI_VIDEO_MODE_CONTROL); |
| 762 | tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); |
| 763 | tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); |
| 764 | tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); |
| 765 | tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); |
| 766 | |
| 767 | tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL); |
| 768 | tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START); |
| 769 | tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE); |
| 770 | } |
| 771 | |
| 772 | static int tegra_dsi_host_attach(struct mipi_dsi_host *host, |
| 773 | struct mipi_dsi_device *device) |
| 774 | { |
| 775 | struct tegra_dsi *dsi = host_to_tegra(host); |
| 776 | struct tegra_output *output = &dsi->output; |
| 777 | |
| 778 | dsi->format = device->format; |
| 779 | dsi->lanes = device->lanes; |
| 780 | |
| 781 | output->panel = of_drm_find_panel(device->dev.of_node); |
| 782 | if (output->panel) { |
| 783 | if (output->connector.dev) |
| 784 | drm_helper_hpd_irq_event(output->connector.dev); |
| 785 | } |
| 786 | |
| 787 | return 0; |
| 788 | } |
| 789 | |
| 790 | static int tegra_dsi_host_detach(struct mipi_dsi_host *host, |
| 791 | struct mipi_dsi_device *device) |
| 792 | { |
| 793 | struct tegra_dsi *dsi = host_to_tegra(host); |
| 794 | struct tegra_output *output = &dsi->output; |
| 795 | |
| 796 | if (output->panel && &device->dev == output->panel->dev) { |
| 797 | if (output->connector.dev) |
| 798 | drm_helper_hpd_irq_event(output->connector.dev); |
| 799 | |
| 800 | output->panel = NULL; |
| 801 | } |
| 802 | |
| 803 | return 0; |
| 804 | } |
| 805 | |
| 806 | static const struct mipi_dsi_host_ops tegra_dsi_host_ops = { |
| 807 | .attach = tegra_dsi_host_attach, |
| 808 | .detach = tegra_dsi_host_detach, |
| 809 | }; |
| 810 | |
| 811 | static int tegra_dsi_probe(struct platform_device *pdev) |
| 812 | { |
| 813 | struct tegra_dsi *dsi; |
| 814 | struct resource *regs; |
| 815 | int err; |
| 816 | |
| 817 | dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL); |
| 818 | if (!dsi) |
| 819 | return -ENOMEM; |
| 820 | |
| 821 | dsi->output.dev = dsi->dev = &pdev->dev; |
| 822 | |
| 823 | err = tegra_output_probe(&dsi->output); |
| 824 | if (err < 0) |
| 825 | return err; |
| 826 | |
| 827 | /* |
| 828 | * Assume these values by default. When a DSI peripheral driver |
| 829 | * attaches to the DSI host, the parameters will be taken from |
| 830 | * the attached device. |
| 831 | */ |
| 832 | dsi->format = MIPI_DSI_FMT_RGB888; |
| 833 | dsi->lanes = 4; |
| 834 | |
| 835 | dsi->rst = devm_reset_control_get(&pdev->dev, "dsi"); |
| 836 | if (IS_ERR(dsi->rst)) |
| 837 | return PTR_ERR(dsi->rst); |
| 838 | |
| 839 | dsi->clk = devm_clk_get(&pdev->dev, NULL); |
| 840 | if (IS_ERR(dsi->clk)) { |
| 841 | dev_err(&pdev->dev, "cannot get DSI clock\n"); |
| 842 | return PTR_ERR(dsi->clk); |
| 843 | } |
| 844 | |
| 845 | err = clk_prepare_enable(dsi->clk); |
| 846 | if (err < 0) { |
| 847 | dev_err(&pdev->dev, "cannot enable DSI clock\n"); |
| 848 | return err; |
| 849 | } |
| 850 | |
| 851 | dsi->clk_lp = devm_clk_get(&pdev->dev, "lp"); |
| 852 | if (IS_ERR(dsi->clk_lp)) { |
| 853 | dev_err(&pdev->dev, "cannot get low-power clock\n"); |
| 854 | return PTR_ERR(dsi->clk_lp); |
| 855 | } |
| 856 | |
| 857 | err = clk_prepare_enable(dsi->clk_lp); |
| 858 | if (err < 0) { |
| 859 | dev_err(&pdev->dev, "cannot enable low-power clock\n"); |
| 860 | return err; |
| 861 | } |
| 862 | |
| 863 | dsi->clk_parent = devm_clk_get(&pdev->dev, "parent"); |
| 864 | if (IS_ERR(dsi->clk_parent)) { |
| 865 | dev_err(&pdev->dev, "cannot get parent clock\n"); |
| 866 | return PTR_ERR(dsi->clk_parent); |
| 867 | } |
| 868 | |
| 869 | err = clk_prepare_enable(dsi->clk_parent); |
| 870 | if (err < 0) { |
| 871 | dev_err(&pdev->dev, "cannot enable parent clock\n"); |
| 872 | return err; |
| 873 | } |
| 874 | |
| 875 | err = tegra_dsi_setup_clocks(dsi); |
| 876 | if (err < 0) { |
| 877 | dev_err(&pdev->dev, "cannot setup clocks\n"); |
| 878 | return err; |
| 879 | } |
| 880 | |
| 881 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 882 | dsi->regs = devm_ioremap_resource(&pdev->dev, regs); |
Wei Yongjun | 85316ea | 2013-10-21 11:34:07 +0800 | [diff] [blame] | 883 | if (IS_ERR(dsi->regs)) |
| 884 | return PTR_ERR(dsi->regs); |
Thierry Reding | dec7273 | 2013-09-03 08:45:46 +0200 | [diff] [blame] | 885 | |
| 886 | tegra_dsi_initialize(dsi); |
| 887 | |
| 888 | dsi->mipi = tegra_mipi_request(&pdev->dev); |
| 889 | if (IS_ERR(dsi->mipi)) |
| 890 | return PTR_ERR(dsi->mipi); |
| 891 | |
| 892 | dsi->host.ops = &tegra_dsi_host_ops; |
| 893 | dsi->host.dev = &pdev->dev; |
| 894 | |
| 895 | err = mipi_dsi_host_register(&dsi->host); |
| 896 | if (err < 0) { |
| 897 | dev_err(&pdev->dev, "failed to register DSI host: %d\n", err); |
| 898 | return err; |
| 899 | } |
| 900 | |
| 901 | INIT_LIST_HEAD(&dsi->client.list); |
| 902 | dsi->client.ops = &dsi_client_ops; |
| 903 | dsi->client.dev = &pdev->dev; |
| 904 | |
| 905 | err = host1x_client_register(&dsi->client); |
| 906 | if (err < 0) { |
| 907 | dev_err(&pdev->dev, "failed to register host1x client: %d\n", |
| 908 | err); |
| 909 | return err; |
| 910 | } |
| 911 | |
| 912 | platform_set_drvdata(pdev, dsi); |
| 913 | |
| 914 | return 0; |
| 915 | } |
| 916 | |
| 917 | static int tegra_dsi_remove(struct platform_device *pdev) |
| 918 | { |
| 919 | struct tegra_dsi *dsi = platform_get_drvdata(pdev); |
| 920 | int err; |
| 921 | |
| 922 | err = host1x_client_unregister(&dsi->client); |
| 923 | if (err < 0) { |
| 924 | dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", |
| 925 | err); |
| 926 | return err; |
| 927 | } |
| 928 | |
| 929 | mipi_dsi_host_unregister(&dsi->host); |
| 930 | tegra_mipi_free(dsi->mipi); |
| 931 | |
| 932 | clk_disable_unprepare(dsi->clk_parent); |
| 933 | clk_disable_unprepare(dsi->clk_lp); |
| 934 | clk_disable_unprepare(dsi->clk); |
| 935 | |
| 936 | err = tegra_output_remove(&dsi->output); |
| 937 | if (err < 0) { |
| 938 | dev_err(&pdev->dev, "failed to remove output: %d\n", err); |
| 939 | return err; |
| 940 | } |
| 941 | |
| 942 | return 0; |
| 943 | } |
| 944 | |
| 945 | static const struct of_device_id tegra_dsi_of_match[] = { |
| 946 | { .compatible = "nvidia,tegra114-dsi", }, |
| 947 | { }, |
| 948 | }; |
| 949 | |
| 950 | struct platform_driver tegra_dsi_driver = { |
| 951 | .driver = { |
| 952 | .name = "tegra-dsi", |
| 953 | .of_match_table = tegra_dsi_of_match, |
| 954 | }, |
| 955 | .probe = tegra_dsi_probe, |
| 956 | .remove = tegra_dsi_remove, |
| 957 | }; |