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Paul Walmsley543d9372008-03-18 10:22:06 +02001/*
2 * linux/arch/arm/mach-omap2/clock.c
3 *
Tony Lindgrena16e9702008-03-18 11:56:39 +02004 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
6 *
7 * Contacts:
Paul Walmsley543d9372008-03-18 10:22:06 +02008 * Richard Woodruff <r-woodruff2@ti.com>
Paul Walmsley543d9372008-03-18 10:22:06 +02009 * Paul Walmsley
10 *
Paul Walmsley543d9372008-03-18 10:22:06 +020011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15#undef DEBUG
16
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/device.h>
20#include <linux/list.h>
21#include <linux/errno.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
Russell Kingfced80c2008-09-06 12:10:45 +010024#include <linux/io.h>
Russell Kingfbd3bdb2008-09-06 12:13:59 +010025#include <linux/bitops.h>
Paul Walmsley543d9372008-03-18 10:22:06 +020026
Russell Kinga09e64f2008-08-05 16:14:15 +010027#include <mach/clock.h>
Paul Walmsley333943b2008-08-19 11:08:45 +030028#include <mach/clockdomain.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010029#include <mach/sram.h>
30#include <mach/cpu.h>
Paul Walmsley543d9372008-03-18 10:22:06 +020031#include <asm/div64.h>
32
33#include "memory.h"
34#include "sdrc.h"
35#include "clock.h"
36#include "prm.h"
37#include "prm-regbits-24xx.h"
38#include "cm.h"
39#include "cm-regbits-24xx.h"
40#include "cm-regbits-34xx.h"
41
42#define MAX_CLOCK_ENABLE_WAIT 100000
43
Paul Walmsley88b8ba92008-07-03 12:24:46 +030044/* DPLL rate rounding: minimum DPLL multiplier, divider values */
45#define DPLL_MIN_MULTIPLIER 1
46#define DPLL_MIN_DIVIDER 1
47
48/* Possible error results from _dpll_test_mult */
49#define DPLL_MULT_UNDERFLOW (1 << 0)
50
51/*
52 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
53 * The higher the scale factor, the greater the risk of arithmetic overflow,
54 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
55 * must be a power of DPLL_SCALE_BASE.
56 */
57#define DPLL_SCALE_FACTOR 64
58#define DPLL_SCALE_BASE 2
59#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
60 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
61
Paul Walmsley543d9372008-03-18 10:22:06 +020062u8 cpu_mask;
63
64/*-------------------------------------------------------------------------
Paul Walmsley333943b2008-08-19 11:08:45 +030065 * OMAP2/3 specific clock functions
Paul Walmsley543d9372008-03-18 10:22:06 +020066 *-------------------------------------------------------------------------*/
67
68/**
Paul Walmsley333943b2008-08-19 11:08:45 +030069 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
70 * @clk: OMAP clock struct ptr to use
71 *
72 * Convert a clockdomain name stored in a struct clk 'clk' into a
73 * clockdomain pointer, and save it into the struct clk. Intended to be
74 * called during clk_register(). No return value.
75 */
76void omap2_init_clk_clkdm(struct clk *clk)
77{
78 struct clockdomain *clkdm;
79
80 if (!clk->clkdm_name)
81 return;
82
83 clkdm = clkdm_lookup(clk->clkdm_name);
84 if (clkdm) {
85 pr_debug("clock: associated clk %s to clkdm %s\n",
86 clk->name, clk->clkdm_name);
87 clk->clkdm = clkdm;
88 } else {
89 pr_debug("clock: could not associate clk %s to "
90 "clkdm %s\n", clk->name, clk->clkdm_name);
91 }
92}
93
94/**
Paul Walmsley543d9372008-03-18 10:22:06 +020095 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
96 * @clk: OMAP clock struct ptr to use
97 *
98 * Given a pointer to a source-selectable struct clk, read the hardware
99 * register and determine what its parent is currently set to. Update the
100 * clk->parent field with the appropriate clk ptr.
101 */
102void omap2_init_clksel_parent(struct clk *clk)
103{
104 const struct clksel *clks;
105 const struct clksel_rate *clkr;
106 u32 r, found = 0;
107
108 if (!clk->clksel)
109 return;
110
111 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
112 r >>= __ffs(clk->clksel_mask);
113
114 for (clks = clk->clksel; clks->parent && !found; clks++) {
115 for (clkr = clks->rates; clkr->div && !found; clkr++) {
116 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
117 if (clk->parent != clks->parent) {
118 pr_debug("clock: inited %s parent "
119 "to %s (was %s)\n",
120 clk->name, clks->parent->name,
121 ((clk->parent) ?
122 clk->parent->name : "NULL"));
123 clk->parent = clks->parent;
124 };
125 found = 1;
126 }
127 }
128 }
129
130 if (!found)
131 printk(KERN_ERR "clock: init parent: could not find "
132 "regval %0x for clock %s\n", r, clk->name);
133
134 return;
135}
136
137/* Returns the DPLL rate */
138u32 omap2_get_dpll_rate(struct clk *clk)
139{
140 long long dpll_clk;
141 u32 dpll_mult, dpll_div, dpll;
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300142 struct dpll_data *dd;
Paul Walmsley543d9372008-03-18 10:22:06 +0200143
144 dd = clk->dpll_data;
145 /* REVISIT: What do we return on error? */
146 if (!dd)
147 return 0;
148
149 dpll = __raw_readl(dd->mult_div1_reg);
150 dpll_mult = dpll & dd->mult_mask;
151 dpll_mult >>= __ffs(dd->mult_mask);
152 dpll_div = dpll & dd->div1_mask;
153 dpll_div >>= __ffs(dd->div1_mask);
154
155 dpll_clk = (long long)clk->parent->rate * dpll_mult;
156 do_div(dpll_clk, dpll_div + 1);
157
Paul Walmsley543d9372008-03-18 10:22:06 +0200158 return dpll_clk;
159}
160
161/*
162 * Used for clocks that have the same value as the parent clock,
163 * divided by some factor
164 */
165void omap2_fixed_divisor_recalc(struct clk *clk)
166{
167 WARN_ON(!clk->fixed_div);
168
169 clk->rate = clk->parent->rate / clk->fixed_div;
170
171 if (clk->flags & RATE_PROPAGATES)
172 propagate_rate(clk);
173}
174
175/**
176 * omap2_wait_clock_ready - wait for clock to enable
177 * @reg: physical address of clock IDLEST register
178 * @mask: value to mask against to determine if the clock is active
179 * @name: name of the clock (for printk)
180 *
181 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
182 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
183 */
184int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
185{
186 int i = 0;
187 int ena = 0;
188
189 /*
190 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
191 * 34xx reverses this, just to keep us on our toes
192 */
193 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) {
194 ena = mask;
195 } else if (cpu_mask & RATE_IN_343X) {
196 ena = 0;
197 }
198
199 /* Wait for lock */
200 while (((__raw_readl(reg) & mask) != ena) &&
201 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
202 udelay(1);
203 }
204
205 if (i < MAX_CLOCK_ENABLE_WAIT)
206 pr_debug("Clock %s stable after %d loops\n", name, i);
207 else
208 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
209 name, MAX_CLOCK_ENABLE_WAIT);
210
211
212 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
213};
214
215
216/*
217 * Note: We don't need special code here for INVERT_ENABLE
218 * for the time being since INVERT_ENABLE only applies to clocks enabled by
219 * CM_CLKEN_PLL
220 */
221static void omap2_clk_wait_ready(struct clk *clk)
222{
223 void __iomem *reg, *other_reg, *st_reg;
224 u32 bit;
225
226 /*
227 * REVISIT: This code is pretty ugly. It would be nice to generalize
228 * it and pull it into struct clk itself somehow.
229 */
230 reg = clk->enable_reg;
231 if ((((u32)reg & 0xff) >= CM_FCLKEN1) &&
232 (((u32)reg & 0xff) <= OMAP24XX_CM_FCLKEN2))
233 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
234 else if ((((u32)reg & 0xff) >= CM_ICLKEN1) &&
235 (((u32)reg & 0xff) <= OMAP24XX_CM_ICLKEN4))
236 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
237 else
238 return;
239
240 /* REVISIT: What are the appropriate exclusions for 34XX? */
241 /* No check for DSS or cam clocks */
242 if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
243 if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
244 clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
245 clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
246 return;
247 }
248
249 /* REVISIT: What are the appropriate exclusions for 34XX? */
250 /* OMAP3: ignore DSS-mod clocks */
251 if (cpu_is_omap34xx() &&
Jouni Högander1971a392008-04-14 16:06:11 +0300252 (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
253 ((((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(CORE_MOD, 0)) &&
254 clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
Paul Walmsley543d9372008-03-18 10:22:06 +0200255 return;
256
257 /* Check if both functional and interface clocks
258 * are running. */
259 bit = 1 << clk->enable_bit;
260 if (!(__raw_readl(other_reg) & bit))
261 return;
262 st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
263
264 omap2_wait_clock_ready(st_reg, bit, clk->name);
265}
266
267/* Enables clock without considering parent dependencies or use count
268 * REVISIT: Maybe change this to use clk->enable like on omap1?
269 */
270int _omap2_clk_enable(struct clk *clk)
271{
272 u32 regval32;
273
274 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
275 return 0;
276
277 if (clk->enable)
278 return clk->enable(clk);
279
Russell Kingc0fc18c52008-09-05 15:10:27 +0100280 if (unlikely(clk->enable_reg == NULL)) {
Paul Walmsley543d9372008-03-18 10:22:06 +0200281 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
282 clk->name);
283 return 0; /* REVISIT: -EINVAL */
284 }
285
286 regval32 = __raw_readl(clk->enable_reg);
287 if (clk->flags & INVERT_ENABLE)
288 regval32 &= ~(1 << clk->enable_bit);
289 else
290 regval32 |= (1 << clk->enable_bit);
291 __raw_writel(regval32, clk->enable_reg);
292 wmb();
293
294 omap2_clk_wait_ready(clk);
295
296 return 0;
297}
298
299/* Disables clock without considering parent dependencies or use count */
300void _omap2_clk_disable(struct clk *clk)
301{
302 u32 regval32;
303
304 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
305 return;
306
307 if (clk->disable) {
308 clk->disable(clk);
309 return;
310 }
311
Russell Kingc0fc18c52008-09-05 15:10:27 +0100312 if (clk->enable_reg == NULL) {
Paul Walmsley543d9372008-03-18 10:22:06 +0200313 /*
314 * 'Independent' here refers to a clock which is not
315 * controlled by its parent.
316 */
317 printk(KERN_ERR "clock: clk_disable called on independent "
318 "clock %s which has no enable_reg\n", clk->name);
319 return;
320 }
321
322 regval32 = __raw_readl(clk->enable_reg);
323 if (clk->flags & INVERT_ENABLE)
324 regval32 |= (1 << clk->enable_bit);
325 else
326 regval32 &= ~(1 << clk->enable_bit);
327 __raw_writel(regval32, clk->enable_reg);
328 wmb();
329}
330
331void omap2_clk_disable(struct clk *clk)
332{
333 if (clk->usecount > 0 && !(--clk->usecount)) {
334 _omap2_clk_disable(clk);
335 if (likely((u32)clk->parent))
336 omap2_clk_disable(clk->parent);
Paul Walmsley333943b2008-08-19 11:08:45 +0300337 if (clk->clkdm)
338 omap2_clkdm_clk_disable(clk->clkdm, clk);
339
Paul Walmsley543d9372008-03-18 10:22:06 +0200340 }
341}
342
343int omap2_clk_enable(struct clk *clk)
344{
345 int ret = 0;
346
347 if (clk->usecount++ == 0) {
348 if (likely((u32)clk->parent))
349 ret = omap2_clk_enable(clk->parent);
350
351 if (unlikely(ret != 0)) {
352 clk->usecount--;
353 return ret;
354 }
355
Paul Walmsley333943b2008-08-19 11:08:45 +0300356 if (clk->clkdm)
357 omap2_clkdm_clk_enable(clk->clkdm, clk);
358
Paul Walmsley543d9372008-03-18 10:22:06 +0200359 ret = _omap2_clk_enable(clk);
360
Paul Walmsley333943b2008-08-19 11:08:45 +0300361 if (unlikely(ret != 0)) {
362 if (clk->clkdm)
363 omap2_clkdm_clk_disable(clk->clkdm, clk);
364
365 if (clk->parent) {
366 omap2_clk_disable(clk->parent);
367 clk->usecount--;
368 }
Paul Walmsley543d9372008-03-18 10:22:06 +0200369 }
370 }
371
372 return ret;
373}
374
375/*
376 * Used for clocks that are part of CLKSEL_xyz governed clocks.
377 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
378 */
379void omap2_clksel_recalc(struct clk *clk)
380{
381 u32 div = 0;
382
383 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
384
385 div = omap2_clksel_get_divisor(clk);
386 if (div == 0)
387 return;
388
389 if (unlikely(clk->rate == clk->parent->rate / div))
390 return;
391 clk->rate = clk->parent->rate / div;
392
393 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
394
395 if (unlikely(clk->flags & RATE_PROPAGATES))
396 propagate_rate(clk);
397}
398
399/**
400 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
401 * @clk: OMAP struct clk ptr to inspect
402 * @src_clk: OMAP struct clk ptr of the parent clk to search for
403 *
404 * Scan the struct clksel array associated with the clock to find
405 * the element associated with the supplied parent clock address.
406 * Returns a pointer to the struct clksel on success or NULL on error.
407 */
408const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
409 struct clk *src_clk)
410{
411 const struct clksel *clks;
412
413 if (!clk->clksel)
414 return NULL;
415
416 for (clks = clk->clksel; clks->parent; clks++) {
417 if (clks->parent == src_clk)
418 break; /* Found the requested parent */
419 }
420
421 if (!clks->parent) {
422 printk(KERN_ERR "clock: Could not find parent clock %s in "
423 "clksel array of clock %s\n", src_clk->name,
424 clk->name);
425 return NULL;
426 }
427
428 return clks;
429}
430
431/**
432 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
433 * @clk: OMAP struct clk to use
434 * @target_rate: desired clock rate
435 * @new_div: ptr to where we should store the divisor
436 *
437 * Finds 'best' divider value in an array based on the source and target
438 * rates. The divider array must be sorted with smallest divider first.
439 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
440 * they are only settable as part of virtual_prcm set.
441 *
442 * Returns the rounded clock rate or returns 0xffffffff on error.
443 */
444u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
445 u32 *new_div)
446{
447 unsigned long test_rate;
448 const struct clksel *clks;
449 const struct clksel_rate *clkr;
450 u32 last_div = 0;
451
452 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
453 clk->name, target_rate);
454
455 *new_div = 1;
456
457 clks = omap2_get_clksel_by_parent(clk, clk->parent);
458 if (clks == NULL)
459 return ~0;
460
461 for (clkr = clks->rates; clkr->div; clkr++) {
462 if (!(clkr->flags & cpu_mask))
463 continue;
464
465 /* Sanity check */
466 if (clkr->div <= last_div)
467 printk(KERN_ERR "clock: clksel_rate table not sorted "
468 "for clock %s", clk->name);
469
470 last_div = clkr->div;
471
472 test_rate = clk->parent->rate / clkr->div;
473
474 if (test_rate <= target_rate)
475 break; /* found it */
476 }
477
478 if (!clkr->div) {
479 printk(KERN_ERR "clock: Could not find divisor for target "
480 "rate %ld for clock %s parent %s\n", target_rate,
481 clk->name, clk->parent->name);
482 return ~0;
483 }
484
485 *new_div = clkr->div;
486
487 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
488 (clk->parent->rate / clkr->div));
489
490 return (clk->parent->rate / clkr->div);
491}
492
493/**
494 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
495 * @clk: OMAP struct clk to use
496 * @target_rate: desired clock rate
497 *
498 * Compatibility wrapper for OMAP clock framework
499 * Finds best target rate based on the source clock and possible dividers.
500 * rates. The divider array must be sorted with smallest divider first.
501 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
502 * they are only settable as part of virtual_prcm set.
503 *
504 * Returns the rounded clock rate or returns 0xffffffff on error.
505 */
506long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
507{
508 u32 new_div;
509
510 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
511}
512
513
514/* Given a clock and a rate apply a clock specific rounding function */
515long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
516{
Russell Kingc0fc18c52008-09-05 15:10:27 +0100517 if (clk->round_rate != NULL)
Paul Walmsley543d9372008-03-18 10:22:06 +0200518 return clk->round_rate(clk, rate);
519
520 if (clk->flags & RATE_FIXED)
521 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
522 "on fixed-rate clock %s\n", clk->name);
523
524 return clk->rate;
525}
526
527/**
528 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
529 * @clk: OMAP struct clk to use
530 * @field_val: register field value to find
531 *
532 * Given a struct clk of a rate-selectable clksel clock, and a register field
533 * value to search for, find the corresponding clock divisor. The register
534 * field value should be pre-masked and shifted down so the LSB is at bit 0
535 * before calling. Returns 0 on error
536 */
537u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
538{
539 const struct clksel *clks;
540 const struct clksel_rate *clkr;
541
542 clks = omap2_get_clksel_by_parent(clk, clk->parent);
543 if (clks == NULL)
544 return 0;
545
546 for (clkr = clks->rates; clkr->div; clkr++) {
547 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
548 break;
549 }
550
551 if (!clkr->div) {
552 printk(KERN_ERR "clock: Could not find fieldval %d for "
553 "clock %s parent %s\n", field_val, clk->name,
554 clk->parent->name);
555 return 0;
556 }
557
558 return clkr->div;
559}
560
561/**
562 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
563 * @clk: OMAP struct clk to use
564 * @div: integer divisor to search for
565 *
566 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
567 * find the corresponding register field value. The return register value is
568 * the value before left-shifting. Returns 0xffffffff on error
569 */
570u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
571{
572 const struct clksel *clks;
573 const struct clksel_rate *clkr;
574
575 /* should never happen */
576 WARN_ON(div == 0);
577
578 clks = omap2_get_clksel_by_parent(clk, clk->parent);
579 if (clks == NULL)
580 return 0;
581
582 for (clkr = clks->rates; clkr->div; clkr++) {
583 if ((clkr->flags & cpu_mask) && (clkr->div == div))
584 break;
585 }
586
587 if (!clkr->div) {
588 printk(KERN_ERR "clock: Could not find divisor %d for "
589 "clock %s parent %s\n", div, clk->name,
590 clk->parent->name);
591 return 0;
592 }
593
594 return clkr->val;
595}
596
597/**
598 * omap2_get_clksel - find clksel register addr & field mask for a clk
599 * @clk: struct clk to use
600 * @field_mask: ptr to u32 to store the register field mask
601 *
602 * Returns the address of the clksel register upon success or NULL on error.
603 */
604void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
605{
Russell Kingc0fc18c52008-09-05 15:10:27 +0100606 if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL)))
Paul Walmsley543d9372008-03-18 10:22:06 +0200607 return NULL;
608
609 *field_mask = clk->clksel_mask;
610
611 return clk->clksel_reg;
612}
613
614/**
615 * omap2_clksel_get_divisor - get current divider applied to parent clock.
616 * @clk: OMAP struct clk to use.
617 *
618 * Returns the integer divisor upon success or 0 on error.
619 */
620u32 omap2_clksel_get_divisor(struct clk *clk)
621{
622 u32 field_mask, field_val;
623 void __iomem *div_addr;
624
625 div_addr = omap2_get_clksel(clk, &field_mask);
Russell Kingc0fc18c52008-09-05 15:10:27 +0100626 if (div_addr == NULL)
Paul Walmsley543d9372008-03-18 10:22:06 +0200627 return 0;
628
629 field_val = __raw_readl(div_addr) & field_mask;
630 field_val >>= __ffs(field_mask);
631
632 return omap2_clksel_to_divisor(clk, field_val);
633}
634
635int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
636{
637 u32 field_mask, field_val, reg_val, validrate, new_div = 0;
638 void __iomem *div_addr;
639
640 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
641 if (validrate != rate)
642 return -EINVAL;
643
644 div_addr = omap2_get_clksel(clk, &field_mask);
Russell Kingc0fc18c52008-09-05 15:10:27 +0100645 if (div_addr == NULL)
Paul Walmsley543d9372008-03-18 10:22:06 +0200646 return -EINVAL;
647
648 field_val = omap2_divisor_to_clksel(clk, new_div);
649 if (field_val == ~0)
650 return -EINVAL;
651
652 reg_val = __raw_readl(div_addr);
653 reg_val &= ~field_mask;
654 reg_val |= (field_val << __ffs(field_mask));
655 __raw_writel(reg_val, div_addr);
656 wmb();
657
658 clk->rate = clk->parent->rate / new_div;
659
660 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300661 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
662 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
Paul Walmsley543d9372008-03-18 10:22:06 +0200663 wmb();
664 }
665
666 return 0;
667}
668
669
670/* Set the clock rate for a clock source */
671int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
672{
673 int ret = -EINVAL;
674
675 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
676
677 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
678 rate table mechanism, driven by mpu_speed */
679 if (clk->flags & CONFIG_PARTICIPANT)
680 return -EINVAL;
681
682 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
Russell Kingc0fc18c52008-09-05 15:10:27 +0100683 if (clk->set_rate != NULL)
Paul Walmsley543d9372008-03-18 10:22:06 +0200684 ret = clk->set_rate(clk, rate);
685
686 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
687 propagate_rate(clk);
688
689 return ret;
690}
691
692/*
693 * Converts encoded control register address into a full address
694 * On error, *src_addr will be returned as 0.
695 */
696static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
697 struct clk *src_clk, u32 *field_mask,
698 struct clk *clk, u32 *parent_div)
699{
700 const struct clksel *clks;
701 const struct clksel_rate *clkr;
702
703 *parent_div = 0;
Russell Kingc0fc18c52008-09-05 15:10:27 +0100704 *src_addr = NULL;
Paul Walmsley543d9372008-03-18 10:22:06 +0200705
706 clks = omap2_get_clksel_by_parent(clk, src_clk);
707 if (clks == NULL)
708 return 0;
709
710 for (clkr = clks->rates; clkr->div; clkr++) {
711 if (clkr->flags & (cpu_mask | DEFAULT_RATE))
712 break; /* Found the default rate for this platform */
713 }
714
715 if (!clkr->div) {
716 printk(KERN_ERR "clock: Could not find default rate for "
717 "clock %s parent %s\n", clk->name,
718 src_clk->parent->name);
719 return 0;
720 }
721
722 /* Should never happen. Add a clksel mask to the struct clk. */
723 WARN_ON(clk->clksel_mask == 0);
724
725 *field_mask = clk->clksel_mask;
726 *src_addr = clk->clksel_reg;
727 *parent_div = clkr->div;
728
729 return clkr->val;
730}
731
732int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
733{
734 void __iomem *src_addr;
735 u32 field_val, field_mask, reg_val, parent_div;
736
737 if (unlikely(clk->flags & CONFIG_PARTICIPANT))
738 return -EINVAL;
739
740 if (!clk->clksel)
741 return -EINVAL;
742
743 field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
744 &field_mask, clk, &parent_div);
Russell Kingc0fc18c52008-09-05 15:10:27 +0100745 if (src_addr == NULL)
Paul Walmsley543d9372008-03-18 10:22:06 +0200746 return -EINVAL;
747
748 if (clk->usecount > 0)
749 _omap2_clk_disable(clk);
750
751 /* Set new source value (previous dividers if any in effect) */
752 reg_val = __raw_readl(src_addr) & ~field_mask;
753 reg_val |= (field_val << __ffs(field_mask));
754 __raw_writel(reg_val, src_addr);
755 wmb();
756
757 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
758 __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
759 wmb();
760 }
761
762 if (clk->usecount > 0)
763 _omap2_clk_enable(clk);
764
765 clk->parent = new_parent;
766
767 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
768 clk->rate = new_parent->rate;
769
770 if (parent_div > 0)
771 clk->rate /= parent_div;
772
773 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
774 clk->name, clk->parent->name, clk->rate);
775
776 if (unlikely(clk->flags & RATE_PROPAGATES))
777 propagate_rate(clk);
778
779 return 0;
780}
781
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300782/* DPLL rate rounding code */
783
784/**
785 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
786 * @clk: struct clk * of the DPLL
787 * @tolerance: maximum rate error tolerance
788 *
789 * Set the maximum DPLL rate error tolerance for the rate rounding
790 * algorithm. The rate tolerance is an attempt to balance DPLL power
791 * saving (the least divider value "n") vs. rate fidelity (the least
792 * difference between the desired DPLL target rate and the rounded
793 * rate out of the algorithm). So, increasing the tolerance is likely
794 * to decrease DPLL power consumption and increase DPLL rate error.
795 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
796 * DPLL; or 0 upon success.
797 */
798int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
799{
800 if (!clk || !clk->dpll_data)
801 return -EINVAL;
802
803 clk->dpll_data->rate_tolerance = tolerance;
804
805 return 0;
806}
807
808static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, unsigned int m, unsigned int n)
809{
810 unsigned long long num;
811
812 num = (unsigned long long)parent_rate * m;
813 do_div(num, n);
814 return num;
815}
816
817/*
818 * _dpll_test_mult - test a DPLL multiplier value
819 * @m: pointer to the DPLL m (multiplier) value under test
820 * @n: current DPLL n (divider) value under test
821 * @new_rate: pointer to storage for the resulting rounded rate
822 * @target_rate: the desired DPLL rate
823 * @parent_rate: the DPLL's parent clock rate
824 *
825 * This code tests a DPLL multiplier value, ensuring that the
826 * resulting rate will not be higher than the target_rate, and that
827 * the multiplier value itself is valid for the DPLL. Initially, the
828 * integer pointed to by the m argument should be prescaled by
829 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
830 * a non-scaled m upon return. This non-scaled m will result in a
831 * new_rate as close as possible to target_rate (but not greater than
832 * target_rate) given the current (parent_rate, n, prescaled m)
833 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
834 * non-scaled m attempted to underflow, which can allow the calling
835 * function to bail out early; or 0 upon success.
836 */
837static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
838 unsigned long target_rate,
839 unsigned long parent_rate)
840{
841 int flags = 0, carry = 0;
842
843 /* Unscale m and round if necessary */
844 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
845 carry = 1;
846 *m = (*m / DPLL_SCALE_FACTOR) + carry;
847
848 /*
849 * The new rate must be <= the target rate to avoid programming
850 * a rate that is impossible for the hardware to handle
851 */
852 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
853 if (*new_rate > target_rate) {
854 (*m)--;
855 *new_rate = 0;
856 }
857
858 /* Guard against m underflow */
859 if (*m < DPLL_MIN_MULTIPLIER) {
860 *m = DPLL_MIN_MULTIPLIER;
861 *new_rate = 0;
862 flags = DPLL_MULT_UNDERFLOW;
863 }
864
865 if (*new_rate == 0)
866 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
867
868 return flags;
869}
870
871/**
872 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
873 * @clk: struct clk * for a DPLL
874 * @target_rate: desired DPLL clock rate
875 *
876 * Given a DPLL, a desired target rate, and a rate tolerance, round
877 * the target rate to a possible, programmable rate for this DPLL.
878 * Rate tolerance is assumed to be set by the caller before this
879 * function is called. Attempts to select the minimum possible n
880 * within the tolerance to reduce power consumption. Stores the
881 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
882 * will not need to call this (expensive) function again. Returns ~0
883 * if the target rate cannot be rounded, either because the rate is
884 * too low or because the rate tolerance is set too tightly; or the
885 * rounded rate upon success.
886 */
887long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
888{
889 int m, n, r, e, scaled_max_m;
890 unsigned long scaled_rt_rp, new_rate;
891 int min_e = -1, min_e_m = -1, min_e_n = -1;
892
893 if (!clk || !clk->dpll_data)
894 return ~0;
895
896 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
897 "%ld\n", clk->name, target_rate);
898
899 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
900 scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR;
901
902 clk->dpll_data->last_rounded_rate = 0;
903
904 for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) {
905
906 /* Compute the scaled DPLL multiplier, based on the divider */
907 m = scaled_rt_rp * n;
908
909 /*
910 * Since we're counting n down, a m overflow means we can
911 * can immediately skip to the next n
912 */
913 if (m > scaled_max_m)
914 continue;
915
916 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
917 clk->parent->rate);
918
919 e = target_rate - new_rate;
920 pr_debug("clock: n = %d: m = %d: rate error is %d "
921 "(new_rate = %ld)\n", n, m, e, new_rate);
922
923 if (min_e == -1 ||
924 min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) {
925 min_e = e;
926 min_e_m = m;
927 min_e_n = n;
928
929 pr_debug("clock: found new least error %d\n", min_e);
930 }
931
932 /*
933 * Since we're counting n down, a m underflow means we
934 * can bail out completely (since as n decreases in
935 * the next iteration, there's no way that m can
936 * increase beyond the current m)
937 */
938 if (r & DPLL_MULT_UNDERFLOW)
939 break;
940 }
941
942 if (min_e < 0) {
943 pr_debug("clock: error: target rate or tolerance too low\n");
944 return ~0;
945 }
946
947 clk->dpll_data->last_rounded_m = min_e_m;
948 clk->dpll_data->last_rounded_n = min_e_n;
949 clk->dpll_data->last_rounded_rate =
950 _dpll_compute_new_rate(clk->parent->rate, min_e_m, min_e_n);
951
952 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
953 min_e, min_e_m, min_e_n);
954 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
955 clk->dpll_data->last_rounded_rate, target_rate);
956
957 return clk->dpll_data->last_rounded_rate;
958}
959
Paul Walmsley543d9372008-03-18 10:22:06 +0200960/*-------------------------------------------------------------------------
961 * Omap2 clock reset and init functions
962 *-------------------------------------------------------------------------*/
963
964#ifdef CONFIG_OMAP_RESET_CLOCKS
965void omap2_clk_disable_unused(struct clk *clk)
966{
967 u32 regval32, v;
968
969 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
970
971 regval32 = __raw_readl(clk->enable_reg);
972 if ((regval32 & (1 << clk->enable_bit)) == v)
973 return;
974
975 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
976 _omap2_clk_disable(clk);
977}
978#endif