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Paul Walmsley543d9372008-03-18 10:22:06 +02001/*
2 * linux/arch/arm/mach-omap2/clock.h
3 *
Tony Lindgrena16e9702008-03-18 11:56:39 +02004 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
6 *
7 * Contacts:
Paul Walmsley543d9372008-03-18 10:22:06 +02008 * Richard Woodruff <r-woodruff2@ti.com>
Paul Walmsley543d9372008-03-18 10:22:06 +02009 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
17#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
18
Russell Kinga09e64f2008-08-05 16:14:15 +010019#include <mach/clock.h>
Paul Walmsley543d9372008-03-18 10:22:06 +020020
Paul Walmsley88b8ba92008-07-03 12:24:46 +030021/* The maximum error between a target DPLL rate and the rounded rate in Hz */
22#define DEFAULT_DPLL_RATE_TOLERANCE 50000
23
Tony Lindgren646e3ed2008-10-06 15:49:36 +030024int omap2_clk_init(void);
Paul Walmsley543d9372008-03-18 10:22:06 +020025int omap2_clk_enable(struct clk *clk);
26void omap2_clk_disable(struct clk *clk);
27long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
28int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
29int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
Paul Walmsley88b8ba92008-07-03 12:24:46 +030030int omap2_dpll_rate_tolerance_set(struct clk *clk, unsigned int tolerance);
31long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
Paul Walmsley543d9372008-03-18 10:22:06 +020032
33#ifdef CONFIG_OMAP_RESET_CLOCKS
34void omap2_clk_disable_unused(struct clk *clk);
35#else
36#define omap2_clk_disable_unused NULL
37#endif
38
39void omap2_clksel_recalc(struct clk *clk);
Paul Walmsley333943b2008-08-19 11:08:45 +030040void omap2_init_clk_clkdm(struct clk *clk);
Paul Walmsley543d9372008-03-18 10:22:06 +020041void omap2_init_clksel_parent(struct clk *clk);
42u32 omap2_clksel_get_divisor(struct clk *clk);
43u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
44 u32 *new_div);
45u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
46u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
47void omap2_fixed_divisor_recalc(struct clk *clk);
48long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
49int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
50u32 omap2_get_dpll_rate(struct clk *clk);
51int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
Tony Lindgrenff00fcc2008-07-03 12:24:44 +030052void omap2_clk_prepare_for_reboot(void);
Paul Walmsley543d9372008-03-18 10:22:06 +020053
54extern u8 cpu_mask;
55
56/* clksel_rate data common to 24xx/343x */
57static const struct clksel_rate gpt_32k_rates[] = {
58 { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
59 { .div = 0 }
60};
61
62static const struct clksel_rate gpt_sys_rates[] = {
63 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
64 { .div = 0 }
65};
66
67static const struct clksel_rate gfx_l3_rates[] = {
68 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
69 { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
70 { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
71 { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
72 { .div = 0 }
73};
74
75
76#endif