blob: 0b4744db22ef6acd94dba1f03a6593aff44834a6 [file] [log] [blame]
Luciano Coelhof5fc0f82009-08-06 16:25:28 +03001/*
2 * This file is part of wl1271
3 *
4 * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
5 * Copyright (C) 2008-2009 Nokia Corporation
6 *
7 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25#ifndef __WL1271_H__
26#define __WL1271_H__
27
28#include <linux/mutex.h>
29#include <linux/completion.h>
30#include <linux/spinlock.h>
31#include <linux/list.h>
32#include <linux/bitops.h>
33#include <net/mac80211.h>
34
35#define DRIVER_NAME "wl1271"
36#define DRIVER_PREFIX DRIVER_NAME ": "
37
38enum {
39 DEBUG_NONE = 0,
40 DEBUG_IRQ = BIT(0),
41 DEBUG_SPI = BIT(1),
42 DEBUG_BOOT = BIT(2),
43 DEBUG_MAILBOX = BIT(3),
44 DEBUG_NETLINK = BIT(4),
45 DEBUG_EVENT = BIT(5),
46 DEBUG_TX = BIT(6),
47 DEBUG_RX = BIT(7),
48 DEBUG_SCAN = BIT(8),
49 DEBUG_CRYPT = BIT(9),
50 DEBUG_PSM = BIT(10),
51 DEBUG_MAC80211 = BIT(11),
52 DEBUG_CMD = BIT(12),
53 DEBUG_ACX = BIT(13),
54 DEBUG_ALL = ~0,
55};
56
57#define DEBUG_LEVEL (DEBUG_NONE)
58
59#define DEBUG_DUMP_LIMIT 1024
60
61#define wl1271_error(fmt, arg...) \
62 printk(KERN_ERR DRIVER_PREFIX "ERROR " fmt "\n", ##arg)
63
64#define wl1271_warning(fmt, arg...) \
65 printk(KERN_WARNING DRIVER_PREFIX "WARNING " fmt "\n", ##arg)
66
67#define wl1271_notice(fmt, arg...) \
68 printk(KERN_INFO DRIVER_PREFIX fmt "\n", ##arg)
69
70#define wl1271_info(fmt, arg...) \
71 printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg)
72
73#define wl1271_debug(level, fmt, arg...) \
74 do { \
75 if (level & DEBUG_LEVEL) \
76 printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg); \
77 } while (0)
78
79#define wl1271_dump(level, prefix, buf, len) \
80 do { \
81 if (level & DEBUG_LEVEL) \
82 print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \
83 DUMP_PREFIX_OFFSET, 16, 1, \
84 buf, \
85 min_t(size_t, len, DEBUG_DUMP_LIMIT), \
86 0); \
87 } while (0)
88
89#define wl1271_dump_ascii(level, prefix, buf, len) \
90 do { \
91 if (level & DEBUG_LEVEL) \
92 print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \
93 DUMP_PREFIX_OFFSET, 16, 1, \
94 buf, \
95 min_t(size_t, len, DEBUG_DUMP_LIMIT), \
96 true); \
97 } while (0)
98
99#define WL1271_DEFAULT_RX_CONFIG (CFG_UNI_FILTER_EN | \
100 CFG_BSSID_FILTER_EN)
101
102#define WL1271_DEFAULT_RX_FILTER (CFG_RX_RCTS_ACK | CFG_RX_PRSP_EN | \
103 CFG_RX_MGMT_EN | CFG_RX_DATA_EN | \
104 CFG_RX_CTL_EN | CFG_RX_BCN_EN | \
105 CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN)
106
Juuso Oikarinend94cd292009-10-08 21:56:25 +0300107#define WL1271_DEFAULT_BASIC_RATE_SET (ACX_RATE_MASK_ALL)
108
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300109#define WL1271_FW_NAME "wl1271-fw.bin"
110#define WL1271_NVS_NAME "wl1271-nvs.bin"
111
Juuso Oikarinen545f1da2009-10-08 21:56:23 +0300112/*
113 * FIXME: for the wl1271, a busy word count of 1 here will result in a more
114 * optimal SPI interface. There is some SPI bug however, causing RXS time outs
115 * with this mode occasionally on boot, so lets have two for now.
116 */
117#define WL1271_BUSY_WORD_CNT 2
118#define WL1271_BUSY_WORD_LEN (WL1271_BUSY_WORD_CNT * sizeof(u32))
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300119
120#define WL1271_ELP_HW_STATE_ASLEEP 0
121#define WL1271_ELP_HW_STATE_IRQ 1
122
Juuso Oikarinend94cd292009-10-08 21:56:25 +0300123#define WL1271_DEFAULT_BEACON_INT 100
124#define WL1271_DEFAULT_DTIM_PERIOD 1
125
Juuso Oikarinenbe7078c2009-10-08 21:56:26 +0300126#define ACX_TX_DESCRIPTORS 32
127
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300128enum wl1271_state {
129 WL1271_STATE_OFF,
130 WL1271_STATE_ON,
131 WL1271_STATE_PLT,
132};
133
134enum wl1271_partition_type {
135 PART_DOWN,
136 PART_WORK,
137 PART_DRPW,
138
139 PART_TABLE_LEN
140};
141
142struct wl1271_partition {
143 u32 size;
144 u32 start;
145};
146
147struct wl1271_partition_set {
148 struct wl1271_partition mem;
149 struct wl1271_partition reg;
150};
151
152struct wl1271;
153
154/* FIXME: I'm not sure about this structure name */
155struct wl1271_chip {
156 u32 id;
157 char fw_ver[21];
158};
159
160struct wl1271_stats {
161 struct acx_statistics *fw_stats;
162 unsigned long fw_stats_update;
163
164 unsigned int retry_count;
165 unsigned int excessive_retries;
166};
167
168struct wl1271_debugfs {
169 struct dentry *rootdir;
170 struct dentry *fw_statistics;
171
172 struct dentry *tx_internal_desc_overflow;
173
174 struct dentry *rx_out_of_mem;
175 struct dentry *rx_hdr_overflow;
176 struct dentry *rx_hw_stuck;
177 struct dentry *rx_dropped;
178 struct dentry *rx_fcs_err;
179 struct dentry *rx_xfr_hint_trig;
180 struct dentry *rx_path_reset;
181 struct dentry *rx_reset_counter;
182
183 struct dentry *dma_rx_requested;
184 struct dentry *dma_rx_errors;
185 struct dentry *dma_tx_requested;
186 struct dentry *dma_tx_errors;
187
188 struct dentry *isr_cmd_cmplt;
189 struct dentry *isr_fiqs;
190 struct dentry *isr_rx_headers;
191 struct dentry *isr_rx_mem_overflow;
192 struct dentry *isr_rx_rdys;
193 struct dentry *isr_irqs;
194 struct dentry *isr_tx_procs;
195 struct dentry *isr_decrypt_done;
196 struct dentry *isr_dma0_done;
197 struct dentry *isr_dma1_done;
198 struct dentry *isr_tx_exch_complete;
199 struct dentry *isr_commands;
200 struct dentry *isr_rx_procs;
201 struct dentry *isr_hw_pm_mode_changes;
202 struct dentry *isr_host_acknowledges;
203 struct dentry *isr_pci_pm;
204 struct dentry *isr_wakeups;
205 struct dentry *isr_low_rssi;
206
207 struct dentry *wep_addr_key_count;
208 struct dentry *wep_default_key_count;
209 /* skipping wep.reserved */
210 struct dentry *wep_key_not_found;
211 struct dentry *wep_decrypt_fail;
212 struct dentry *wep_packets;
213 struct dentry *wep_interrupt;
214
215 struct dentry *pwr_ps_enter;
216 struct dentry *pwr_elp_enter;
217 struct dentry *pwr_missing_bcns;
218 struct dentry *pwr_wake_on_host;
219 struct dentry *pwr_wake_on_timer_exp;
220 struct dentry *pwr_tx_with_ps;
221 struct dentry *pwr_tx_without_ps;
222 struct dentry *pwr_rcvd_beacons;
223 struct dentry *pwr_power_save_off;
224 struct dentry *pwr_enable_ps;
225 struct dentry *pwr_disable_ps;
226 struct dentry *pwr_fix_tsf_ps;
227 /* skipping cont_miss_bcns_spread for now */
228 struct dentry *pwr_rcvd_awake_beacons;
229
230 struct dentry *mic_rx_pkts;
231 struct dentry *mic_calc_failure;
232
233 struct dentry *aes_encrypt_fail;
234 struct dentry *aes_decrypt_fail;
235 struct dentry *aes_encrypt_packets;
236 struct dentry *aes_decrypt_packets;
237 struct dentry *aes_encrypt_interrupt;
238 struct dentry *aes_decrypt_interrupt;
239
240 struct dentry *event_heart_beat;
241 struct dentry *event_calibration;
242 struct dentry *event_rx_mismatch;
243 struct dentry *event_rx_mem_empty;
244 struct dentry *event_rx_pool;
245 struct dentry *event_oom_late;
246 struct dentry *event_phy_transmit_error;
247 struct dentry *event_tx_stuck;
248
249 struct dentry *ps_pspoll_timeouts;
250 struct dentry *ps_upsd_timeouts;
251 struct dentry *ps_upsd_max_sptime;
252 struct dentry *ps_upsd_max_apturn;
253 struct dentry *ps_pspoll_max_apturn;
254 struct dentry *ps_pspoll_utilization;
255 struct dentry *ps_upsd_utilization;
256
257 struct dentry *rxpipe_rx_prep_beacon_drop;
258 struct dentry *rxpipe_descr_host_int_trig_rx_data;
259 struct dentry *rxpipe_beacon_buffer_thres_host_int_trig_rx_data;
260 struct dentry *rxpipe_missed_beacon_host_int_trig_rx_data;
261 struct dentry *rxpipe_tx_xfr_host_int_trig_rx_data;
262
263 struct dentry *tx_queue_len;
264
265 struct dentry *retry_count;
266 struct dentry *excessive_retries;
267};
268
269#define NUM_TX_QUEUES 4
270#define NUM_RX_PKT_DESC 8
271
272/* FW status registers */
273struct wl1271_fw_status {
274 u32 intr;
275 u8 fw_rx_counter;
276 u8 drv_rx_counter;
277 u8 reserved;
278 u8 tx_results_counter;
279 u32 rx_pkt_descs[NUM_RX_PKT_DESC];
280 u32 tx_released_blks[NUM_TX_QUEUES];
281 u32 fw_localtime;
282 u32 padding[2];
283} __attribute__ ((packed));
284
285struct wl1271_rx_mem_pool_addr {
286 u32 addr;
287 u32 addr_extra;
288};
289
290struct wl1271 {
291 struct ieee80211_hw *hw;
292 bool mac80211_registered;
293
294 struct spi_device *spi;
295
296 void (*set_power)(bool enable);
297 int irq;
298
299 spinlock_t wl_lock;
300
301 enum wl1271_state state;
302 struct mutex mutex;
303
304 int physical_mem_addr;
305 int physical_reg_addr;
306 int virtual_mem_addr;
307 int virtual_reg_addr;
308
309 struct wl1271_chip chip;
310
311 int cmd_box_addr;
312 int event_box_addr;
313
314 u8 *fw;
315 size_t fw_len;
316 u8 *nvs;
317 size_t nvs_len;
318
319 u8 bssid[ETH_ALEN];
320 u8 mac_addr[ETH_ALEN];
321 u8 bss_type;
322 u8 ssid[IW_ESSID_MAX_SIZE + 1];
323 u8 ssid_len;
324 u8 listen_int;
325 int channel;
326
327 struct wl1271_acx_mem_map *target_mem_map;
328
329 /* Accounting for allocated / available TX blocks on HW */
330 u32 tx_blocks_freed[NUM_TX_QUEUES];
331 u32 tx_blocks_available;
332 u8 tx_results_count;
333
334 /* Transmitted TX packets counter for chipset interface */
335 int tx_packets_count;
336
337 /* Time-offset between host and chipset clocks */
338 int time_offset;
339
340 /* Session counter for the chipset */
341 int session_counter;
342
343 /* Frames scheduled for transmission, not handled yet */
344 struct sk_buff_head tx_queue;
345 bool tx_queue_stopped;
346
347 struct work_struct tx_work;
348 struct work_struct filter_work;
349
350 /* Pending TX frames */
Juuso Oikarinenbe7078c2009-10-08 21:56:26 +0300351 struct sk_buff *tx_frames[ACX_TX_DESCRIPTORS];
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300352
Juuso Oikarinenac4e4ce2009-10-08 21:56:19 +0300353 /* Security sequence number counters */
354 u8 tx_security_last_seq;
355 u16 tx_security_seq_16;
356 u32 tx_security_seq_32;
357
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300358 /* FW Rx counter */
359 u32 rx_counter;
360
361 /* Rx memory pool address */
362 struct wl1271_rx_mem_pool_addr rx_mem_pool_addr;
363
364 /* The target interrupt mask */
365 struct work_struct irq_work;
366
367 /* The mbox event mask */
368 u32 event_mask;
369
370 /* Mailbox pointers */
371 u32 mbox_ptr[2];
372
373 /* Are we currently scanning */
374 bool scanning;
375
376 /* Our association ID */
377 u16 aid;
378
Juuso Oikarinend94cd292009-10-08 21:56:25 +0300379 /* Beacon parameters */
380 u16 beacon_int;
381 u8 dtim_period;
382
383 /* currently configured rate set */
384 u32 basic_rate_set;
385
Juuso Oikarinen8a5a37a2009-10-08 21:56:24 +0300386 /* The current band */
387 enum ieee80211_band band;
388
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300389 /* Default key (for WEP) */
390 u32 default_key;
391
392 unsigned int rx_config;
393 unsigned int rx_filter;
394
395 /* is firmware in elp mode */
396 bool elp;
397
398 struct completion *elp_compl;
Juuso Oikarinen37b70a82009-10-08 21:56:21 +0300399 struct delayed_work elp_work;
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300400
401 /* we can be in psm, but not in elp, we have to differentiate */
402 bool psm;
403
404 /* PSM mode requested */
405 bool psm_requested;
406
407 /* in dBm */
408 int power_level;
409
410 struct wl1271_stats stats;
411 struct wl1271_debugfs debugfs;
412
413 u32 buffer_32;
414 u32 buffer_cmd;
Juuso Oikarinen545f1da2009-10-08 21:56:23 +0300415 u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300416 struct wl1271_rx_descriptor *rx_descriptor;
417
418 struct wl1271_fw_status *fw_status;
419 struct wl1271_tx_hw_res_if *tx_res_if;
420};
421
422int wl1271_plt_start(struct wl1271 *wl);
423int wl1271_plt_stop(struct wl1271 *wl);
424
425#define JOIN_TIMEOUT 5000 /* 5000 milliseconds to join */
426
427#define SESSION_COUNTER_MAX 7 /* maximum value for the session counter */
428
429#define WL1271_DEFAULT_POWER_LEVEL 0
430
431#define WL1271_TX_QUEUE_MAX_LENGTH 20
432
433/* WL1271 needs a 200ms sleep after power on */
434#define WL1271_POWER_ON_SLEEP 200 /* in miliseconds */
435
436#endif