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gerrit-public.fairphone.software / kernel / msm-4.9 / befc229c0e1aef9fd14948c12ca9dbad47958d9d / . / drivers / net / ethernet / intel / i40evf / i40e_adminq_cmd.h
blob: 6e617669c326256295e4c283c1781e6681ed2bdd [file] [log] [blame]
Greg Rosed358aa92013-12-21 06:13:11 +0000[diff] [blame]1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * The full GNU General Public License is included in this distribution in
16 * the file called "COPYING".
17 *
18 * Contact Information:
19 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
20 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
21 *
22 ******************************************************************************/
23
24#ifndef _I40E_ADMINQ_CMD_H_
25#define _I40E_ADMINQ_CMD_H_
26
27/* This header file defines the i40e Admin Queue commands and is shared between
28 * i40e Firmware and Software.
29 *
30 * This file needs to comply with the Linux Kernel coding style.
31 */
32
33#define I40E_FW_API_VERSION_MAJOR 0x0001
34#define I40E_FW_API_VERSION_MINOR 0x0001
Greg Rose90327e72013-12-21 06:13:21 +0000[diff] [blame]35#define I40E_FW_API_VERSION_A0_MINOR 0x0000
Greg Rosed358aa92013-12-21 06:13:11 +0000[diff] [blame]36
37struct i40e_aq_desc {
38 __le16 flags;
39 __le16 opcode;
40 __le16 datalen;
41 __le16 retval;
42 __le32 cookie_high;
43 __le32 cookie_low;
44 union {
45 struct {
46 __le32 param0;
47 __le32 param1;
48 __le32 param2;
49 __le32 param3;
50 } internal;
51 struct {
52 __le32 param0;
53 __le32 param1;
54 __le32 addr_high;
55 __le32 addr_low;
56 } external;
57 u8 raw[16];
58 } params;
59};
60
61/* Flags sub-structure
62 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
63 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
64 */
65
66/* command flags and offsets*/
67#define I40E_AQ_FLAG_DD_SHIFT 0
68#define I40E_AQ_FLAG_CMP_SHIFT 1
69#define I40E_AQ_FLAG_ERR_SHIFT 2
70#define I40E_AQ_FLAG_VFE_SHIFT 3
71#define I40E_AQ_FLAG_LB_SHIFT 9
72#define I40E_AQ_FLAG_RD_SHIFT 10
73#define I40E_AQ_FLAG_VFC_SHIFT 11
74#define I40E_AQ_FLAG_BUF_SHIFT 12
75#define I40E_AQ_FLAG_SI_SHIFT 13
76#define I40E_AQ_FLAG_EI_SHIFT 14
77#define I40E_AQ_FLAG_FE_SHIFT 15
78
79#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
80#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
81#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
82#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
83#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
84#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
85#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
86#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
87#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
88#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
89#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
90
91/* error codes */
92enum i40e_admin_queue_err {
93 I40E_AQ_RC_OK = 0, /* success */
94 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
95 I40E_AQ_RC_ENOENT = 2, /* No such element */
96 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
97 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
98 I40E_AQ_RC_EIO = 5, /* I/O error */
99 I40E_AQ_RC_ENXIO = 6, /* No such resource */
100 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
101 I40E_AQ_RC_EAGAIN = 8, /* Try again */
102 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
103 I40E_AQ_RC_EACCES = 10, /* Permission denied */
104 I40E_AQ_RC_EFAULT = 11, /* Bad address */
105 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
106 I40E_AQ_RC_EEXIST = 13, /* object already exists */
107 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
108 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
109 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
110 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
111 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
112 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed because of prev cmd error */
113 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
114 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
115 I40E_AQ_RC_EFBIG = 22, /* File too large */
116};
117
118/* Admin Queue command opcodes */
119enum i40e_admin_queue_opc {
120 /* aq commands */
121 i40e_aqc_opc_get_version = 0x0001,
122 i40e_aqc_opc_driver_version = 0x0002,
123 i40e_aqc_opc_queue_shutdown = 0x0003,
124
125 /* resource ownership */
126 i40e_aqc_opc_request_resource = 0x0008,
127 i40e_aqc_opc_release_resource = 0x0009,
128
129 i40e_aqc_opc_list_func_capabilities = 0x000A,
130 i40e_aqc_opc_list_dev_capabilities = 0x000B,
131
132 i40e_aqc_opc_set_cppm_configuration = 0x0103,
133 i40e_aqc_opc_set_arp_proxy_entry = 0x0104,
134 i40e_aqc_opc_set_ns_proxy_entry = 0x0105,
135
136 /* LAA */
137 i40e_aqc_opc_mng_laa = 0x0106, /* AQ obsolete */
138 i40e_aqc_opc_mac_address_read = 0x0107,
139 i40e_aqc_opc_mac_address_write = 0x0108,
140
141 /* PXE */
142 i40e_aqc_opc_clear_pxe_mode = 0x0110,
143
144 /* internal switch commands */
145 i40e_aqc_opc_get_switch_config = 0x0200,
146 i40e_aqc_opc_add_statistics = 0x0201,
147 i40e_aqc_opc_remove_statistics = 0x0202,
148 i40e_aqc_opc_set_port_parameters = 0x0203,
149 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
150
151 i40e_aqc_opc_add_vsi = 0x0210,
152 i40e_aqc_opc_update_vsi_parameters = 0x0211,
153 i40e_aqc_opc_get_vsi_parameters = 0x0212,
154
155 i40e_aqc_opc_add_pv = 0x0220,
156 i40e_aqc_opc_update_pv_parameters = 0x0221,
157 i40e_aqc_opc_get_pv_parameters = 0x0222,
158
159 i40e_aqc_opc_add_veb = 0x0230,
160 i40e_aqc_opc_update_veb_parameters = 0x0231,
161 i40e_aqc_opc_get_veb_parameters = 0x0232,
162
163 i40e_aqc_opc_delete_element = 0x0243,
164
165 i40e_aqc_opc_add_macvlan = 0x0250,
166 i40e_aqc_opc_remove_macvlan = 0x0251,
167 i40e_aqc_opc_add_vlan = 0x0252,
168 i40e_aqc_opc_remove_vlan = 0x0253,
169 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
170 i40e_aqc_opc_add_tag = 0x0255,
171 i40e_aqc_opc_remove_tag = 0x0256,
172 i40e_aqc_opc_add_multicast_etag = 0x0257,
173 i40e_aqc_opc_remove_multicast_etag = 0x0258,
174 i40e_aqc_opc_update_tag = 0x0259,
175 i40e_aqc_opc_add_control_packet_filter = 0x025A,
176 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
177 i40e_aqc_opc_add_cloud_filters = 0x025C,
178 i40e_aqc_opc_remove_cloud_filters = 0x025D,
179
180 i40e_aqc_opc_add_mirror_rule = 0x0260,
181 i40e_aqc_opc_delete_mirror_rule = 0x0261,
182
Greg Rosed358aa92013-12-21 06:13:11 +0000[diff] [blame]183 /* DCB commands */
184 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
185 i40e_aqc_opc_dcb_updated = 0x0302,
186
187 /* TX scheduler */
188 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
189 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
190 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
191 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
192 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
193 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
194
195 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
196 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
197 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
198 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
199 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
200 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
201 i40e_aqc_opc_query_port_ets_config = 0x0419,
202 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
203 i40e_aqc_opc_suspend_port_tx = 0x041B,
204 i40e_aqc_opc_resume_port_tx = 0x041C,
Shannon Nelsonbefc2292014-03-14 07:32:23 +0000[diff] [blame^]205 i40e_aqc_opc_configure_partition_bw = 0x041D,
Greg Rosed358aa92013-12-21 06:13:11 +0000[diff] [blame]206
207 /* hmc */
208 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
209 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
210
211 /* phy commands*/
212 i40e_aqc_opc_get_phy_abilities = 0x0600,
213 i40e_aqc_opc_set_phy_config = 0x0601,
214 i40e_aqc_opc_set_mac_config = 0x0603,
215 i40e_aqc_opc_set_link_restart_an = 0x0605,
216 i40e_aqc_opc_get_link_status = 0x0607,
217 i40e_aqc_opc_set_phy_int_mask = 0x0613,
218 i40e_aqc_opc_get_local_advt_reg = 0x0614,
219 i40e_aqc_opc_set_local_advt_reg = 0x0615,
220 i40e_aqc_opc_get_partner_advt = 0x0616,
221 i40e_aqc_opc_set_lb_modes = 0x0618,
222 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
223 i40e_aqc_opc_set_phy_reset = 0x0622,
224 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
225
226 /* NVM commands */
227 i40e_aqc_opc_nvm_read = 0x0701,
228 i40e_aqc_opc_nvm_erase = 0x0702,
229 i40e_aqc_opc_nvm_update = 0x0703,
230
231 /* virtualization commands */
232 i40e_aqc_opc_send_msg_to_pf = 0x0801,
233 i40e_aqc_opc_send_msg_to_vf = 0x0802,
234 i40e_aqc_opc_send_msg_to_peer = 0x0803,
235
236 /* alternate structure */
237 i40e_aqc_opc_alternate_write = 0x0900,
238 i40e_aqc_opc_alternate_write_indirect = 0x0901,
239 i40e_aqc_opc_alternate_read = 0x0902,
240 i40e_aqc_opc_alternate_read_indirect = 0x0903,
241 i40e_aqc_opc_alternate_write_done = 0x0904,
242 i40e_aqc_opc_alternate_set_mode = 0x0905,
243 i40e_aqc_opc_alternate_clear_port = 0x0906,
244
245 /* LLDP commands */
246 i40e_aqc_opc_lldp_get_mib = 0x0A00,
247 i40e_aqc_opc_lldp_update_mib = 0x0A01,
248 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
249 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
250 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
251 i40e_aqc_opc_lldp_stop = 0x0A05,
252 i40e_aqc_opc_lldp_start = 0x0A06,
253
254 /* Tunnel commands */
255 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
256 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
257 i40e_aqc_opc_tunnel_key_structure = 0x0B10,
258
259 /* Async Events */
260 i40e_aqc_opc_event_lan_overflow = 0x1001,
261
262 /* OEM commands */
263 i40e_aqc_opc_oem_parameter_change = 0xFE00,
264 i40e_aqc_opc_oem_device_status_change = 0xFE01,
265
266 /* debug commands */
267 i40e_aqc_opc_debug_get_deviceid = 0xFF00,
268 i40e_aqc_opc_debug_set_mode = 0xFF01,
269 i40e_aqc_opc_debug_read_reg = 0xFF03,
270 i40e_aqc_opc_debug_write_reg = 0xFF04,
271 i40e_aqc_opc_debug_read_reg_sg = 0xFF05,
272 i40e_aqc_opc_debug_write_reg_sg = 0xFF06,
273 i40e_aqc_opc_debug_modify_reg = 0xFF07,
274 i40e_aqc_opc_debug_dump_internals = 0xFF08,
275 i40e_aqc_opc_debug_modify_internals = 0xFF09,
276};
277
278/* command structures and indirect data structures */
279
280/* Structure naming conventions:
281 * - no suffix for direct command descriptor structures
282 * - _data for indirect sent data
283 * - _resp for indirect return data (data which is both will use _data)
284 * - _completion for direct return data
285 * - _element_ for repeated elements (may also be _data or _resp)
286 *
287 * Command structures are expected to overlay the params.raw member of the basic
288 * descriptor, and as such cannot exceed 16 bytes in length.
289 */
290
291/* This macro is used to generate a compilation error if a structure
292 * is not exactly the correct length. It gives a divide by zero error if the
293 * structure is not of the correct size, otherwise it creates an enum that is
294 * never used.
295 */
296#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
297 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
298
299/* This macro is used extensively to ensure that command structures are 16
300 * bytes in length as they have to map to the raw array of that size.
301 */
302#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
303
304/* internal (0x00XX) commands */
305
306/* Get version (direct 0x0001) */
307struct i40e_aqc_get_version {
308 __le32 rom_ver;
309 __le32 fw_build;
310 __le16 fw_major;
311 __le16 fw_minor;
312 __le16 api_major;
313 __le16 api_minor;
314};
315
316I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
317
318/* Send driver version (indirect 0x0002) */
319struct i40e_aqc_driver_version {
320 u8 driver_major_ver;
321 u8 driver_minor_ver;
322 u8 driver_build_ver;
323 u8 driver_subbuild_ver;
324 u8 reserved[4];
325 __le32 address_high;
326 __le32 address_low;
327};
328
329I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
330
331/* Queue Shutdown (direct 0x0003) */
332struct i40e_aqc_queue_shutdown {
333 __le32 driver_unloading;
334#define I40E_AQ_DRIVER_UNLOADING 0x1
335 u8 reserved[12];
336};
337
338I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
339
340/* Request resource ownership (direct 0x0008)
341 * Release resource ownership (direct 0x0009)
342 */
343#define I40E_AQ_RESOURCE_NVM 1
344#define I40E_AQ_RESOURCE_SDP 2
345#define I40E_AQ_RESOURCE_ACCESS_READ 1
346#define I40E_AQ_RESOURCE_ACCESS_WRITE 2
347#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
348#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
349
350struct i40e_aqc_request_resource {
351 __le16 resource_id;
352 __le16 access_type;
353 __le32 timeout;
354 __le32 resource_number;
355 u8 reserved[4];
356};
357
358I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
359
360/* Get function capabilities (indirect 0x000A)
361 * Get device capabilities (indirect 0x000B)
362 */
363struct i40e_aqc_list_capabilites {
364 u8 command_flags;
365#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
366 u8 pf_index;
367 u8 reserved[2];
368 __le32 count;
369 __le32 addr_high;
370 __le32 addr_low;
371};
372
373I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
374
375struct i40e_aqc_list_capabilities_element_resp {
376 __le16 id;
377 u8 major_rev;
378 u8 minor_rev;
379 __le32 number;
380 __le32 logical_id;
381 __le32 phys_id;
382 u8 reserved[16];
383};
384
385/* list of caps */
386
387#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
388#define I40E_AQ_CAP_ID_MNG_MODE 0x0002
389#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
390#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
391#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
392#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
393#define I40E_AQ_CAP_ID_SRIOV 0x0012
394#define I40E_AQ_CAP_ID_VF 0x0013
395#define I40E_AQ_CAP_ID_VMDQ 0x0014
396#define I40E_AQ_CAP_ID_8021QBG 0x0015
397#define I40E_AQ_CAP_ID_8021QBR 0x0016
398#define I40E_AQ_CAP_ID_VSI 0x0017
399#define I40E_AQ_CAP_ID_DCB 0x0018
400#define I40E_AQ_CAP_ID_FCOE 0x0021
401#define I40E_AQ_CAP_ID_RSS 0x0040
402#define I40E_AQ_CAP_ID_RXQ 0x0041
403#define I40E_AQ_CAP_ID_TXQ 0x0042
404#define I40E_AQ_CAP_ID_MSIX 0x0043
405#define I40E_AQ_CAP_ID_VF_MSIX 0x0044
406#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
407#define I40E_AQ_CAP_ID_1588 0x0046
408#define I40E_AQ_CAP_ID_IWARP 0x0051
409#define I40E_AQ_CAP_ID_LED 0x0061
410#define I40E_AQ_CAP_ID_SDP 0x0062
411#define I40E_AQ_CAP_ID_MDIO 0x0063
412#define I40E_AQ_CAP_ID_FLEX10 0x00F1
413#define I40E_AQ_CAP_ID_CEM 0x00F2
414
415/* Set CPPM Configuration (direct 0x0103) */
416struct i40e_aqc_cppm_configuration {
417 __le16 command_flags;
418#define I40E_AQ_CPPM_EN_LTRC 0x0800
419#define I40E_AQ_CPPM_EN_DMCTH 0x1000
420#define I40E_AQ_CPPM_EN_DMCTLX 0x2000
421#define I40E_AQ_CPPM_EN_HPTC 0x4000
422#define I40E_AQ_CPPM_EN_DMARC 0x8000
423 __le16 ttlx;
424 __le32 dmacr;
425 __le16 dmcth;
426 u8 hptc;
427 u8 reserved;
428 __le32 pfltrc;
429};
430
431I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
432
433/* Set ARP Proxy command / response (indirect 0x0104) */
434struct i40e_aqc_arp_proxy_data {
435 __le16 command_flags;
436#define I40E_AQ_ARP_INIT_IPV4 0x0008
437#define I40E_AQ_ARP_UNSUP_CTL 0x0010
438#define I40E_AQ_ARP_ENA 0x0020
439#define I40E_AQ_ARP_ADD_IPV4 0x0040
440#define I40E_AQ_ARP_DEL_IPV4 0x0080
441 __le16 table_id;
442 __le32 pfpm_proxyfc;
443 __le32 ip_addr;
444 u8 mac_addr[6];
445};
446
447/* Set NS Proxy Table Entry Command (indirect 0x0105) */
448struct i40e_aqc_ns_proxy_data {
449 __le16 table_idx_mac_addr_0;
450 __le16 table_idx_mac_addr_1;
451 __le16 table_idx_ipv6_0;
452 __le16 table_idx_ipv6_1;
453 __le16 control;
454#define I40E_AQ_NS_PROXY_ADD_0 0x0100
455#define I40E_AQ_NS_PROXY_DEL_0 0x0200
456#define I40E_AQ_NS_PROXY_ADD_1 0x0400
457#define I40E_AQ_NS_PROXY_DEL_1 0x0800
458#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
459#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
460#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
461#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
462#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
463#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
464#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
465 u8 mac_addr_0[6];
466 u8 mac_addr_1[6];
467 u8 local_mac_addr[6];
468 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
469 u8 ipv6_addr_1[16];
470};
471
472/* Manage LAA Command (0x0106) - obsolete */
473struct i40e_aqc_mng_laa {
474 __le16 command_flags;
475#define I40E_AQ_LAA_FLAG_WR 0x8000
476 u8 reserved[2];
477 __le32 sal;
478 __le16 sah;
479 u8 reserved2[6];
480};
481
482/* Manage MAC Address Read Command (indirect 0x0107) */
483struct i40e_aqc_mac_address_read {
484 __le16 command_flags;
485#define I40E_AQC_LAN_ADDR_VALID 0x10
486#define I40E_AQC_SAN_ADDR_VALID 0x20
487#define I40E_AQC_PORT_ADDR_VALID 0x40
488#define I40E_AQC_WOL_ADDR_VALID 0x80
489#define I40E_AQC_ADDR_VALID_MASK 0xf0
490 u8 reserved[6];
491 __le32 addr_high;
492 __le32 addr_low;
493};
494
495I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
496
497struct i40e_aqc_mac_address_read_data {
498 u8 pf_lan_mac[6];
499 u8 pf_san_mac[6];
500 u8 port_mac[6];
501 u8 pf_wol_mac[6];
502};
503
504I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
505
506/* Manage MAC Address Write Command (0x0108) */
507struct i40e_aqc_mac_address_write {
508 __le16 command_flags;
509#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
510#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
511#define I40E_AQC_WRITE_TYPE_PORT 0x8000
512#define I40E_AQC_WRITE_TYPE_MASK 0xc000
513 __le16 mac_sah;
514 __le32 mac_sal;
515 u8 reserved[8];
516};
517
518I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
519
520/* PXE commands (0x011x) */
521
522/* Clear PXE Command and response (direct 0x0110) */
523struct i40e_aqc_clear_pxe {
524 u8 rx_cnt;
525 u8 reserved[15];
526};
527
528I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
529
530/* Switch configuration commands (0x02xx) */
531
532/* Used by many indirect commands that only pass an seid and a buffer in the
533 * command
534 */
535struct i40e_aqc_switch_seid {
536 __le16 seid;
537 u8 reserved[6];
538 __le32 addr_high;
539 __le32 addr_low;
540};
541
542I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
543
544/* Get Switch Configuration command (indirect 0x0200)
545 * uses i40e_aqc_switch_seid for the descriptor
546 */
547struct i40e_aqc_get_switch_config_header_resp {
548 __le16 num_reported;
549 __le16 num_total;
550 u8 reserved[12];
551};
552
553struct i40e_aqc_switch_config_element_resp {
554 u8 element_type;
555#define I40E_AQ_SW_ELEM_TYPE_MAC 1
556#define I40E_AQ_SW_ELEM_TYPE_PF 2
557#define I40E_AQ_SW_ELEM_TYPE_VF 3
558#define I40E_AQ_SW_ELEM_TYPE_EMP 4
559#define I40E_AQ_SW_ELEM_TYPE_BMC 5
560#define I40E_AQ_SW_ELEM_TYPE_PV 16
561#define I40E_AQ_SW_ELEM_TYPE_VEB 17
562#define I40E_AQ_SW_ELEM_TYPE_PA 18
563#define I40E_AQ_SW_ELEM_TYPE_VSI 19
564 u8 revision;
565#define I40E_AQ_SW_ELEM_REV_1 1
566 __le16 seid;
567 __le16 uplink_seid;
568 __le16 downlink_seid;
569 u8 reserved[3];
570 u8 connection_type;
571#define I40E_AQ_CONN_TYPE_REGULAR 0x1
572#define I40E_AQ_CONN_TYPE_DEFAULT 0x2
573#define I40E_AQ_CONN_TYPE_CASCADED 0x3
574 __le16 scheduler_id;
575 __le16 element_info;
576};
577
578/* Get Switch Configuration (indirect 0x0200)
579 * an array of elements are returned in the response buffer
580 * the first in the array is the header, remainder are elements
581 */
582struct i40e_aqc_get_switch_config_resp {
583 struct i40e_aqc_get_switch_config_header_resp header;
584 struct i40e_aqc_switch_config_element_resp element[1];
585};
586
587/* Add Statistics (direct 0x0201)
588 * Remove Statistics (direct 0x0202)
589 */
590struct i40e_aqc_add_remove_statistics {
591 __le16 seid;
592 __le16 vlan;
593 __le16 stat_index;
594 u8 reserved[10];
595};
596
597I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
598
599/* Set Port Parameters command (direct 0x0203) */
600struct i40e_aqc_set_port_parameters {
601 __le16 command_flags;
602#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
603#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
604#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
605 __le16 bad_frame_vsi;
606 __le16 default_seid; /* reserved for command */
607 u8 reserved[10];
608};
609
610I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
611
612/* Get Switch Resource Allocation (indirect 0x0204) */
613struct i40e_aqc_get_switch_resource_alloc {
614 u8 num_entries; /* reserved for command */
615 u8 reserved[7];
616 __le32 addr_high;
617 __le32 addr_low;
618};
619
620I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
621
622/* expect an array of these structs in the response buffer */
623struct i40e_aqc_switch_resource_alloc_element_resp {
624 u8 resource_type;
625#define I40E_AQ_RESOURCE_TYPE_VEB 0x0
626#define I40E_AQ_RESOURCE_TYPE_VSI 0x1
627#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
628#define I40E_AQ_RESOURCE_TYPE_STAG 0x3
629#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
630#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
631#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
632#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
633#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
634#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
635#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
636#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
637#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
638#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
639#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
640#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
641#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
642#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
643#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
644 u8 reserved1;
645 __le16 guaranteed;
646 __le16 total;
647 __le16 used;
648 __le16 total_unalloced;
649 u8 reserved2[6];
650};
651
652/* Add VSI (indirect 0x0210)
653 * this indirect command uses struct i40e_aqc_vsi_properties_data
654 * as the indirect buffer (128 bytes)
655 *
656 * Update VSI (indirect 0x211)
657 * uses the same data structure as Add VSI
658 *
659 * Get VSI (indirect 0x0212)
660 * uses the same completion and data structure as Add VSI
661 */
662struct i40e_aqc_add_get_update_vsi {
663 __le16 uplink_seid;
664 u8 connection_type;
665#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
666#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
667#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
668 u8 reserved1;
669 u8 vf_id;
670 u8 reserved2;
671 __le16 vsi_flags;
672#define I40E_AQ_VSI_TYPE_SHIFT 0x0
673#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
674#define I40E_AQ_VSI_TYPE_VF 0x0
675#define I40E_AQ_VSI_TYPE_VMDQ2 0x1
676#define I40E_AQ_VSI_TYPE_PF 0x2
677#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
678#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
679#define I40E_AQ_VSI_FLAG_CLOUD_VSI 0x8
680 __le32 addr_high;
681 __le32 addr_low;
682};
683
684I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
685
686struct i40e_aqc_add_get_update_vsi_completion {
687 __le16 seid;
688 __le16 vsi_number;
689 __le16 vsi_used;
690 __le16 vsi_free;
691 __le32 addr_high;
692 __le32 addr_low;
693};
694
695I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
696
697struct i40e_aqc_vsi_properties_data {
698 /* first 96 byte are written by SW */
699 __le16 valid_sections;
700#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
701#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
702#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
703#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
704#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
705#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
706#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
707#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
708#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
709#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
710 /* switch section */
711 __le16 switch_id; /* 12bit id combined with flags below */
712#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
713#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
714#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
715#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
716#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
717 u8 sw_reserved[2];
718 /* security section */
719 u8 sec_flags;
720#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
721#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
722#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
723 u8 sec_reserved;
724 /* VLAN section */
725 __le16 pvid; /* VLANS include priority bits */
726 __le16 fcoe_pvid;
727 u8 port_vlan_flags;
728#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
729#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
730 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
731#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
732#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
733#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
734#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
735#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
736#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
737 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
738#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
739#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
740#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
741#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
742 u8 pvlan_reserved[3];
743 /* ingress egress up sections */
744 __le32 ingress_table; /* bitmap, 3 bits per up */
745#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
746#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
747 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
748#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
749#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
750 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
751#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
752#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
753 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
754#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
755#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
756 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
757#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
758#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
759 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
760#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
761#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
762 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
763#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
764#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
765 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
766#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
767#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
768 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
769 __le32 egress_table; /* same defines as for ingress table */
770 /* cascaded PV section */
771 __le16 cas_pv_tag;
772 u8 cas_pv_flags;
773#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
774#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
775 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
776#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
777#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
778#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
779#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
780#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
781#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
782 u8 cas_pv_reserved;
783 /* queue mapping section */
784 __le16 mapping_flags;
785#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
786#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
787 __le16 queue_mapping[16];
788#define I40E_AQ_VSI_QUEUE_SHIFT 0x0
789#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
790 __le16 tc_mapping[8];
791#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
792#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
793 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
794#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
795#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
796 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
797 /* queueing option section */
798 u8 queueing_opt_flags;
799#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
800#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
801 u8 queueing_opt_reserved[3];
802 /* scheduler section */
803 u8 up_enable_bits;
804 u8 sched_reserved;
805 /* outer up section */
806 __le32 outer_up_table; /* same structure and defines as ingress table */
807 u8 cmd_reserved[8];
808 /* last 32 bytes are written by FW */
809 __le16 qs_handle[8];
810#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
811 __le16 stat_counter_idx;
812 __le16 sched_id;
813 u8 resp_reserved[12];
814};
815
816I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
817
818/* Add Port Virtualizer (direct 0x0220)
819 * also used for update PV (direct 0x0221) but only flags are used
820 * (IS_CTRL_PORT only works on add PV)
821 */
822struct i40e_aqc_add_update_pv {
823 __le16 command_flags;
824#define I40E_AQC_PV_FLAG_PV_TYPE 0x1
825#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
826#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
827#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
828 __le16 uplink_seid;
829 __le16 connected_seid;
830 u8 reserved[10];
831};
832
833I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
834
835struct i40e_aqc_add_update_pv_completion {
836 /* reserved for update; for add also encodes error if rc == ENOSPC */
837 __le16 pv_seid;
838#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
839#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
840#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
841#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
842 u8 reserved[14];
843};
844
845I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
846
847/* Get PV Params (direct 0x0222)
848 * uses i40e_aqc_switch_seid for the descriptor
849 */
850
851struct i40e_aqc_get_pv_params_completion {
852 __le16 seid;
853 __le16 default_stag;
854 __le16 pv_flags; /* same flags as add_pv */
855#define I40E_AQC_GET_PV_PV_TYPE 0x1
856#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
857#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
858 u8 reserved[8];
859 __le16 default_port_seid;
860};
861
862I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
863
864/* Add VEB (direct 0x0230) */
865struct i40e_aqc_add_veb {
866 __le16 uplink_seid;
867 __le16 downlink_seid;
868 __le16 veb_flags;
869#define I40E_AQC_ADD_VEB_FLOATING 0x1
870#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
871#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
872 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
873#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
874#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
875#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8
876 u8 enable_tcs;
877 u8 reserved[9];
878};
879
880I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
881
882struct i40e_aqc_add_veb_completion {
883 u8 reserved[6];
884 __le16 switch_seid;
885 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
886 __le16 veb_seid;
887#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
888#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
889#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
890#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
891 __le16 statistic_index;
892 __le16 vebs_used;
893 __le16 vebs_free;
894};
895
896I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
897
898/* Get VEB Parameters (direct 0x0232)
899 * uses i40e_aqc_switch_seid for the descriptor
900 */
901struct i40e_aqc_get_veb_parameters_completion {
902 __le16 seid;
903 __le16 switch_id;
904 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
905 __le16 statistic_index;
906 __le16 vebs_used;
907 __le16 vebs_free;
908 u8 reserved[4];
909};
910
911I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
912
913/* Delete Element (direct 0x0243)
914 * uses the generic i40e_aqc_switch_seid
915 */
916
917/* Add MAC-VLAN (indirect 0x0250) */
918
919/* used for the command for most vlan commands */
920struct i40e_aqc_macvlan {
921 __le16 num_addresses;
922 __le16 seid[3];
923#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
924#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
925 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
926#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
927 __le32 addr_high;
928 __le32 addr_low;
929};
930
931I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
932
933/* indirect data for command and response */
934struct i40e_aqc_add_macvlan_element_data {
935 u8 mac_addr[6];
936 __le16 vlan_tag;
937 __le16 flags;
938#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
939#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
940#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
941#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
942 __le16 queue_number;
943#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
944#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
945 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
946 /* response section */
947 u8 match_method;
948#define I40E_AQC_MM_PERFECT_MATCH 0x01
949#define I40E_AQC_MM_HASH_MATCH 0x02
950#define I40E_AQC_MM_ERR_NO_RES 0xFF
951 u8 reserved1[3];
952};
953
954struct i40e_aqc_add_remove_macvlan_completion {
955 __le16 perfect_mac_used;
956 __le16 perfect_mac_free;
957 __le16 unicast_hash_free;
958 __le16 multicast_hash_free;
959 __le32 addr_high;
960 __le32 addr_low;
961};
962
963I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
964
965/* Remove MAC-VLAN (indirect 0x0251)
966 * uses i40e_aqc_macvlan for the descriptor
967 * data points to an array of num_addresses of elements
968 */
969
970struct i40e_aqc_remove_macvlan_element_data {
971 u8 mac_addr[6];
972 __le16 vlan_tag;
973 u8 flags;
974#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
975#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
976#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
977#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
978 u8 reserved[3];
979 /* reply section */
980 u8 error_code;
981#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
982#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
983 u8 reply_reserved[3];
984};
985
986/* Add VLAN (indirect 0x0252)
987 * Remove VLAN (indirect 0x0253)
988 * use the generic i40e_aqc_macvlan for the command
989 */
990struct i40e_aqc_add_remove_vlan_element_data {
991 __le16 vlan_tag;
992 u8 vlan_flags;
993/* flags for add VLAN */
994#define I40E_AQC_ADD_VLAN_LOCAL 0x1
995#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
996#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << \
997 I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
998#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
999#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1000#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1001#define I40E_AQC_VLAN_PTYPE_SHIFT 3
1002#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1003#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1004#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1005#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1006#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1007/* flags for remove VLAN */
1008#define I40E_AQC_REMOVE_VLAN_ALL 0x1
1009 u8 reserved;
1010 u8 result;
1011/* flags for add VLAN */
1012#define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1013#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1014#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1015/* flags for remove VLAN */
1016#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1017#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1018 u8 reserved1[3];
1019};
1020
1021struct i40e_aqc_add_remove_vlan_completion {
1022 u8 reserved[4];
1023 __le16 vlans_used;
1024 __le16 vlans_free;
1025 __le32 addr_high;
1026 __le32 addr_low;
1027};
1028
1029/* Set VSI Promiscuous Modes (direct 0x0254) */
1030struct i40e_aqc_set_vsi_promiscuous_modes {
1031 __le16 promiscuous_flags;
1032 __le16 valid_flags;
1033/* flags used for both fields above */
1034#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1035#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1036#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1037#define I40E_AQC_SET_VSI_DEFAULT 0x08
1038#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1039 __le16 seid;
1040#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1041 u8 reserved[10];
1042};
1043
1044I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1045
1046/* Add S/E-tag command (direct 0x0255)
1047 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1048 */
1049struct i40e_aqc_add_tag {
1050 __le16 flags;
1051#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1052 __le16 seid;
1053#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1054#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1055 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1056 __le16 tag;
1057 __le16 queue_number;
1058 u8 reserved[8];
1059};
1060
1061I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1062
1063struct i40e_aqc_add_remove_tag_completion {
1064 u8 reserved[12];
1065 __le16 tags_used;
1066 __le16 tags_free;
1067};
1068
1069I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1070
1071/* Remove S/E-tag command (direct 0x0256)
1072 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1073 */
1074struct i40e_aqc_remove_tag {
1075 __le16 seid;
1076#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1077#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1078 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1079 __le16 tag;
1080 u8 reserved[12];
1081};
1082
1083/* Add multicast E-Tag (direct 0x0257)
1084 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1085 * and no external data
1086 */
1087struct i40e_aqc_add_remove_mcast_etag {
1088 __le16 pv_seid;
1089 __le16 etag;
1090 u8 num_unicast_etags;
1091 u8 reserved[3];
1092 __le32 addr_high; /* address of array of 2-byte s-tags */
1093 __le32 addr_low;
1094};
1095
1096I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1097
1098struct i40e_aqc_add_remove_mcast_etag_completion {
1099 u8 reserved[4];
1100 __le16 mcast_etags_used;
1101 __le16 mcast_etags_free;
1102 __le32 addr_high;
1103 __le32 addr_low;
1104
1105};
1106
1107I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1108
1109/* Update S/E-Tag (direct 0x0259) */
1110struct i40e_aqc_update_tag {
1111 __le16 seid;
1112#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1113#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1114 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1115 __le16 old_tag;
1116 __le16 new_tag;
1117 u8 reserved[10];
1118};
1119
1120I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1121
1122struct i40e_aqc_update_tag_completion {
1123 u8 reserved[12];
1124 __le16 tags_used;
1125 __le16 tags_free;
1126};
1127
1128I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1129
1130/* Add Control Packet filter (direct 0x025A)
1131 * Remove Control Packet filter (direct 0x025B)
1132 * uses the i40e_aqc_add_oveb_cloud,
1133 * and the generic direct completion structure
1134 */
1135struct i40e_aqc_add_remove_control_packet_filter {
1136 u8 mac[6];
1137 __le16 etype;
1138 __le16 flags;
1139#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1140#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1141#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1142#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1143#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1144 __le16 seid;
1145#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1146#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1147 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1148 __le16 queue;
1149 u8 reserved[2];
1150};
1151
1152I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1153
1154struct i40e_aqc_add_remove_control_packet_filter_completion {
1155 __le16 mac_etype_used;
1156 __le16 etype_used;
1157 __le16 mac_etype_free;
1158 __le16 etype_free;
1159 u8 reserved[8];
1160};
1161
1162I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1163
1164/* Add Cloud filters (indirect 0x025C)
1165 * Remove Cloud filters (indirect 0x025D)
1166 * uses the i40e_aqc_add_remove_cloud_filters,
1167 * and the generic indirect completion structure
1168 */
1169struct i40e_aqc_add_remove_cloud_filters {
1170 u8 num_filters;
1171 u8 reserved;
1172 __le16 seid;
1173#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1174#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1175 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1176 u8 reserved2[4];
1177 __le32 addr_high;
1178 __le32 addr_low;
1179};
1180
1181I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1182
1183struct i40e_aqc_add_remove_cloud_filters_element_data {
1184 u8 outer_mac[6];
1185 u8 inner_mac[6];
1186 __le16 inner_vlan;
1187 union {
1188 struct {
1189 u8 reserved[12];
1190 u8 data[4];
1191 } v4;
1192 struct {
1193 u8 data[16];
1194 } v6;
1195 } ipaddr;
1196 __le16 flags;
1197#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1198#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1199 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
Greg Rose90327e72013-12-21 06:13:21 +0000[diff] [blame]1200#define I40E_AQC_ADD_CLOUD_FILTER_OIP_GRE 0x0002
1201#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_GRE 0x0004
1202#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_VNL 0x0007
Greg Rosed358aa92013-12-21 06:13:11 +0000[diff] [blame]1203/* 0x0000 reserved */
1204#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1205/* 0x0002 reserved */
1206#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1207#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1208/* 0x0005 reserved */
1209#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1210/* 0x0007 reserved */
1211/* 0x0008 reserved */
1212#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1213#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1214#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1215#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1216
1217#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1218#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1219#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1220#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1221#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1222
1223#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1224#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1225#define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0
1226#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1227#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2
1228#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1229
Mitch A Williams821bd3e2014-02-20 19:29:14 -0800[diff] [blame]1230 __le32 tenant_id;
Greg Rosed358aa92013-12-21 06:13:11 +0000[diff] [blame]1231 u8 reserved[4];
1232 __le16 queue_number;
1233#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1234#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x3F << \
1235 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1236 u8 reserved2[14];
1237 /* response section */
1238 u8 allocation_result;
1239#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1240#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1241 u8 response_reserved[7];
1242};
1243
1244struct i40e_aqc_remove_cloud_filters_completion {
1245 __le16 perfect_ovlan_used;
1246 __le16 perfect_ovlan_free;
1247 __le16 vlan_used;
1248 __le16 vlan_free;
1249 __le32 addr_high;
1250 __le32 addr_low;
1251};
1252
1253I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1254
1255/* Add Mirror Rule (indirect or direct 0x0260)
1256 * Delete Mirror Rule (indirect or direct 0x0261)
1257 * note: some rule types (4,5) do not use an external buffer.
1258 * take care to set the flags correctly.
1259 */
1260struct i40e_aqc_add_delete_mirror_rule {
1261 __le16 seid;
1262 __le16 rule_type;
1263#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1264#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1265 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1266#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1267#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1268#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1269#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1270#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1271 __le16 num_entries;
1272 __le16 destination; /* VSI for add, rule id for delete */
1273 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1274 __le32 addr_low;
1275};
1276
1277I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1278
1279struct i40e_aqc_add_delete_mirror_rule_completion {
1280 u8 reserved[2];
1281 __le16 rule_id; /* only used on add */
1282 __le16 mirror_rules_used;
1283 __le16 mirror_rules_free;
1284 __le32 addr_high;
1285 __le32 addr_low;
1286};
1287
1288I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1289
Greg Rosed358aa92013-12-21 06:13:11 +0000[diff] [blame]1290/* DCB 0x03xx*/
1291
1292/* PFC Ignore (direct 0x0301)
1293 * the command and response use the same descriptor structure
1294 */
1295struct i40e_aqc_pfc_ignore {
1296 u8 tc_bitmap;
1297 u8 command_flags; /* unused on response */
1298#define I40E_AQC_PFC_IGNORE_SET 0x80
1299#define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1300 u8 reserved[14];
1301};
1302
1303I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1304
1305/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1306 * with no parameters
1307 */
1308
1309/* TX scheduler 0x04xx */
1310
1311/* Almost all the indirect commands use
1312 * this generic struct to pass the SEID in param0
1313 */
1314struct i40e_aqc_tx_sched_ind {
1315 __le16 vsi_seid;
1316 u8 reserved[6];
1317 __le32 addr_high;
1318 __le32 addr_low;
1319};
1320
1321I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1322
1323/* Several commands respond with a set of queue set handles */
1324struct i40e_aqc_qs_handles_resp {
1325 __le16 qs_handles[8];
1326};
1327
1328/* Configure VSI BW limits (direct 0x0400) */
1329struct i40e_aqc_configure_vsi_bw_limit {
1330 __le16 vsi_seid;
1331 u8 reserved[2];
1332 __le16 credit;
1333 u8 reserved1[2];
1334 u8 max_credit; /* 0-3, limit = 2^max */
1335 u8 reserved2[7];
1336};
1337
1338I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1339
1340/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1341 * responds with i40e_aqc_qs_handles_resp
1342 */
1343struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1344 u8 tc_valid_bits;
1345 u8 reserved[15];
1346 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1347
1348 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1349 __le16 tc_bw_max[2];
1350 u8 reserved1[28];
1351};
1352
1353/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1354 * responds with i40e_aqc_qs_handles_resp
1355 */
1356struct i40e_aqc_configure_vsi_tc_bw_data {
1357 u8 tc_valid_bits;
1358 u8 reserved[3];
1359 u8 tc_bw_credits[8];
1360 u8 reserved1[4];
1361 __le16 qs_handles[8];
1362};
1363
1364/* Query vsi bw configuration (indirect 0x0408) */
1365struct i40e_aqc_query_vsi_bw_config_resp {
1366 u8 tc_valid_bits;
1367 u8 tc_suspended_bits;
1368 u8 reserved[14];
1369 __le16 qs_handles[8];
1370 u8 reserved1[4];
1371 __le16 port_bw_limit;
1372 u8 reserved2[2];
1373 u8 max_bw; /* 0-3, limit = 2^max */
1374 u8 reserved3[23];
1375};
1376
1377/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1378struct i40e_aqc_query_vsi_ets_sla_config_resp {
1379 u8 tc_valid_bits;
1380 u8 reserved[3];
1381 u8 share_credits[8];
1382 __le16 credits[8];
1383
1384 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1385 __le16 tc_bw_max[2];
1386};
1387
1388/* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1389struct i40e_aqc_configure_switching_comp_bw_limit {
1390 __le16 seid;
1391 u8 reserved[2];
1392 __le16 credit;
1393 u8 reserved1[2];
1394 u8 max_bw; /* 0-3, limit = 2^max */
1395 u8 reserved2[7];
1396};
1397
1398I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1399
1400/* Enable Physical Port ETS (indirect 0x0413)
1401 * Modify Physical Port ETS (indirect 0x0414)
1402 * Disable Physical Port ETS (indirect 0x0415)
1403 */
1404struct i40e_aqc_configure_switching_comp_ets_data {
1405 u8 reserved[4];
1406 u8 tc_valid_bits;
1407 u8 reserved1;
1408 u8 tc_strict_priority_flags;
1409 u8 reserved2[17];
1410 u8 tc_bw_share_credits[8];
1411 u8 reserved3[96];
1412};
1413
1414/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1415struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1416 u8 tc_valid_bits;
1417 u8 reserved[15];
1418 __le16 tc_bw_credit[8];
1419
1420 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1421 __le16 tc_bw_max[2];
1422 u8 reserved1[28];
1423};
1424
1425/* Configure Switching Component Bandwidth Allocation per Tc
1426 * (indirect 0x0417)
1427 */
1428struct i40e_aqc_configure_switching_comp_bw_config_data {
1429 u8 tc_valid_bits;
1430 u8 reserved[2];
1431 u8 absolute_credits; /* bool */
1432 u8 tc_bw_share_credits[8];
1433 u8 reserved1[20];
1434};
1435
1436/* Query Switching Component Configuration (indirect 0x0418) */
1437struct i40e_aqc_query_switching_comp_ets_config_resp {
1438 u8 tc_valid_bits;
1439 u8 reserved[35];
1440 __le16 port_bw_limit;
1441 u8 reserved1[2];
1442 u8 tc_bw_max; /* 0-3, limit = 2^max */
1443 u8 reserved2[23];
1444};
1445
1446/* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1447struct i40e_aqc_query_port_ets_config_resp {
1448 u8 reserved[4];
1449 u8 tc_valid_bits;
1450 u8 reserved1;
1451 u8 tc_strict_priority_bits;
1452 u8 reserved2;
1453 u8 tc_bw_share_credits[8];
1454 __le16 tc_bw_limits[8];
1455
1456 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1457 __le16 tc_bw_max[2];
1458 u8 reserved3[32];
1459};
1460
1461/* Query Switching Component Bandwidth Allocation per Traffic Type
1462 * (indirect 0x041A)
1463 */
1464struct i40e_aqc_query_switching_comp_bw_config_resp {
1465 u8 tc_valid_bits;
1466 u8 reserved[2];
1467 u8 absolute_credits_enable; /* bool */
1468 u8 tc_bw_share_credits[8];
1469 __le16 tc_bw_limits[8];
1470
1471 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1472 __le16 tc_bw_max[2];
1473};
1474
1475/* Suspend/resume port TX traffic
1476 * (direct 0x041B and 0x041C) uses the generic SEID struct
1477 */
1478
Shannon Nelsonbefc2292014-03-14 07:32:23 +0000[diff] [blame^]1479/* Configure partition BW
1480 * (indirect 0x041D)
1481 */
1482struct i40e_aqc_configure_partition_bw_data {
1483 __le16 pf_valid_bits;
1484 u8 min_bw[16]; /* guaranteed bandwidth */
1485 u8 max_bw[16]; /* bandwidth limit */
1486};
1487
Greg Rosed358aa92013-12-21 06:13:11 +0000[diff] [blame]1488/* Get and set the active HMC resource profile and status.
1489 * (direct 0x0500) and (direct 0x0501)
1490 */
1491struct i40e_aq_get_set_hmc_resource_profile {
1492 u8 pm_profile;
1493 u8 pe_vf_enabled;
1494 u8 reserved[14];
1495};
1496
1497I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1498
1499enum i40e_aq_hmc_profile {
1500 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1501 I40E_HMC_PROFILE_DEFAULT = 1,
1502 I40E_HMC_PROFILE_FAVOR_VF = 2,
1503 I40E_HMC_PROFILE_EQUAL = 3,
1504};
1505
1506#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF
1507#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F
1508
1509/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1510
1511/* set in param0 for get phy abilities to report qualified modules */
1512#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1513#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1514
1515enum i40e_aq_phy_type {
1516 I40E_PHY_TYPE_SGMII = 0x0,
1517 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1518 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1519 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1520 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1521 I40E_PHY_TYPE_XAUI = 0x5,
1522 I40E_PHY_TYPE_XFI = 0x6,
1523 I40E_PHY_TYPE_SFI = 0x7,
1524 I40E_PHY_TYPE_XLAUI = 0x8,
1525 I40E_PHY_TYPE_XLPPI = 0x9,
1526 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1527 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1528 I40E_PHY_TYPE_100BASE_TX = 0x11,
1529 I40E_PHY_TYPE_1000BASE_T = 0x12,
1530 I40E_PHY_TYPE_10GBASE_T = 0x13,
1531 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1532 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1533 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1534 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1535 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1536 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1537 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1538 I40E_PHY_TYPE_20GBASE_KR2 = 0x1B,
1539 I40E_PHY_TYPE_MAX
1540};
1541
1542#define I40E_LINK_SPEED_100MB_SHIFT 0x1
1543#define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1544#define I40E_LINK_SPEED_10GB_SHIFT 0x3
1545#define I40E_LINK_SPEED_40GB_SHIFT 0x4
1546#define I40E_LINK_SPEED_20GB_SHIFT 0x5
1547
1548enum i40e_aq_link_speed {
1549 I40E_LINK_SPEED_UNKNOWN = 0,
1550 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1551 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1552 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1553 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1554 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT)
1555};
1556
1557struct i40e_aqc_module_desc {
1558 u8 oui[3];
1559 u8 reserved1;
1560 u8 part_number[16];
1561 u8 revision[4];
1562 u8 reserved2[8];
1563};
1564
1565struct i40e_aq_get_phy_abilities_resp {
1566 __le32 phy_type; /* bitmap using the above enum for offsets */
1567 u8 link_speed; /* bitmap using the above enum bit patterns */
1568 u8 abilities;
1569#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1570#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1571#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
Shannon Nelsonbefc2292014-03-14 07:32:23 +0000[diff] [blame^]1572#define I40E_AQ_PHY_LINK_ENABLED 0x08
1573#define I40E_AQ_PHY_AN_ENABLED 0x10
Greg Rosed358aa92013-12-21 06:13:11 +0000[diff] [blame]1574#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1575 __le16 eee_capability;
1576#define I40E_AQ_EEE_100BASE_TX 0x0002
1577#define I40E_AQ_EEE_1000BASE_T 0x0004
1578#define I40E_AQ_EEE_10GBASE_T 0x0008
1579#define I40E_AQ_EEE_1000BASE_KX 0x0010
1580#define I40E_AQ_EEE_10GBASE_KX4 0x0020
1581#define I40E_AQ_EEE_10GBASE_KR 0x0040
1582 __le32 eeer_val;
1583 u8 d3_lpan;
1584#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1585 u8 reserved[3];
1586 u8 phy_id[4];
1587 u8 module_type[3];
1588 u8 qualified_module_count;
1589#define I40E_AQ_PHY_MAX_QMS 16
1590 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1591};
1592
1593/* Set PHY Config (direct 0x0601) */
1594struct i40e_aq_set_phy_config { /* same bits as above in all */
1595 __le32 phy_type;
1596 u8 link_speed;
1597 u8 abilities;
1598/* bits 0-2 use the values from get_phy_abilities_resp */
1599#define I40E_AQ_PHY_ENABLE_LINK 0x08
1600#define I40E_AQ_PHY_ENABLE_AN 0x10
1601#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1602 __le16 eee_capability;
1603 __le32 eeer;
1604 u8 low_power_ctrl;
1605 u8 reserved[3];
1606};
1607
1608I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1609
1610/* Set MAC Config command data structure (direct 0x0603) */
1611struct i40e_aq_set_mac_config {
1612 __le16 max_frame_size;
1613 u8 params;
1614#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1615#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1616#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1617#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1618#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1619#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1620#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1621#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1622#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1623#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1624#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1625#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1626#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1627#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1628 u8 tx_timer_priority; /* bitmap */
1629 __le16 tx_timer_value;
1630 __le16 fc_refresh_threshold;
1631 u8 reserved[8];
1632};
1633
1634I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1635
1636/* Restart Auto-Negotiation (direct 0x605) */
1637struct i40e_aqc_set_link_restart_an {
1638 u8 command;
1639#define I40E_AQ_PHY_RESTART_AN 0x02
1640#define I40E_AQ_PHY_LINK_ENABLE 0x04
1641 u8 reserved[15];
1642};
1643
1644I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1645
1646/* Get Link Status cmd & response data structure (direct 0x0607) */
1647struct i40e_aqc_get_link_status {
1648 __le16 command_flags; /* only field set on command */
1649#define I40E_AQ_LSE_MASK 0x3
1650#define I40E_AQ_LSE_NOP 0x0
1651#define I40E_AQ_LSE_DISABLE 0x2
1652#define I40E_AQ_LSE_ENABLE 0x3
1653/* only response uses this flag */
1654#define I40E_AQ_LSE_IS_ENABLED 0x1
1655 u8 phy_type; /* i40e_aq_phy_type */
1656 u8 link_speed; /* i40e_aq_link_speed */
1657 u8 link_info;
1658#define I40E_AQ_LINK_UP 0x01
1659#define I40E_AQ_LINK_FAULT 0x02
1660#define I40E_AQ_LINK_FAULT_TX 0x04
1661#define I40E_AQ_LINK_FAULT_RX 0x08
1662#define I40E_AQ_LINK_FAULT_REMOTE 0x10
1663#define I40E_AQ_MEDIA_AVAILABLE 0x40
1664#define I40E_AQ_SIGNAL_DETECT 0x80
1665 u8 an_info;
1666#define I40E_AQ_AN_COMPLETED 0x01
1667#define I40E_AQ_LP_AN_ABILITY 0x02
1668#define I40E_AQ_PD_FAULT 0x04
1669#define I40E_AQ_FEC_EN 0x08
1670#define I40E_AQ_PHY_LOW_POWER 0x10
1671#define I40E_AQ_LINK_PAUSE_TX 0x20
1672#define I40E_AQ_LINK_PAUSE_RX 0x40
1673#define I40E_AQ_QUALIFIED_MODULE 0x80
1674 u8 ext_info;
1675#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1676#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1677#define I40E_AQ_LINK_TX_SHIFT 0x02
1678#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1679#define I40E_AQ_LINK_TX_ACTIVE 0x00
1680#define I40E_AQ_LINK_TX_DRAINED 0x01
1681#define I40E_AQ_LINK_TX_FLUSHED 0x03
1682 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1683 __le16 max_frame_size;
1684 u8 config;
1685#define I40E_AQ_CONFIG_CRC_ENA 0x04
1686#define I40E_AQ_CONFIG_PACING_MASK 0x78
1687 u8 reserved[5];
1688};
1689
1690I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1691
1692/* Set event mask command (direct 0x613) */
1693struct i40e_aqc_set_phy_int_mask {
1694 u8 reserved[8];
1695 __le16 event_mask;
1696#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1697#define I40E_AQ_EVENT_MEDIA_NA 0x0004
1698#define I40E_AQ_EVENT_LINK_FAULT 0x0008
1699#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1700#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1701#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1702#define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1703#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1704#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1705 u8 reserved1[6];
1706};
1707
1708I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1709
1710/* Get Local AN advt register (direct 0x0614)
1711 * Set Local AN advt register (direct 0x0615)
1712 * Get Link Partner AN advt register (direct 0x0616)
1713 */
1714struct i40e_aqc_an_advt_reg {
1715 __le32 local_an_reg0;
1716 __le16 local_an_reg1;
1717 u8 reserved[10];
1718};
1719
1720I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1721
1722/* Set Loopback mode (0x0618) */
1723struct i40e_aqc_set_lb_mode {
1724 __le16 lb_mode;
1725#define I40E_AQ_LB_PHY_LOCAL 0x01
1726#define I40E_AQ_LB_PHY_REMOTE 0x02
1727#define I40E_AQ_LB_MAC_LOCAL 0x04
1728 u8 reserved[14];
1729};
1730
1731I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1732
1733/* Set PHY Reset command (0x0622) */
1734struct i40e_aqc_set_phy_reset {
1735 u8 reset_flags;
1736#define I40E_AQ_PHY_RESET_REQUEST 0x02
1737 u8 reserved[15];
1738};
1739
1740I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_reset);
1741
1742enum i40e_aq_phy_reg_type {
1743 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1744 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1745 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1746};
1747
1748/* NVM Read command (indirect 0x0701)
1749 * NVM Erase commands (direct 0x0702)
1750 * NVM Update commands (indirect 0x0703)
1751 */
1752struct i40e_aqc_nvm_update {
1753 u8 command_flags;
1754#define I40E_AQ_NVM_LAST_CMD 0x01
1755#define I40E_AQ_NVM_FLASH_ONLY 0x80
1756 u8 module_pointer;
1757 __le16 length;
1758 __le32 offset;
1759 __le32 addr_high;
1760 __le32 addr_low;
1761};
1762
1763I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1764
1765/* Send to PF command (indirect 0x0801) id is only used by PF
1766 * Send to VF command (indirect 0x0802) id is only used by PF
1767 * Send to Peer PF command (indirect 0x0803)
1768 */
1769struct i40e_aqc_pf_vf_message {
1770 __le32 id;
1771 u8 reserved[4];
1772 __le32 addr_high;
1773 __le32 addr_low;
1774};
1775
1776I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1777
1778/* Alternate structure */
1779
1780/* Direct write (direct 0x0900)
1781 * Direct read (direct 0x0902)
1782 */
1783struct i40e_aqc_alternate_write {
1784 __le32 address0;
1785 __le32 data0;
1786 __le32 address1;
1787 __le32 data1;
1788};
1789
1790I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1791
1792/* Indirect write (indirect 0x0901)
1793 * Indirect read (indirect 0x0903)
1794 */
1795
1796struct i40e_aqc_alternate_ind_write {
1797 __le32 address;
1798 __le32 length;
1799 __le32 addr_high;
1800 __le32 addr_low;
1801};
1802
1803I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1804
1805/* Done alternate write (direct 0x0904)
1806 * uses i40e_aq_desc
1807 */
1808struct i40e_aqc_alternate_write_done {
1809 __le16 cmd_flags;
1810#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
1811#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
1812#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
1813#define I40E_AQ_ALTERNATE_RESET_NEEDED 2
1814 u8 reserved[14];
1815};
1816
1817I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
1818
1819/* Set OEM mode (direct 0x0905) */
1820struct i40e_aqc_alternate_set_mode {
1821 __le32 mode;
1822#define I40E_AQ_ALTERNATE_MODE_NONE 0
1823#define I40E_AQ_ALTERNATE_MODE_OEM 1
1824 u8 reserved[12];
1825};
1826
1827I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
1828
1829/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
1830
1831/* async events 0x10xx */
1832
1833/* Lan Queue Overflow Event (direct, 0x1001) */
1834struct i40e_aqc_lan_overflow {
1835 __le32 prtdcb_rupto;
1836 __le32 otx_ctl;
1837 u8 reserved[8];
1838};
1839
1840I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
1841
1842/* Get LLDP MIB (indirect 0x0A00) */
1843struct i40e_aqc_lldp_get_mib {
1844 u8 type;
1845 u8 reserved1;
1846#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
1847#define I40E_AQ_LLDP_MIB_LOCAL 0x0
1848#define I40E_AQ_LLDP_MIB_REMOTE 0x1
1849#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
1850#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
1851#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
1852#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
1853#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
1854#define I40E_AQ_LLDP_TX_SHIFT 0x4
1855#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
1856/* TX pause flags use I40E_AQ_LINK_TX_* above */
1857 __le16 local_len;
1858 __le16 remote_len;
1859 u8 reserved2[2];
1860 __le32 addr_high;
1861 __le32 addr_low;
1862};
1863
1864I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
1865
1866/* Configure LLDP MIB Change Event (direct 0x0A01)
1867 * also used for the event (with type in the command field)
1868 */
1869struct i40e_aqc_lldp_update_mib {
1870 u8 command;
1871#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1872#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
1873 u8 reserved[7];
1874 __le32 addr_high;
1875 __le32 addr_low;
1876};
1877
1878I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
1879
1880/* Add LLDP TLV (indirect 0x0A02)
1881 * Delete LLDP TLV (indirect 0x0A04)
1882 */
1883struct i40e_aqc_lldp_add_tlv {
1884 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1885 u8 reserved1[1];
1886 __le16 len;
1887 u8 reserved2[4];
1888 __le32 addr_high;
1889 __le32 addr_low;
1890};
1891
1892I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
1893
1894/* Update LLDP TLV (indirect 0x0A03) */
1895struct i40e_aqc_lldp_update_tlv {
1896 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1897 u8 reserved;
1898 __le16 old_len;
1899 __le16 new_offset;
1900 __le16 new_len;
1901 __le32 addr_high;
1902 __le32 addr_low;
1903};
1904
1905I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
1906
1907/* Stop LLDP (direct 0x0A05) */
1908struct i40e_aqc_lldp_stop {
1909 u8 command;
1910#define I40E_AQ_LLDP_AGENT_STOP 0x0
1911#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
1912 u8 reserved[15];
1913};
1914
1915I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
1916
1917/* Start LLDP (direct 0x0A06) */
1918
1919struct i40e_aqc_lldp_start {
1920 u8 command;
1921#define I40E_AQ_LLDP_AGENT_START 0x1
1922 u8 reserved[15];
1923};
1924
1925I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
1926
1927/* Apply MIB changes (0x0A07)
1928 * uses the generic struc as it contains no data
1929 */
1930
1931/* Add Udp Tunnel command and completion (direct 0x0B00) */
1932struct i40e_aqc_add_udp_tunnel {
1933 __le16 udp_port;
1934 u8 header_len; /* in DWords, 1 to 15 */
1935 u8 protocol_type;
1936#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x0
1937#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x2
1938#define I40E_AQC_TUNNEL_TYPE_NGE 0x3
1939 u8 variable_udp_length;
1940#define I40E_AQC_TUNNEL_FIXED_UDP_LENGTH 0x0
1941#define I40E_AQC_TUNNEL_VARIABLE_UDP_LENGTH 0x1
1942 u8 udp_key_index;
1943#define I40E_AQC_TUNNEL_KEY_INDEX_VXLAN 0x0
1944#define I40E_AQC_TUNNEL_KEY_INDEX_NGE 0x1
1945#define I40E_AQC_TUNNEL_KEY_INDEX_PROPRIETARY_UDP 0x2
1946 u8 reserved[10];
1947};
1948
1949I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
1950
1951struct i40e_aqc_add_udp_tunnel_completion {
1952 __le16 udp_port;
1953 u8 filter_entry_index;
1954 u8 multiple_pfs;
1955#define I40E_AQC_SINGLE_PF 0x0
1956#define I40E_AQC_MULTIPLE_PFS 0x1
1957 u8 total_filters;
1958 u8 reserved[11];
1959};
1960
1961I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
1962
1963/* remove UDP Tunnel command (0x0B01) */
1964struct i40e_aqc_remove_udp_tunnel {
1965 u8 reserved[2];
1966 u8 index; /* 0 to 15 */
Greg Rose90327e72013-12-21 06:13:21 +0000[diff] [blame]1967 u8 pf_filters;
1968 u8 total_filters;
1969 u8 reserved2[11];
Greg Rosed358aa92013-12-21 06:13:11 +0000[diff] [blame]1970};
1971
1972I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
1973
1974struct i40e_aqc_del_udp_tunnel_completion {
1975 __le16 udp_port;
1976 u8 index; /* 0 to 15 */
1977 u8 multiple_pfs;
1978 u8 total_filters_used;
Greg Rose90327e72013-12-21 06:13:21 +0000[diff] [blame]1979 u8 reserved;
1980 u8 tunnels_free;
1981 u8 reserved1[9];
Greg Rosed358aa92013-12-21 06:13:11 +0000[diff] [blame]1982};
1983
1984I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
1985
1986/* tunnel key structure 0x0B10 */
1987
Greg Rose90327e72013-12-21 06:13:21 +0000[diff] [blame]1988struct i40e_aqc_tunnel_key_structure_A0 {
1989 __le16 key1_off;
1990 __le16 key1_len;
1991 __le16 key2_off;
1992 __le16 key2_len;
1993 __le16 flags;
1994#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
1995/* response flags */
1996#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
1997#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
1998#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
1999 u8 resreved[6];
2000};
2001
2002I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0);
2003
Greg Rosed358aa92013-12-21 06:13:11 +0000[diff] [blame]2004struct i40e_aqc_tunnel_key_structure {
2005 u8 key1_off;
2006 u8 key2_off;
2007 u8 key1_len; /* 0 to 15 */
2008 u8 key2_len; /* 0 to 15 */
2009 u8 flags;
2010#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2011/* response flags */
2012#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2013#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2014#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2015 u8 network_key_index;
2016#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2017#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2018#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2019#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2020 u8 reserved[10];
2021};
2022
2023I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2024
2025/* OEM mode commands (direct 0xFE0x) */
2026struct i40e_aqc_oem_param_change {
2027 __le32 param_type;
2028#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2029#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2030#define I40E_AQ_OEM_PARAM_MAC 2
2031 __le32 param_value1;
2032 u8 param_value2[8];
2033};
2034
2035I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2036
2037struct i40e_aqc_oem_state_change {
2038 __le32 state;
2039#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2040#define I40E_AQ_OEM_STATE_LINK_UP 0x1
2041 u8 reserved[12];
2042};
2043
2044I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2045
2046/* debug commands */
2047
2048/* get device id (0xFF00) uses the generic structure */
2049
2050/* set test more (0xFF01, internal) */
2051
2052struct i40e_acq_set_test_mode {
2053 u8 mode;
2054#define I40E_AQ_TEST_PARTIAL 0
2055#define I40E_AQ_TEST_FULL 1
2056#define I40E_AQ_TEST_NVM 2
2057 u8 reserved[3];
2058 u8 command;
2059#define I40E_AQ_TEST_OPEN 0
2060#define I40E_AQ_TEST_CLOSE 1
2061#define I40E_AQ_TEST_INC 2
2062 u8 reserved2[3];
2063 __le32 address_high;
2064 __le32 address_low;
2065};
2066
2067I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2068
2069/* Debug Read Register command (0xFF03)
2070 * Debug Write Register command (0xFF04)
2071 */
2072struct i40e_aqc_debug_reg_read_write {
2073 __le32 reserved;
2074 __le32 address;
2075 __le32 value_high;
2076 __le32 value_low;
2077};
2078
2079I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2080
2081/* Scatter/gather Reg Read (indirect 0xFF05)
2082 * Scatter/gather Reg Write (indirect 0xFF06)
2083 */
2084
2085/* i40e_aq_desc is used for the command */
2086struct i40e_aqc_debug_reg_sg_element_data {
2087 __le32 address;
2088 __le32 value;
2089};
2090
2091/* Debug Modify register (direct 0xFF07) */
2092struct i40e_aqc_debug_modify_reg {
2093 __le32 address;
2094 __le32 value;
2095 __le32 clear_mask;
2096 __le32 set_mask;
2097};
2098
2099I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2100
2101/* dump internal data (0xFF08, indirect) */
2102
2103#define I40E_AQ_CLUSTER_ID_AUX 0
2104#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2105#define I40E_AQ_CLUSTER_ID_TXSCHED 2
2106#define I40E_AQ_CLUSTER_ID_HMC 3
2107#define I40E_AQ_CLUSTER_ID_MAC0 4
2108#define I40E_AQ_CLUSTER_ID_MAC1 5
2109#define I40E_AQ_CLUSTER_ID_MAC2 6
2110#define I40E_AQ_CLUSTER_ID_MAC3 7
2111#define I40E_AQ_CLUSTER_ID_DCB 8
2112#define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2113#define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2114#define I40E_AQ_CLUSTER_ID_ALTRAM 11
2115
2116struct i40e_aqc_debug_dump_internals {
2117 u8 cluster_id;
2118 u8 table_id;
2119 __le16 data_size;
2120 __le32 idx;
2121 __le32 address_high;
2122 __le32 address_low;
2123};
2124
2125I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2126
2127struct i40e_aqc_debug_modify_internals {
2128 u8 cluster_id;
2129 u8 cluster_specific_params[7];
2130 __le32 address_high;
2131 __le32 address_low;
2132};
2133
2134I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2135
2136#endif