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gerrit-public.fairphone.software / kernel / msm-4.9 / beff1084f1cab155feb3551d72d41ce48af4ae79 / . / arch / arm / boot / dts / tegra124-jetson-tk1.dts
blob: 66b4451eb2ca1b98bfbc33263eb31d18df37d1b0 [file] [log] [blame]
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1/dts-v1/;
2
3#include <dt-bindings/input/input.h>
4#include "tegra124.dtsi"
5
Mikko Perttunen6e72cf02015-03-12 15:48:01 +0100[diff] [blame]6#include "tegra124-jetson-tk1-emc.dtsi"
7
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]8/ {
9 model = "NVIDIA Tegra124 Jetson TK1";
10 compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
11
12 aliases {
13 rtc0 = "/i2c@0,7000d000/pmic@40";
14 rtc1 = "/rtc@0,7000e000";
Olof Johanssonc4574aa2014-11-11 12:49:30 -0800[diff] [blame]15 serial0 = &uartd;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]16 };
17
18 memory {
19 reg = <0x0 0x80000000 0x0 0x80000000>;
20 };
21
Thierry Reding8e2b9e42014-09-17 10:02:45 -0600[diff] [blame]22 pcie-controller@0,01003000 {
23 status = "okay";
24
25 avddio-pex-supply = <&vdd_1v05_run>;
26 dvddio-pex-supply = <&vdd_1v05_run>;
27 avdd-pex-pll-supply = <&vdd_1v05_run>;
28 hvdd-pex-supply = <&vdd_3v3_lp0>;
29 hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
30 vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
31 avdd-pll-erefe-supply = <&avdd_1v05_run>;
32
33 pci@1,0 {
34 status = "okay";
35 };
36
37 pci@2,0 {
38 status = "okay";
39 };
40 };
41
Thierry Reding6054dd32014-04-25 17:44:47 +0200[diff] [blame]42 host1x@0,50000000 {
43 hdmi@0,54280000 {
44 status = "okay";
45
46 hdmi-supply = <&vdd_5v0_hdmi>;
47 pll-supply = <&vdd_hdmi_pll>;
48 vdd-supply = <&vdd_3v3_hdmi>;
49
50 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
51 nvidia,hpd-gpio =
52 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
53 };
54 };
55
Alexandre Courbot21fa1962015-07-01 18:13:47 +0900[diff] [blame]56 gpu@0,57000000 {
57 /*
58 * Node left disabled on purpose - the bootloader will enable
59 * it after having set the VPR up
60 */
61 vdd-supply = <&vdd_gpu>;
62 };
63
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]64 pinmux: pinmux@0,70000868 {
Stephen Warren6dbaff22014-09-03 09:42:06 -0600[diff] [blame]65 pinctrl-names = "boot";
66 pinctrl-0 = <&state_boot>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]67
Stephen Warren6dbaff22014-09-03 09:42:06 -0600[diff] [blame]68 state_boot: pinmux {
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]69 clk_32k_out_pa0 {
70 nvidia,pins = "clk_32k_out_pa0";
71 nvidia,function = "soc";
72 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]73 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]74 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
75 };
76 uart3_cts_n_pa1 {
77 nvidia,pins = "uart3_cts_n_pa1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]78 nvidia,function = "gmi";
79 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
80 nvidia,tristate = <TEGRA_PIN_ENABLE>;
81 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]82 };
83 dap2_fs_pa2 {
84 nvidia,pins = "dap2_fs_pa2";
85 nvidia,function = "i2s1";
86 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
87 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]88 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]89 };
90 dap2_sclk_pa3 {
91 nvidia,pins = "dap2_sclk_pa3";
92 nvidia,function = "i2s1";
93 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
94 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]95 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]96 };
97 dap2_din_pa4 {
98 nvidia,pins = "dap2_din_pa4";
99 nvidia,function = "i2s1";
100 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]101 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]102 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
103 };
104 dap2_dout_pa5 {
105 nvidia,pins = "dap2_dout_pa5";
106 nvidia,function = "i2s1";
107 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
108 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]109 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]110 };
111 sdmmc3_clk_pa6 {
112 nvidia,pins = "sdmmc3_clk_pa6";
113 nvidia,function = "sdmmc3";
114 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
115 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]116 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]117 };
118 sdmmc3_cmd_pa7 {
119 nvidia,pins = "sdmmc3_cmd_pa7";
120 nvidia,function = "sdmmc3";
121 nvidia,pull = <TEGRA_PIN_PULL_UP>;
122 nvidia,tristate = <TEGRA_PIN_DISABLE>;
123 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
124 };
125 pb0 {
126 nvidia,pins = "pb0";
127 nvidia,function = "uartd";
128 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]129 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]130 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
131 };
132 pb1 {
133 nvidia,pins = "pb1";
134 nvidia,function = "uartd";
135 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]136 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]137 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
138 };
139 sdmmc3_dat3_pb4 {
140 nvidia,pins = "sdmmc3_dat3_pb4";
141 nvidia,function = "sdmmc3";
142 nvidia,pull = <TEGRA_PIN_PULL_UP>;
143 nvidia,tristate = <TEGRA_PIN_DISABLE>;
144 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
145 };
146 sdmmc3_dat2_pb5 {
147 nvidia,pins = "sdmmc3_dat2_pb5";
148 nvidia,function = "sdmmc3";
149 nvidia,pull = <TEGRA_PIN_PULL_UP>;
150 nvidia,tristate = <TEGRA_PIN_DISABLE>;
151 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
152 };
153 sdmmc3_dat1_pb6 {
154 nvidia,pins = "sdmmc3_dat1_pb6";
155 nvidia,function = "sdmmc3";
156 nvidia,pull = <TEGRA_PIN_PULL_UP>;
157 nvidia,tristate = <TEGRA_PIN_DISABLE>;
158 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
159 };
160 sdmmc3_dat0_pb7 {
161 nvidia,pins = "sdmmc3_dat0_pb7";
162 nvidia,function = "sdmmc3";
163 nvidia,pull = <TEGRA_PIN_PULL_UP>;
164 nvidia,tristate = <TEGRA_PIN_DISABLE>;
165 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
166 };
167 uart3_rts_n_pc0 {
168 nvidia,pins = "uart3_rts_n_pc0";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]169 nvidia,function = "gmi";
170 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
171 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]172 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
173 };
174 uart2_txd_pc2 {
175 nvidia,pins = "uart2_txd_pc2";
176 nvidia,function = "irda";
177 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
178 nvidia,tristate = <TEGRA_PIN_DISABLE>;
179 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
180 };
181 uart2_rxd_pc3 {
182 nvidia,pins = "uart2_rxd_pc3";
183 nvidia,function = "irda";
184 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]185 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]186 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
187 };
188 gen1_i2c_scl_pc4 {
189 nvidia,pins = "gen1_i2c_scl_pc4";
190 nvidia,function = "i2c1";
191 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
192 nvidia,tristate = <TEGRA_PIN_DISABLE>;
193 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
194 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
195 };
196 gen1_i2c_sda_pc5 {
197 nvidia,pins = "gen1_i2c_sda_pc5";
198 nvidia,function = "i2c1";
199 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
200 nvidia,tristate = <TEGRA_PIN_DISABLE>;
201 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
202 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
203 };
204 pc7 {
205 nvidia,pins = "pc7";
206 nvidia,function = "rsvd1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]207 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
208 nvidia,tristate = <TEGRA_PIN_ENABLE>;
209 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]210 };
211 pg0 {
212 nvidia,pins = "pg0";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]213 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]214 nvidia,tristate = <TEGRA_PIN_ENABLE>;
215 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]216 };
217 pg1 {
218 nvidia,pins = "pg1";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]219 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]220 nvidia,tristate = <TEGRA_PIN_ENABLE>;
221 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]222 };
223 pg2 {
224 nvidia,pins = "pg2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]225 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
226 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]227 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
228 };
229 pg3 {
230 nvidia,pins = "pg3";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]231 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
232 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]233 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
234 };
235 pg4 {
236 nvidia,pins = "pg4";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]237 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]238 nvidia,tristate = <TEGRA_PIN_ENABLE>;
239 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]240 };
241 pg5 {
242 nvidia,pins = "pg5";
243 nvidia,function = "spi4";
244 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
245 nvidia,tristate = <TEGRA_PIN_DISABLE>;
246 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
247 };
248 pg6 {
249 nvidia,pins = "pg6";
250 nvidia,function = "spi4";
251 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
252 nvidia,tristate = <TEGRA_PIN_DISABLE>;
253 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
254 };
255 pg7 {
256 nvidia,pins = "pg7";
257 nvidia,function = "spi4";
258 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]259 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]260 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
261 };
262 ph0 {
263 nvidia,pins = "ph0";
264 nvidia,function = "gmi";
265 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
266 nvidia,tristate = <TEGRA_PIN_ENABLE>;
267 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
268 };
269 ph1 {
270 nvidia,pins = "ph1";
271 nvidia,function = "pwm1";
272 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
273 nvidia,tristate = <TEGRA_PIN_DISABLE>;
274 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
275 };
276 ph2 {
277 nvidia,pins = "ph2";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]278 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
279 nvidia,tristate = <TEGRA_PIN_DISABLE>;
280 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
281 };
282 ph3 {
283 nvidia,pins = "ph3";
284 nvidia,function = "gmi";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]285 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
286 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]287 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
288 };
289 ph4 {
290 nvidia,pins = "ph4";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]291 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
292 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]293 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
294 };
295 ph5 {
296 nvidia,pins = "ph5";
297 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]298 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
299 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]300 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
301 };
302 ph6 {
303 nvidia,pins = "ph6";
304 nvidia,function = "gmi";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]305 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
306 nvidia,tristate = <TEGRA_PIN_ENABLE>;
307 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]308 };
309 ph7 {
310 nvidia,pins = "ph7";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]311 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
312 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]313 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]314 };
315 pi0 {
316 nvidia,pins = "pi0";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]317 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
318 nvidia,tristate = <TEGRA_PIN_DISABLE>;
319 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
320 };
321 pi1 {
322 nvidia,pins = "pi1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]323 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]324 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]325 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]326 };
327 pi2 {
328 nvidia,pins = "pi2";
329 nvidia,function = "rsvd4";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]330 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
331 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]332 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
333 };
334 pi3 {
335 nvidia,pins = "pi3";
336 nvidia,function = "spi4";
337 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
338 nvidia,tristate = <TEGRA_PIN_DISABLE>;
339 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
340 };
341 pi4 {
342 nvidia,pins = "pi4";
343 nvidia,function = "gmi";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]344 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
345 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]346 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
347 };
348 pi5 {
349 nvidia,pins = "pi5";
350 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]351 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
352 nvidia,tristate = <TEGRA_PIN_ENABLE>;
353 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]354 };
355 pi6 {
356 nvidia,pins = "pi6";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]357 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
358 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]359 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
360 };
361 pi7 {
362 nvidia,pins = "pi7";
363 nvidia,function = "rsvd1";
364 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
365 nvidia,tristate = <TEGRA_PIN_ENABLE>;
366 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
367 };
368 pj0 {
369 nvidia,pins = "pj0";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]370 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
371 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]372 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
373 };
374 pj2 {
375 nvidia,pins = "pj2";
376 nvidia,function = "rsvd1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]377 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
378 nvidia,tristate = <TEGRA_PIN_ENABLE>;
379 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]380 };
381 uart2_cts_n_pj5 {
382 nvidia,pins = "uart2_cts_n_pj5";
383 nvidia,function = "uartb";
384 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]385 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]386 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
387 };
388 uart2_rts_n_pj6 {
389 nvidia,pins = "uart2_rts_n_pj6";
390 nvidia,function = "uartb";
391 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
392 nvidia,tristate = <TEGRA_PIN_DISABLE>;
393 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
394 };
395 pj7 {
396 nvidia,pins = "pj7";
397 nvidia,function = "uartd";
398 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
399 nvidia,tristate = <TEGRA_PIN_DISABLE>;
400 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
401 };
402 pk0 {
403 nvidia,pins = "pk0";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]404 nvidia,function = "rsvd1";
405 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
406 nvidia,tristate = <TEGRA_PIN_ENABLE>;
407 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]408 };
409 pk1 {
410 nvidia,pins = "pk1";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]411 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
412 nvidia,tristate = <TEGRA_PIN_DISABLE>;
413 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
414 };
415 pk2 {
416 nvidia,pins = "pk2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]417 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]418 nvidia,tristate = <TEGRA_PIN_DISABLE>;
419 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
420 };
421 pk3 {
422 nvidia,pins = "pk3";
423 nvidia,function = "gmi";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]424 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
425 nvidia,tristate = <TEGRA_PIN_ENABLE>;
426 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]427 };
428 pk4 {
429 nvidia,pins = "pk4";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]430 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
431 nvidia,tristate = <TEGRA_PIN_DISABLE>;
432 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
433 };
434 spdif_out_pk5 {
435 nvidia,pins = "spdif_out_pk5";
436 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]437 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
438 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]439 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
440 };
441 spdif_in_pk6 {
442 nvidia,pins = "spdif_in_pk6";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]443 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
444 nvidia,tristate = <TEGRA_PIN_DISABLE>;
445 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
446 };
447 pk7 {
448 nvidia,pins = "pk7";
449 nvidia,function = "uartd";
450 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
451 nvidia,tristate = <TEGRA_PIN_DISABLE>;
452 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
453 };
454 dap1_fs_pn0 {
455 nvidia,pins = "dap1_fs_pn0";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]456 nvidia,function = "rsvd4";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]457 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]458 nvidia,tristate = <TEGRA_PIN_ENABLE>;
459 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]460 };
461 dap1_din_pn1 {
462 nvidia,pins = "dap1_din_pn1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]463 nvidia,function = "rsvd4";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]464 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]465 nvidia,tristate = <TEGRA_PIN_ENABLE>;
466 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]467 };
468 dap1_dout_pn2 {
469 nvidia,pins = "dap1_dout_pn2";
470 nvidia,function = "sata";
471 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
472 nvidia,tristate = <TEGRA_PIN_DISABLE>;
473 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
474 };
475 dap1_sclk_pn3 {
476 nvidia,pins = "dap1_sclk_pn3";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]477 nvidia,function = "rsvd4";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]478 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]479 nvidia,tristate = <TEGRA_PIN_ENABLE>;
480 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]481 };
482 usb_vbus_en0_pn4 {
483 nvidia,pins = "usb_vbus_en0_pn4";
484 nvidia,function = "usb";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]485 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]486 nvidia,tristate = <TEGRA_PIN_DISABLE>;
487 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]488 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]489 };
490 usb_vbus_en1_pn5 {
491 nvidia,pins = "usb_vbus_en1_pn5";
492 nvidia,function = "usb";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]493 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]494 nvidia,tristate = <TEGRA_PIN_DISABLE>;
495 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]496 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]497 };
498 hdmi_int_pn7 {
499 nvidia,pins = "hdmi_int_pn7";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]500 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]501 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]502 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
503 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
504 };
505 ulpi_data7_po0 {
506 nvidia,pins = "ulpi_data7_po0";
507 nvidia,function = "ulpi";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]508 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
509 nvidia,tristate = <TEGRA_PIN_ENABLE>;
510 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]511 };
512 ulpi_data0_po1 {
513 nvidia,pins = "ulpi_data0_po1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]514 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
515 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]516 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
517 };
518 ulpi_data1_po2 {
519 nvidia,pins = "ulpi_data1_po2";
520 nvidia,function = "ulpi";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]521 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
522 nvidia,tristate = <TEGRA_PIN_ENABLE>;
523 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]524 };
525 ulpi_data2_po3 {
526 nvidia,pins = "ulpi_data2_po3";
527 nvidia,function = "ulpi";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]528 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
529 nvidia,tristate = <TEGRA_PIN_ENABLE>;
530 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]531 };
532 ulpi_data3_po4 {
533 nvidia,pins = "ulpi_data3_po4";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]534 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
535 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]536 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
537 };
538 ulpi_data4_po5 {
539 nvidia,pins = "ulpi_data4_po5";
540 nvidia,function = "ulpi";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]541 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
542 nvidia,tristate = <TEGRA_PIN_ENABLE>;
543 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]544 };
545 ulpi_data5_po6 {
546 nvidia,pins = "ulpi_data5_po6";
547 nvidia,function = "ulpi";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]548 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
549 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]550 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
551 };
552 ulpi_data6_po7 {
553 nvidia,pins = "ulpi_data6_po7";
554 nvidia,function = "ulpi";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]555 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
556 nvidia,tristate = <TEGRA_PIN_ENABLE>;
557 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]558 };
559 dap3_fs_pp0 {
560 nvidia,pins = "dap3_fs_pp0";
561 nvidia,function = "i2s2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]562 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
563 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]564 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
565 };
566 dap3_din_pp1 {
567 nvidia,pins = "dap3_din_pp1";
568 nvidia,function = "i2s2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]569 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
570 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]571 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
572 };
573 dap3_dout_pp2 {
574 nvidia,pins = "dap3_dout_pp2";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]575 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
576 nvidia,tristate = <TEGRA_PIN_DISABLE>;
577 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
578 };
579 dap3_sclk_pp3 {
580 nvidia,pins = "dap3_sclk_pp3";
581 nvidia,function = "rsvd3";
582 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
583 nvidia,tristate = <TEGRA_PIN_ENABLE>;
584 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
585 };
586 dap4_fs_pp4 {
587 nvidia,pins = "dap4_fs_pp4";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]588 nvidia,function = "rsvd4";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]589 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]590 nvidia,tristate = <TEGRA_PIN_ENABLE>;
591 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]592 };
593 dap4_din_pp5 {
594 nvidia,pins = "dap4_din_pp5";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]595 nvidia,function = "rsvd3";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]596 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]597 nvidia,tristate = <TEGRA_PIN_ENABLE>;
598 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]599 };
600 dap4_dout_pp6 {
601 nvidia,pins = "dap4_dout_pp6";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]602 nvidia,function = "rsvd4";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]603 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]604 nvidia,tristate = <TEGRA_PIN_ENABLE>;
605 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]606 };
607 dap4_sclk_pp7 {
608 nvidia,pins = "dap4_sclk_pp7";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]609 nvidia,function = "rsvd3";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]610 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]611 nvidia,tristate = <TEGRA_PIN_ENABLE>;
612 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]613 };
614 kb_col0_pq0 {
615 nvidia,pins = "kb_col0_pq0";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]616 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]617 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]618 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
619 };
620 kb_col1_pq1 {
621 nvidia,pins = "kb_col1_pq1";
622 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]623 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
624 nvidia,tristate = <TEGRA_PIN_ENABLE>;
625 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]626 };
627 kb_col2_pq2 {
628 nvidia,pins = "kb_col2_pq2";
629 nvidia,function = "rsvd2";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]630 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
631 nvidia,tristate = <TEGRA_PIN_ENABLE>;
632 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
633 };
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]634 kb_col3_pq3 {
635 nvidia,pins = "kb_col3_pq3";
636 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
637 nvidia,tristate = <TEGRA_PIN_ENABLE>;
638 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
639 };
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]640 kb_col4_pq4 {
641 nvidia,pins = "kb_col4_pq4";
642 nvidia,function = "sdmmc3";
643 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]644 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]645 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
646 };
647 kb_col5_pq5 {
648 nvidia,pins = "kb_col5_pq5";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]649 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
650 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]651 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
652 };
653 kb_col6_pq6 {
654 nvidia,pins = "kb_col6_pq6";
655 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]656 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
657 nvidia,tristate = <TEGRA_PIN_ENABLE>;
658 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]659 };
660 kb_col7_pq7 {
661 nvidia,pins = "kb_col7_pq7";
662 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]663 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
664 nvidia,tristate = <TEGRA_PIN_ENABLE>;
665 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]666 };
667 kb_row0_pr0 {
668 nvidia,pins = "kb_row0_pr0";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]669 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
670 nvidia,tristate = <TEGRA_PIN_DISABLE>;
671 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
672 };
673 kb_row1_pr1 {
674 nvidia,pins = "kb_row1_pr1";
675 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]676 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
677 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]678 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
679 };
680 kb_row2_pr2 {
681 nvidia,pins = "kb_row2_pr2";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]682 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
683 nvidia,tristate = <TEGRA_PIN_DISABLE>;
684 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
685 };
686 kb_row3_pr3 {
687 nvidia,pins = "kb_row3_pr3";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]688 nvidia,function = "kbc";
689 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
690 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]691 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
692 };
693 kb_row4_pr4 {
694 nvidia,pins = "kb_row4_pr4";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]695 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
696 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]697 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
698 };
699 kb_row5_pr5 {
700 nvidia,pins = "kb_row5_pr5";
701 nvidia,function = "rsvd3";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]702 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
703 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]704 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
705 };
706 kb_row6_pr6 {
707 nvidia,pins = "kb_row6_pr6";
708 nvidia,function = "displaya_alt";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]709 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
710 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]711 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
712 };
713 kb_row7_pr7 {
714 nvidia,pins = "kb_row7_pr7";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]715 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
716 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]717 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
718 };
719 kb_row8_ps0 {
720 nvidia,pins = "kb_row8_ps0";
721 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]722 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
723 nvidia,tristate = <TEGRA_PIN_ENABLE>;
724 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]725 };
726 kb_row9_ps1 {
727 nvidia,pins = "kb_row9_ps1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]728 nvidia,function = "uarta";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]729 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
730 nvidia,tristate = <TEGRA_PIN_DISABLE>;
731 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
732 };
733 kb_row10_ps2 {
734 nvidia,pins = "kb_row10_ps2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]735 nvidia,function = "uarta";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]736 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]737 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]738 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
739 };
740 kb_row11_ps3 {
741 nvidia,pins = "kb_row11_ps3";
742 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]743 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
744 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]745 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
746 };
747 kb_row12_ps4 {
748 nvidia,pins = "kb_row12_ps4";
749 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]750 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
751 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]752 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
753 };
754 kb_row13_ps5 {
755 nvidia,pins = "kb_row13_ps5";
756 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]757 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
758 nvidia,tristate = <TEGRA_PIN_ENABLE>;
759 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]760 };
761 kb_row14_ps6 {
762 nvidia,pins = "kb_row14_ps6";
763 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]764 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
765 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]766 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
767 };
768 kb_row15_ps7 {
769 nvidia,pins = "kb_row15_ps7";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]770 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
771 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]772 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
773 };
774 kb_row16_pt0 {
775 nvidia,pins = "kb_row16_pt0";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]776 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
777 nvidia,tristate = <TEGRA_PIN_DISABLE>;
778 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
779 };
780 kb_row17_pt1 {
781 nvidia,pins = "kb_row17_pt1";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]782 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]783 nvidia,tristate = <TEGRA_PIN_ENABLE>;
784 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]785 };
786 gen2_i2c_scl_pt5 {
787 nvidia,pins = "gen2_i2c_scl_pt5";
788 nvidia,function = "i2c2";
789 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
790 nvidia,tristate = <TEGRA_PIN_DISABLE>;
791 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
792 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
793 };
794 gen2_i2c_sda_pt6 {
795 nvidia,pins = "gen2_i2c_sda_pt6";
796 nvidia,function = "i2c2";
797 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
798 nvidia,tristate = <TEGRA_PIN_DISABLE>;
799 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
800 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
801 };
802 sdmmc4_cmd_pt7 {
803 nvidia,pins = "sdmmc4_cmd_pt7";
804 nvidia,function = "sdmmc4";
805 nvidia,pull = <TEGRA_PIN_PULL_UP>;
806 nvidia,tristate = <TEGRA_PIN_DISABLE>;
807 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
808 };
809 pu0 {
810 nvidia,pins = "pu0";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]811 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
812 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]813 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]814 };
815 pu1 {
816 nvidia,pins = "pu1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]817 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]818 nvidia,tristate = <TEGRA_PIN_DISABLE>;
819 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
820 };
821 pu2 {
822 nvidia,pins = "pu2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]823 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]824 nvidia,tristate = <TEGRA_PIN_DISABLE>;
825 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
826 };
827 pu3 {
828 nvidia,pins = "pu3";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]829 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
830 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]831 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]832 };
833 pu4 {
834 nvidia,pins = "pu4";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]835 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
836 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]837 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]838 };
839 pu5 {
840 nvidia,pins = "pu5";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]841 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]842 nvidia,tristate = <TEGRA_PIN_DISABLE>;
843 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
844 };
845 pu6 {
846 nvidia,pins = "pu6";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]847 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]848 nvidia,tristate = <TEGRA_PIN_DISABLE>;
849 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
850 };
851 pv0 {
852 nvidia,pins = "pv0";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]853 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
854 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]855 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
856 };
857 pv1 {
858 nvidia,pins = "pv1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]859 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
860 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]861 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
862 };
863 sdmmc3_cd_n_pv2 {
864 nvidia,pins = "sdmmc3_cd_n_pv2";
865 nvidia,function = "sdmmc3";
866 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]867 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]868 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
869 };
870 sdmmc1_wp_n_pv3 {
871 nvidia,pins = "sdmmc1_wp_n_pv3";
872 nvidia,function = "sdmmc1";
873 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
874 nvidia,tristate = <TEGRA_PIN_ENABLE>;
875 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
876 };
877 ddc_scl_pv4 {
878 nvidia,pins = "ddc_scl_pv4";
879 nvidia,function = "i2c4";
880 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
881 nvidia,tristate = <TEGRA_PIN_DISABLE>;
882 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
883 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
884 };
885 ddc_sda_pv5 {
886 nvidia,pins = "ddc_sda_pv5";
887 nvidia,function = "i2c4";
888 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
889 nvidia,tristate = <TEGRA_PIN_DISABLE>;
890 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
891 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
892 };
893 gpio_w2_aud_pw2 {
894 nvidia,pins = "gpio_w2_aud_pw2";
895 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]896 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
897 nvidia,tristate = <TEGRA_PIN_ENABLE>;
898 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]899 };
900 gpio_w3_aud_pw3 {
901 nvidia,pins = "gpio_w3_aud_pw3";
902 nvidia,function = "spi6";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]903 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
904 nvidia,tristate = <TEGRA_PIN_ENABLE>;
905 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]906 };
907 dap_mclk1_pw4 {
908 nvidia,pins = "dap_mclk1_pw4";
909 nvidia,function = "extperiph1";
910 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
911 nvidia,tristate = <TEGRA_PIN_DISABLE>;
912 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
913 };
914 clk2_out_pw5 {
915 nvidia,pins = "clk2_out_pw5";
916 nvidia,function = "extperiph2";
917 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
918 nvidia,tristate = <TEGRA_PIN_DISABLE>;
919 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
920 };
921 uart3_txd_pw6 {
922 nvidia,pins = "uart3_txd_pw6";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]923 nvidia,function = "rsvd2";
924 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
925 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]926 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
927 };
928 uart3_rxd_pw7 {
929 nvidia,pins = "uart3_rxd_pw7";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]930 nvidia,function = "rsvd2";
931 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
932 nvidia,tristate = <TEGRA_PIN_ENABLE>;
933 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]934 };
935 dvfs_pwm_px0 {
936 nvidia,pins = "dvfs_pwm_px0";
937 nvidia,function = "cldvfs";
938 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
939 nvidia,tristate = <TEGRA_PIN_DISABLE>;
940 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
941 };
942 gpio_x1_aud_px1 {
943 nvidia,pins = "gpio_x1_aud_px1";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]944 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]945 nvidia,tristate = <TEGRA_PIN_ENABLE>;
946 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]947 };
948 dvfs_clk_px2 {
949 nvidia,pins = "dvfs_clk_px2";
950 nvidia,function = "cldvfs";
951 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
952 nvidia,tristate = <TEGRA_PIN_DISABLE>;
953 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
954 };
955 gpio_x3_aud_px3 {
956 nvidia,pins = "gpio_x3_aud_px3";
957 nvidia,function = "rsvd4";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]958 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
959 nvidia,tristate = <TEGRA_PIN_ENABLE>;
960 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]961 };
962 gpio_x4_aud_px4 {
963 nvidia,pins = "gpio_x4_aud_px4";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]964 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]965 nvidia,tristate = <TEGRA_PIN_ENABLE>;
966 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]967 };
968 gpio_x5_aud_px5 {
969 nvidia,pins = "gpio_x5_aud_px5";
970 nvidia,function = "rsvd4";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]971 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
972 nvidia,tristate = <TEGRA_PIN_ENABLE>;
973 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]974 };
975 gpio_x6_aud_px6 {
976 nvidia,pins = "gpio_x6_aud_px6";
977 nvidia,function = "gmi";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]978 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
979 nvidia,tristate = <TEGRA_PIN_ENABLE>;
980 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]981 };
982 gpio_x7_aud_px7 {
983 nvidia,pins = "gpio_x7_aud_px7";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]984 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
985 nvidia,tristate = <TEGRA_PIN_DISABLE>;
986 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
987 };
988 ulpi_clk_py0 {
989 nvidia,pins = "ulpi_clk_py0";
990 nvidia,function = "spi1";
991 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
992 nvidia,tristate = <TEGRA_PIN_DISABLE>;
993 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
994 };
995 ulpi_dir_py1 {
996 nvidia,pins = "ulpi_dir_py1";
997 nvidia,function = "spi1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]998 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
999 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1000 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1001 };
1002 ulpi_nxt_py2 {
1003 nvidia,pins = "ulpi_nxt_py2";
1004 nvidia,function = "spi1";
1005 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1006 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1007 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1008 };
1009 ulpi_stp_py3 {
1010 nvidia,pins = "ulpi_stp_py3";
1011 nvidia,function = "spi1";
1012 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1013 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1014 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1015 };
1016 sdmmc1_dat3_py4 {
1017 nvidia,pins = "sdmmc1_dat3_py4";
1018 nvidia,function = "sdmmc1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1019 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1020 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1021 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1022 };
1023 sdmmc1_dat2_py5 {
1024 nvidia,pins = "sdmmc1_dat2_py5";
1025 nvidia,function = "sdmmc1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1026 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1027 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1028 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1029 };
1030 sdmmc1_dat1_py6 {
1031 nvidia,pins = "sdmmc1_dat1_py6";
1032 nvidia,function = "sdmmc1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1033 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1034 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1035 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1036 };
1037 sdmmc1_dat0_py7 {
1038 nvidia,pins = "sdmmc1_dat0_py7";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1039 nvidia,function = "rsvd2";
1040 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1041 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1042 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1043 };
1044 sdmmc1_clk_pz0 {
1045 nvidia,pins = "sdmmc1_clk_pz0";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1046 nvidia,function = "rsvd3";
1047 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1048 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1049 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1050 };
1051 sdmmc1_cmd_pz1 {
1052 nvidia,pins = "sdmmc1_cmd_pz1";
1053 nvidia,function = "sdmmc1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1054 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1055 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1056 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1057 };
1058 pwr_i2c_scl_pz6 {
1059 nvidia,pins = "pwr_i2c_scl_pz6";
1060 nvidia,function = "i2cpwr";
1061 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1062 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1063 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1064 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
1065 };
1066 pwr_i2c_sda_pz7 {
1067 nvidia,pins = "pwr_i2c_sda_pz7";
1068 nvidia,function = "i2cpwr";
1069 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1070 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1071 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1072 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
1073 };
1074 sdmmc4_dat0_paa0 {
1075 nvidia,pins = "sdmmc4_dat0_paa0";
1076 nvidia,function = "sdmmc4";
1077 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1078 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1079 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1080 };
1081 sdmmc4_dat1_paa1 {
1082 nvidia,pins = "sdmmc4_dat1_paa1";
1083 nvidia,function = "sdmmc4";
1084 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1085 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1086 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1087 };
1088 sdmmc4_dat2_paa2 {
1089 nvidia,pins = "sdmmc4_dat2_paa2";
1090 nvidia,function = "sdmmc4";
1091 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1092 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1093 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1094 };
1095 sdmmc4_dat3_paa3 {
1096 nvidia,pins = "sdmmc4_dat3_paa3";
1097 nvidia,function = "sdmmc4";
1098 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1099 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1100 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1101 };
1102 sdmmc4_dat4_paa4 {
1103 nvidia,pins = "sdmmc4_dat4_paa4";
1104 nvidia,function = "sdmmc4";
1105 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1106 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1107 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1108 };
1109 sdmmc4_dat5_paa5 {
1110 nvidia,pins = "sdmmc4_dat5_paa5";
1111 nvidia,function = "sdmmc4";
1112 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1113 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1114 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1115 };
1116 sdmmc4_dat6_paa6 {
1117 nvidia,pins = "sdmmc4_dat6_paa6";
1118 nvidia,function = "sdmmc4";
1119 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1120 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1121 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1122 };
1123 sdmmc4_dat7_paa7 {
1124 nvidia,pins = "sdmmc4_dat7_paa7";
1125 nvidia,function = "sdmmc4";
1126 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1127 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1128 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1129 };
1130 pbb0 {
1131 nvidia,pins = "pbb0";
1132 nvidia,function = "vimclk2_alt";
1133 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1134 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1135 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1136 };
1137 cam_i2c_scl_pbb1 {
1138 nvidia,pins = "cam_i2c_scl_pbb1";
1139 nvidia,function = "i2c3";
1140 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1141 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1142 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1143 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
1144 };
1145 cam_i2c_sda_pbb2 {
1146 nvidia,pins = "cam_i2c_sda_pbb2";
1147 nvidia,function = "i2c3";
1148 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1149 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1150 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1151 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
1152 };
1153 pbb3 {
1154 nvidia,pins = "pbb3";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1155 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1156 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1157 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1158 };
1159 pbb4 {
1160 nvidia,pins = "pbb4";
1161 nvidia,function = "vgp4";
1162 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1163 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1164 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1165 };
1166 pbb5 {
1167 nvidia,pins = "pbb5";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1168 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1169 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1170 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1171 };
1172 pbb6 {
1173 nvidia,pins = "pbb6";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1174 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1175 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1176 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1177 };
1178 pbb7 {
1179 nvidia,pins = "pbb7";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1180 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1181 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1182 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1183 };
1184 cam_mclk_pcc0 {
1185 nvidia,pins = "cam_mclk_pcc0";
1186 nvidia,function = "vi_alt3";
1187 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1188 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1189 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1190 };
1191 pcc1 {
1192 nvidia,pins = "pcc1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1193 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1194 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1195 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1196 };
1197 pcc2 {
1198 nvidia,pins = "pcc2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1199 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1200 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1201 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1202 };
1203 sdmmc4_clk_pcc4 {
1204 nvidia,pins = "sdmmc4_clk_pcc4";
1205 nvidia,function = "sdmmc4";
1206 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1207 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1208 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1209 };
1210 clk2_req_pcc5 {
1211 nvidia,pins = "clk2_req_pcc5";
1212 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1213 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1214 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1215 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1216 };
Stephen Warrenb0da12d2014-08-22 15:07:13 -0600[diff] [blame]1217 pex_l0_rst_n_pdd1 {
1218 nvidia,pins = "pex_l0_rst_n_pdd1";
1219 nvidia,function = "pe0";
1220 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1221 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1222 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1223 };
1224 pex_l0_clkreq_n_pdd2 {
1225 nvidia,pins = "pex_l0_clkreq_n_pdd2";
1226 nvidia,function = "pe0";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1227 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1228 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenb0da12d2014-08-22 15:07:13 -0600[diff] [blame]1229 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1230 };
1231 pex_wake_n_pdd3 {
1232 nvidia,pins = "pex_wake_n_pdd3";
1233 nvidia,function = "pe";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1234 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1235 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenb0da12d2014-08-22 15:07:13 -0600[diff] [blame]1236 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1237 };
1238 pex_l1_rst_n_pdd5 {
1239 nvidia,pins = "pex_l1_rst_n_pdd5";
1240 nvidia,function = "pe1";
1241 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1242 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1243 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1244 };
1245 pex_l1_clkreq_n_pdd6 {
1246 nvidia,pins = "pex_l1_clkreq_n_pdd6";
1247 nvidia,function = "pe1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1248 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1249 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenb0da12d2014-08-22 15:07:13 -0600[diff] [blame]1250 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1251 };
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1252 clk3_out_pee0 {
1253 nvidia,pins = "clk3_out_pee0";
1254 nvidia,function = "extperiph3";
1255 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1256 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1257 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1258 };
1259 clk3_req_pee1 {
1260 nvidia,pins = "clk3_req_pee1";
1261 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1262 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1263 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1264 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1265 };
1266 dap_mclk1_req_pee2 {
1267 nvidia,pins = "dap_mclk1_req_pee2";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1268 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1269 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1270 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1271 };
1272 hdmi_cec_pee3 {
1273 nvidia,pins = "hdmi_cec_pee3";
1274 nvidia,function = "cec";
1275 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1276 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1277 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1278 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1279 };
1280 sdmmc3_clk_lb_out_pee4 {
1281 nvidia,pins = "sdmmc3_clk_lb_out_pee4";
1282 nvidia,function = "sdmmc3";
1283 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1284 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1285 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1286 };
1287 sdmmc3_clk_lb_in_pee5 {
1288 nvidia,pins = "sdmmc3_clk_lb_in_pee5";
1289 nvidia,function = "sdmmc3";
1290 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1291 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1292 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1293 };
1294 dp_hpd_pff0 {
1295 nvidia,pins = "dp_hpd_pff0";
1296 nvidia,function = "dp";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1297 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1298 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1299 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1300 };
1301 usb_vbus_en2_pff1 {
1302 nvidia,pins = "usb_vbus_en2_pff1";
1303 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1304 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1305 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1306 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1307 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1308 };
1309 pff2 {
1310 nvidia,pins = "pff2";
1311 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1312 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1313 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1314 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1315 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1316 };
1317 core_pwr_req {
1318 nvidia,pins = "core_pwr_req";
1319 nvidia,function = "pwron";
1320 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1321 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1322 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1323 };
1324 cpu_pwr_req {
1325 nvidia,pins = "cpu_pwr_req";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1326 nvidia,function = "cpu";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1327 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1328 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1329 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1330 };
1331 pwr_int_n {
1332 nvidia,pins = "pwr_int_n";
1333 nvidia,function = "pmi";
1334 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1335 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1336 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1337 };
1338 reset_out_n {
1339 nvidia,pins = "reset_out_n";
1340 nvidia,function = "reset_out_n";
1341 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1342 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1343 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1344 };
1345 owr {
1346 nvidia,pins = "owr";
1347 nvidia,function = "rsvd2";
1348 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1349 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1350 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1351 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
1352 };
1353 clk_32k_in {
1354 nvidia,pins = "clk_32k_in";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1355 nvidia,function = "clk";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1356 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1357 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1358 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1359 };
1360 jtag_rtck {
1361 nvidia,pins = "jtag_rtck";
1362 nvidia,function = "rtck";
1363 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1364 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1365 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1366 };
1367 };
1368 };
1369
1370 /* DB9 serial port */
1371 serial@0,70006300 {
1372 status = "okay";
1373 };
1374
1375 /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */
1376 i2c@0,7000c000 {
1377 status = "okay";
1378 clock-frequency = <100000>;
1379
Stephen Warren98de7442014-04-25 10:12:42 -0600[diff] [blame]1380 rt5639: audio-codec@1c {
1381 compatible = "realtek,rt5639";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1382 reg = <0x1c>;
1383 interrupt-parent = <&gpio>;
1384 interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
1385 realtek,ldo1-en-gpios =
1386 <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
1387 };
1388
1389 temperature-sensor@4c {
1390 compatible = "ti,tmp451";
1391 reg = <0x4c>;
1392 interrupt-parent = <&gpio>;
1393 interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
1394 };
1395
1396 eeprom@56 {
1397 compatible = "atmel,24c02";
1398 reg = <0x56>;
1399 pagesize = <8>;
1400 };
1401 };
1402
1403 /* Expansion GEN2_I2C_* */
1404 i2c@0,7000c400 {
1405 status = "okay";
1406 clock-frequency = <100000>;
1407 };
1408
1409 /* Expansion CAM_I2C_* */
1410 i2c@0,7000c500 {
1411 status = "okay";
1412 clock-frequency = <100000>;
1413 };
1414
1415 /* HDMI DDC */
Thierry Reding6054dd32014-04-25 17:44:47 +0200[diff] [blame]1416 hdmi_ddc: i2c@0,7000c700 {
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1417 status = "okay";
1418 clock-frequency = <100000>;
1419 };
1420
1421 /* Expansion PWR_I2C_*, on-board components */
1422 i2c@0,7000d000 {
1423 status = "okay";
1424 clock-frequency = <400000>;
1425
1426 pmic: pmic@40 {
1427 compatible = "ams,as3722";
1428 reg = <0x40>;
1429 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
1430
1431 ams,system-power-controller;
1432
1433 #interrupt-cells = <2>;
1434 interrupt-controller;
1435
1436 gpio-controller;
1437 #gpio-cells = <2>;
1438
1439 pinctrl-names = "default";
1440 pinctrl-0 = <&as3722_default>;
1441
1442 as3722_default: pinmux {
1443 gpio0 {
1444 pins = "gpio0";
1445 function = "gpio";
1446 bias-pull-down;
1447 };
1448
1449 gpio1_2_4_7 {
1450 pins = "gpio1", "gpio2", "gpio4", "gpio7";
1451 function = "gpio";
1452 bias-pull-up;
1453 };
1454
1455 gpio3_5_6 {
1456 pins = "gpio3", "gpio5", "gpio6";
1457 bias-high-impedance;
1458 };
1459 };
Stephen Warren22b35772014-03-24 18:04:43 -0600[diff] [blame]1460
1461 regulators {
1462 vsup-sd2-supply = <&vdd_5v0_sys>;
1463 vsup-sd3-supply = <&vdd_5v0_sys>;
1464 vsup-sd4-supply = <&vdd_5v0_sys>;
1465 vsup-sd5-supply = <&vdd_5v0_sys>;
1466 vin-ldo0-supply = <&vdd_1v35_lp0>;
1467 vin-ldo1-6-supply = <&vdd_3v3_run>;
1468 vin-ldo2-5-7-supply = <&vddio_1v8>;
1469 vin-ldo3-4-supply = <&vdd_3v3_sys>;
1470 vin-ldo9-10-supply = <&vdd_5v0_sys>;
1471 vin-ldo11-supply = <&vdd_3v3_run>;
1472
Tuomas Tynkkynen9be1e472015-05-13 17:58:45 +0300[diff] [blame]1473 vdd_cpu: sd0 {
Stephen Warren22b35772014-03-24 18:04:43 -0600[diff] [blame]1474 regulator-name = "+VDD_CPU_AP";
1475 regulator-min-microvolt = <700000>;
1476 regulator-max-microvolt = <1400000>;
1477 regulator-min-microamp = <3500000>;
1478 regulator-max-microamp = <3500000>;
1479 regulator-always-on;
1480 regulator-boot-on;
Tuomas Tynkkynenee913f72014-07-09 21:53:17 +0300[diff] [blame]1481 ams,ext-control = <2>;
Stephen Warren22b35772014-03-24 18:04:43 -0600[diff] [blame]1482 };
1483
1484 sd1 {
1485 regulator-name = "+VDD_CORE";
1486 regulator-min-microvolt = <700000>;
1487 regulator-max-microvolt = <1350000>;
1488 regulator-min-microamp = <2500000>;
1489 regulator-max-microamp = <2500000>;
1490 regulator-always-on;
1491 regulator-boot-on;
Tuomas Tynkkynenee913f72014-07-09 21:53:17 +0300[diff] [blame]1492 ams,ext-control = <1>;
Stephen Warren22b35772014-03-24 18:04:43 -0600[diff] [blame]1493 };
1494
1495 vdd_1v35_lp0: sd2 {
1496 regulator-name = "+1.35V_LP0(sd2)";
1497 regulator-min-microvolt = <1350000>;
1498 regulator-max-microvolt = <1350000>;
1499 regulator-always-on;
1500 regulator-boot-on;
1501 };
1502
1503 sd3 {
1504 regulator-name = "+1.35V_LP0(sd3)";
1505 regulator-min-microvolt = <1350000>;
1506 regulator-max-microvolt = <1350000>;
1507 regulator-always-on;
1508 regulator-boot-on;
1509 };
1510
Thierry Reding6054dd32014-04-25 17:44:47 +0200[diff] [blame]1511 vdd_1v05_run: sd4 {
Stephen Warren22b35772014-03-24 18:04:43 -0600[diff] [blame]1512 regulator-name = "+1.05V_RUN";
1513 regulator-min-microvolt = <1050000>;
1514 regulator-max-microvolt = <1050000>;
1515 };
1516
1517 vddio_1v8: sd5 {
1518 regulator-name = "+1.8V_VDDIO";
1519 regulator-min-microvolt = <1800000>;
1520 regulator-max-microvolt = <1800000>;
1521 regulator-boot-on;
1522 regulator-always-on;
1523 };
1524
Alexandre Courbot21fa1962015-07-01 18:13:47 +0900[diff] [blame]1525 vdd_gpu: sd6 {
Stephen Warren22b35772014-03-24 18:04:43 -0600[diff] [blame]1526 regulator-name = "+VDD_GPU_AP";
1527 regulator-min-microvolt = <650000>;
1528 regulator-max-microvolt = <1200000>;
1529 regulator-min-microamp = <3500000>;
1530 regulator-max-microamp = <3500000>;
1531 regulator-boot-on;
1532 regulator-always-on;
1533 };
1534
Thierry Reding8e2b9e42014-09-17 10:02:45 -0600[diff] [blame]1535 avdd_1v05_run: ldo0 {
Stephen Warren22b35772014-03-24 18:04:43 -0600[diff] [blame]1536 regulator-name = "+1.05V_RUN_AVDD";
1537 regulator-min-microvolt = <1050000>;
1538 regulator-max-microvolt = <1050000>;
1539 regulator-boot-on;
1540 regulator-always-on;
Tuomas Tynkkynenee913f72014-07-09 21:53:17 +0300[diff] [blame]1541 ams,ext-control = <1>;
Stephen Warren22b35772014-03-24 18:04:43 -0600[diff] [blame]1542 };
1543
1544 ldo1 {
1545 regulator-name = "+1.8V_RUN_CAM";
1546 regulator-min-microvolt = <1800000>;
1547 regulator-max-microvolt = <1800000>;
1548 };
1549
1550 ldo2 {
1551 regulator-name = "+1.2V_GEN_AVDD";
1552 regulator-min-microvolt = <1200000>;
1553 regulator-max-microvolt = <1200000>;
1554 regulator-boot-on;
1555 regulator-always-on;
1556 };
1557
1558 ldo3 {
1559 regulator-name = "+1.05V_LP0_VDD_RTC";
1560 regulator-min-microvolt = <1000000>;
1561 regulator-max-microvolt = <1000000>;
1562 regulator-boot-on;
1563 regulator-always-on;
1564 ams,enable-tracking;
1565 };
1566
1567 ldo4 {
1568 regulator-name = "+2.8V_RUN_CAM";
1569 regulator-min-microvolt = <2800000>;
1570 regulator-max-microvolt = <2800000>;
1571 };
1572
1573 ldo5 {
1574 regulator-name = "+1.2V_RUN_CAM_FRONT";
1575 regulator-min-microvolt = <1200000>;
1576 regulator-max-microvolt = <1200000>;
1577 };
1578
1579 vddio_sdmmc3: ldo6 {
1580 regulator-name = "+VDDIO_SDMMC3";
1581 regulator-min-microvolt = <1800000>;
1582 regulator-max-microvolt = <3300000>;
1583 };
1584
1585 ldo7 {
1586 regulator-name = "+1.05V_RUN_CAM_REAR";
1587 regulator-min-microvolt = <1050000>;
1588 regulator-max-microvolt = <1050000>;
1589 };
1590
1591 ldo9 {
1592 regulator-name = "+3.3V_RUN_TOUCH";
1593 regulator-min-microvolt = <2800000>;
1594 regulator-max-microvolt = <2800000>;
1595 };
1596
1597 ldo10 {
1598 regulator-name = "+2.8V_RUN_CAM_AF";
1599 regulator-min-microvolt = <2800000>;
1600 regulator-max-microvolt = <2800000>;
1601 };
1602
1603 ldo11 {
1604 regulator-name = "+1.8V_RUN_VPP_FUSE";
1605 regulator-min-microvolt = <1800000>;
1606 regulator-max-microvolt = <1800000>;
1607 };
1608 };
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1609 };
1610 };
1611
1612 /* Expansion TS_SPI_* */
1613 spi@0,7000d400 {
1614 status = "okay";
1615 };
1616
1617 /* Internal SPI */
1618 spi@0,7000da00 {
1619 status = "okay";
1620 spi-max-frequency = <25000000>;
1621 spi-flash@0 {
1622 compatible = "winbond,w25q32dw";
1623 reg = <0>;
1624 spi-max-frequency = <20000000>;
1625 };
1626 };
1627
1628 pmc@0,7000e400 {
1629 nvidia,invert-interrupt;
1630 nvidia,suspend-mode = <1>;
1631 nvidia,cpu-pwr-good-time = <500>;
1632 nvidia,cpu-pwr-off-time = <300>;
1633 nvidia,core-pwr-good-time = <641 3845>;
1634 nvidia,core-pwr-off-time = <61036>;
1635 nvidia,core-power-req-active-high;
1636 nvidia,sys-clock-req-active-high;
Mikko Perttunen9c963302015-01-06 12:52:57 +0200[diff] [blame]1637
1638 i2c-thermtrip {
1639 nvidia,i2c-controller-id = <4>;
1640 nvidia,bus-addr = <0x40>;
1641 nvidia,reg-addr = <0x36>;
1642 nvidia,reg-data = <0x2>;
1643 };
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1644 };
1645
Mikko Perttunen1b3ce992014-07-16 11:54:18 +0300[diff] [blame]1646 /* Serial ATA */
1647 sata@0,70020000 {
1648 status = "okay";
1649
1650 hvdd-supply = <&vdd_3v3_lp0>;
1651 vddio-supply = <&vdd_1v05_run>;
1652 avdd-supply = <&vdd_1v05_run>;
1653
1654 target-5v-supply = <&vdd_5v0_sata>;
1655 target-12v-supply = <&vdd_12v0_sata>;
1656 };
1657
Thierry Reding4c844722014-05-22 09:38:31 +0200[diff] [blame]1658 hda@0,70030000 {
1659 status = "okay";
1660 };
1661
Thierry Reding62b8db02014-06-19 13:37:10 +0200[diff] [blame]1662 padctl@0,7009f000 {
1663 pinctrl-0 = <&padctl_default>;
1664 pinctrl-names = "default";
1665
1666 padctl_default: pinmux {
1667 usb3 {
1668 nvidia,lanes = "pcie-0", "pcie-1";
1669 nvidia,function = "usb3";
1670 nvidia,iddq = <0>;
1671 };
1672
1673 pcie {
1674 nvidia,lanes = "pcie-2", "pcie-3",
1675 "pcie-4";
1676 nvidia,function = "pcie";
1677 nvidia,iddq = <0>;
1678 };
1679
1680 sata {
1681 nvidia,lanes = "sata-0";
1682 nvidia,function = "sata";
1683 nvidia,iddq = <0>;
1684 };
1685 };
1686 };
1687
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1688 /* SD card */
1689 sdhci@0,700b0400 {
1690 status = "okay";
1691 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
1692 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
Stephen Warren215f21c2014-04-28 11:05:57 -0600[diff] [blame]1693 wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1694 bus-width = <4>;
Stephen Warren92607642014-04-16 10:34:18 -0600[diff] [blame]1695 vqmmc-supply = <&vddio_sdmmc3>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1696 };
1697
1698 /* eMMC */
1699 sdhci@0,700b0600 {
1700 status = "okay";
1701 bus-width = <8>;
Lucas Stach33f34f02014-06-03 14:48:46 +0200[diff] [blame]1702 non-removable;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1703 };
1704
Tuomas Tynkkynen9be1e472015-05-13 17:58:45 +0300[diff] [blame]1705 /* CPU DFLL clock */
1706 clock@0,70110000 {
1707 status = "okay";
1708 vdd-cpu-supply = <&vdd_cpu>;
1709 nvidia,i2c-fs-rate = <400000>;
1710 };
1711
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1712 ahub@0,70300000 {
1713 i2s@0,70301100 {
1714 status = "okay";
1715 };
1716 };
1717
1718 /* mini-PCIe USB */
1719 usb@0,7d004000 {
1720 status = "okay";
1721 };
1722
1723 usb-phy@0,7d004000 {
1724 status = "okay";
1725 };
1726
1727 /* USB A connector */
1728 usb@0,7d008000 {
1729 status = "okay";
1730 };
1731
1732 usb-phy@0,7d008000 {
1733 status = "okay";
1734 vbus-supply = <&vdd_usb3_vbus>;
1735 };
1736
1737 clocks {
1738 compatible = "simple-bus";
1739 #address-cells = <1>;
1740 #size-cells = <0>;
1741
1742 clk32k_in: clock@0 {
1743 compatible = "fixed-clock";
1744 reg = <0>;
1745 #clock-cells = <0>;
1746 clock-frequency = <32768>;
1747 };
1748 };
1749
Mikko Perttunenee9f1062015-05-13 17:58:50 +0300[diff] [blame]1750 cpus {
1751 cpu@0 {
1752 vdd-cpu-supply = <&vdd_cpu>;
1753 };
1754 };
1755
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1756 gpio-keys {
1757 compatible = "gpio-keys";
1758
1759 power {
1760 label = "Power";
1761 gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
1762 linux,code = <KEY_POWER>;
1763 debounce-interval = <10>;
1764 gpio-key,wakeup;
1765 };
1766 };
1767
1768 regulators {
1769 compatible = "simple-bus";
1770 #address-cells = <1>;
1771 #size-cells = <0>;
1772
Stephen Warren22b35772014-03-24 18:04:43 -0600[diff] [blame]1773 vdd_mux: regulator@0 {
1774 compatible = "regulator-fixed";
1775 reg = <0>;
1776 regulator-name = "+VDD_MUX";
1777 regulator-min-microvolt = <12000000>;
1778 regulator-max-microvolt = <12000000>;
1779 regulator-always-on;
1780 regulator-boot-on;
1781 };
1782
1783 vdd_5v0_sys: regulator@1 {
1784 compatible = "regulator-fixed";
1785 reg = <1>;
1786 regulator-name = "+5V_SYS";
1787 regulator-min-microvolt = <5000000>;
1788 regulator-max-microvolt = <5000000>;
1789 regulator-always-on;
1790 regulator-boot-on;
1791 vin-supply = <&vdd_mux>;
1792 };
1793
1794 vdd_3v3_sys: regulator@2 {
1795 compatible = "regulator-fixed";
1796 reg = <2>;
1797 regulator-name = "+3.3V_SYS";
1798 regulator-min-microvolt = <3300000>;
1799 regulator-max-microvolt = <3300000>;
1800 regulator-always-on;
1801 regulator-boot-on;
1802 vin-supply = <&vdd_mux>;
1803 };
1804
1805 vdd_3v3_run: regulator@3 {
1806 compatible = "regulator-fixed";
1807 reg = <3>;
1808 regulator-name = "+3.3V_RUN";
1809 regulator-min-microvolt = <3300000>;
1810 regulator-max-microvolt = <3300000>;
1811 regulator-always-on;
1812 regulator-boot-on;
1813 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
1814 enable-active-high;
1815 vin-supply = <&vdd_3v3_sys>;
1816 };
1817
1818 vdd_3v3_hdmi: regulator@4 {
1819 compatible = "regulator-fixed";
1820 reg = <4>;
1821 regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
1822 regulator-min-microvolt = <3300000>;
1823 regulator-max-microvolt = <3300000>;
1824 vin-supply = <&vdd_3v3_run>;
1825 };
1826
1827 vdd_usb1_vbus: regulator@7 {
1828 compatible = "regulator-fixed";
1829 reg = <7>;
1830 regulator-name = "+USB0_VBUS_SW";
1831 regulator-min-microvolt = <5000000>;
1832 regulator-max-microvolt = <5000000>;
1833 gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
1834 enable-active-high;
1835 gpio-open-drain;
1836 vin-supply = <&vdd_5v0_sys>;
1837 };
1838
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1839 vdd_usb3_vbus: regulator@8 {
1840 compatible = "regulator-fixed";
1841 reg = <8>;
1842 regulator-name = "+5V_USB_HS";
1843 regulator-min-microvolt = <5000000>;
1844 regulator-max-microvolt = <5000000>;
1845 gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
1846 enable-active-high;
1847 gpio-open-drain;
Stephen Warren22b35772014-03-24 18:04:43 -0600[diff] [blame]1848 vin-supply = <&vdd_5v0_sys>;
1849 };
1850
1851 vdd_3v3_lp0: regulator@10 {
1852 compatible = "regulator-fixed";
1853 reg = <10>;
1854 regulator-name = "+3.3V_LP0";
1855 regulator-min-microvolt = <3300000>;
1856 regulator-max-microvolt = <3300000>;
1857 regulator-always-on;
1858 regulator-boot-on;
1859 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
1860 enable-active-high;
1861 vin-supply = <&vdd_3v3_sys>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1862 };
Thierry Reding6054dd32014-04-25 17:44:47 +0200[diff] [blame]1863
1864 vdd_hdmi_pll: regulator@11 {
1865 compatible = "regulator-fixed";
1866 reg = <11>;
1867 regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
1868 regulator-min-microvolt = <1050000>;
1869 regulator-max-microvolt = <1050000>;
1870 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
1871 vin-supply = <&vdd_1v05_run>;
1872 };
1873
1874 vdd_5v0_hdmi: regulator@12 {
1875 compatible = "regulator-fixed";
1876 reg = <12>;
1877 regulator-name = "+5V_HDMI_CON";
1878 regulator-min-microvolt = <5000000>;
1879 regulator-max-microvolt = <5000000>;
1880 gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
1881 enable-active-high;
1882 vin-supply = <&vdd_5v0_sys>;
1883 };
Mikko Perttunen1b3ce992014-07-16 11:54:18 +0300[diff] [blame]1884
1885 /* Molex power connector */
1886 vdd_5v0_sata: regulator@13 {
1887 compatible = "regulator-fixed";
1888 reg = <13>;
1889 regulator-name = "+5V_SATA";
1890 regulator-min-microvolt = <5000000>;
1891 regulator-max-microvolt = <5000000>;
1892 gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
1893 enable-active-high;
1894 vin-supply = <&vdd_5v0_sys>;
1895 };
1896
1897 vdd_12v0_sata: regulator@14 {
1898 compatible = "regulator-fixed";
1899 reg = <14>;
1900 regulator-name = "+12V_SATA";
1901 regulator-min-microvolt = <12000000>;
1902 regulator-max-microvolt = <12000000>;
1903 gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
1904 enable-active-high;
1905 vin-supply = <&vdd_mux>;
1906 };
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1907 };
1908
1909 sound {
1910 compatible = "nvidia,tegra-audio-rt5640-jetson-tk1",
1911 "nvidia,tegra-audio-rt5640";
1912 nvidia,model = "NVIDIA Tegra Jetson TK1";
1913
1914 nvidia,audio-routing =
1915 "Headphones", "HPOR",
1916 "Headphones", "HPOL",
1917 "Mic Jack", "MICBIAS1",
1918 "IN2P", "Mic Jack";
1919
1920 nvidia,i2s-controller = <&tegra_i2s1>;
Stephen Warren98de7442014-04-25 10:12:42 -0600[diff] [blame]1921 nvidia,audio-codec = <&rt5639>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1922
1923 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>;
1924
1925 clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
1926 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
1927 <&tegra_car TEGRA124_CLK_EXTERN1>;
1928 clock-names = "pll_a", "pll_a_out0", "mclk";
1929 };
Mikko Perttunened7eac32014-09-26 12:43:12 +0300[diff] [blame]1930
1931 thermal-zones {
1932 cpu {
1933 trips {
1934 trip@0 {
1935 temperature = <101000>;
1936 hysteresis = <0>;
1937 type = "critical";
1938 };
1939 };
1940
1941 cooling-maps {
1942 /* There are currently no cooling maps because there are no cooling devices */
1943 };
1944 };
1945
1946 mem {
1947 trips {
1948 trip@0 {
1949 temperature = <101000>;
1950 hysteresis = <0>;
1951 type = "critical";
1952 };
1953 };
1954
1955 cooling-maps {
1956 /* There are currently no cooling maps because there are no cooling devices */
1957 };
1958 };
1959
1960 gpu {
1961 trips {
1962 trip@0 {
1963 temperature = <101000>;
1964 hysteresis = <0>;
1965 type = "critical";
1966 };
1967 };
1968
1969 cooling-maps {
1970 /* There are currently no cooling maps because there are no cooling devices */
1971 };
1972 };
1973 };
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1974};