| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /************************************************************************/ |
| 2 | /* */ |
| 3 | /* Title : RIO Host Card Hardware Definitions */ |
| 4 | /* */ |
| 5 | /* Author : N.P.Vassallo */ |
| 6 | /* */ |
| 7 | /* Creation : 26th April 1999 */ |
| 8 | /* */ |
| 9 | /* Version : 1.0.0 */ |
| 10 | /* */ |
| 11 | /* Copyright : (c) Specialix International Ltd. 1999 * |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or modify |
| 14 | * it under the terms of the GNU General Public License as published by |
| 15 | * the Free Software Foundation; either version 2 of the License, or |
| 16 | * (at your option) any later version. |
| 17 | * |
| 18 | * This program is distributed in the hope that it will be useful, |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 21 | * GNU General Public License for more details. |
| 22 | * |
| 23 | * You should have received a copy of the GNU General Public License |
| 24 | * along with this program; if not, write to the Free Software |
| 25 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 26 | * */ |
| 27 | /* Description : Prototypes, structures and definitions */ |
| 28 | /* describing the RIO board hardware */ |
| 29 | /* */ |
| 30 | /************************************************************************/ |
| 31 | |
| 32 | /* History... |
| 33 | |
| 34 | 1.0.0 26/04/99 NPV Creation. |
| 35 | |
| 36 | */ |
| 37 | |
| 38 | #ifndef _rioboard_h /* If RIOBOARD.H not already defined */ |
| 39 | #define _rioboard_h 1 |
| 40 | |
| 41 | /***************************************************************************** |
| 42 | *********************** *********************** |
| 43 | *********************** Hardware Control Registers *********************** |
| 44 | *********************** *********************** |
| 45 | *****************************************************************************/ |
| 46 | |
| 47 | /* Hardware Registers... */ |
| 48 | |
| 49 | #define RIO_REG_BASE 0x7C00 /* Base of control registers */ |
| 50 | |
| 51 | #define RIO_CONFIG RIO_REG_BASE + 0x0000 /* WRITE: Configuration Register */ |
| 52 | #define RIO_INTSET RIO_REG_BASE + 0x0080 /* WRITE: Interrupt Set */ |
| 53 | #define RIO_RESET RIO_REG_BASE + 0x0100 /* WRITE: Host Reset */ |
| 54 | #define RIO_INTRESET RIO_REG_BASE + 0x0180 /* WRITE: Interrupt Reset */ |
| 55 | |
| 56 | #define RIO_VPD_ROM RIO_REG_BASE + 0x0000 /* READ: Vital Product Data ROM */ |
| 57 | #define RIO_INTSTAT RIO_REG_BASE + 0x0080 /* READ: Interrupt Status (Jet boards only) */ |
| 58 | #define RIO_RESETSTAT RIO_REG_BASE + 0x0100 /* READ: Reset Status (Jet boards only) */ |
| 59 | |
| 60 | /* RIO_VPD_ROM definitions... */ |
| 61 | #define VPD_SLX_ID1 0x00 /* READ: Specialix Identifier #1 */ |
| 62 | #define VPD_SLX_ID2 0x01 /* READ: Specialix Identifier #2 */ |
| 63 | #define VPD_HW_REV 0x02 /* READ: Hardware Revision */ |
| 64 | #define VPD_HW_ASSEM 0x03 /* READ: Hardware Assembly Level */ |
| 65 | #define VPD_UNIQUEID4 0x04 /* READ: Unique Identifier #4 */ |
| 66 | #define VPD_UNIQUEID3 0x05 /* READ: Unique Identifier #3 */ |
| 67 | #define VPD_UNIQUEID2 0x06 /* READ: Unique Identifier #2 */ |
| 68 | #define VPD_UNIQUEID1 0x07 /* READ: Unique Identifier #1 */ |
| 69 | #define VPD_MANU_YEAR 0x08 /* READ: Year Of Manufacture (0 = 1970) */ |
| 70 | #define VPD_MANU_WEEK 0x09 /* READ: Week Of Manufacture (0 = week 1 Jan) */ |
| 71 | #define VPD_HWFEATURE1 0x0A /* READ: Hardware Feature Byte 1 */ |
| 72 | #define VPD_HWFEATURE2 0x0B /* READ: Hardware Feature Byte 2 */ |
| 73 | #define VPD_HWFEATURE3 0x0C /* READ: Hardware Feature Byte 3 */ |
| 74 | #define VPD_HWFEATURE4 0x0D /* READ: Hardware Feature Byte 4 */ |
| 75 | #define VPD_HWFEATURE5 0x0E /* READ: Hardware Feature Byte 5 */ |
| 76 | #define VPD_OEMID 0x0F /* READ: OEM Identifier */ |
| 77 | #define VPD_IDENT 0x10 /* READ: Identifier string (16 bytes) */ |
| 78 | #define VPD_IDENT_LEN 0x10 |
| 79 | |
| 80 | /* VPD ROM Definitions... */ |
| 81 | #define SLX_ID1 0x4D |
| 82 | #define SLX_ID2 0x98 |
| 83 | |
| 84 | #define PRODUCT_ID(a) ((a>>4)&0xF) /* Use to obtain Product ID from VPD_UNIQUEID1 */ |
| 85 | |
| 86 | #define ID_SX_ISA 0x2 |
| 87 | #define ID_RIO_EISA 0x3 |
| 88 | #define ID_SX_PCI 0x5 |
| 89 | #define ID_SX_EISA 0x7 |
| 90 | #define ID_RIO_RTA16 0x9 |
| 91 | #define ID_RIO_ISA 0xA |
| 92 | #define ID_RIO_MCA 0xB |
| 93 | #define ID_RIO_SBUS 0xC |
| 94 | #define ID_RIO_PCI 0xD |
| 95 | #define ID_RIO_RTA8 0xE |
| 96 | |
| 97 | /* Transputer bootstrap definitions... */ |
| 98 | |
| 99 | #define BOOTLOADADDR (0x8000 - 6) |
| 100 | #define BOOTINDICATE (0x8000 - 2) |
| 101 | |
| 102 | /* Firmware load position... */ |
| 103 | |
| 104 | #define FIRMWARELOADADDR 0x7C00 /* Firmware is loaded _before_ this address */ |
| 105 | |
| 106 | /***************************************************************************** |
| 107 | ***************************** ***************************** |
| 108 | ***************************** RIO (Rev1) ISA ***************************** |
| 109 | ***************************** ***************************** |
| 110 | *****************************************************************************/ |
| 111 | |
| 112 | /* Control Register Definitions... */ |
| 113 | #define RIO_ISA_IDENT "JBJGPGGHINSMJPJR" |
| 114 | |
| 115 | #define RIO_ISA_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */ |
| 116 | #define RIO_ISA_CFG_BUSENABLE 0x02 /* Enable processor bus */ |
| 117 | #define RIO_ISA_CFG_IRQMASK 0x30 /* Interrupt mask */ |
| 118 | #define RIO_ISA_CFG_IRQ12 0x10 /* Interrupt Level 12 */ |
| 119 | #define RIO_ISA_CFG_IRQ11 0x20 /* Interrupt Level 11 */ |
| 120 | #define RIO_ISA_CFG_IRQ9 0x30 /* Interrupt Level 9 */ |
| 121 | #define RIO_ISA_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */ |
| 122 | #define RIO_ISA_CFG_WAITSTATE0 0x80 /* 0 waitstates, else 1 */ |
| 123 | |
| 124 | /***************************************************************************** |
| 125 | ***************************** ***************************** |
| 126 | ***************************** RIO (Rev2) ISA ***************************** |
| 127 | ***************************** ***************************** |
| 128 | *****************************************************************************/ |
| 129 | |
| 130 | /* Control Register Definitions... */ |
| 131 | #define RIO_ISA2_IDENT "JBJGPGGHINSMJPJR" |
| 132 | |
| 133 | #define RIO_ISA2_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */ |
| 134 | #define RIO_ISA2_CFG_BUSENABLE 0x02 /* Enable processor bus */ |
| 135 | #define RIO_ISA2_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */ |
| 136 | #define RIO_ISA2_CFG_16BIT 0x08 /* 16bit mode, else 8bit */ |
| 137 | #define RIO_ISA2_CFG_IRQMASK 0x30 /* Interrupt mask */ |
| 138 | #define RIO_ISA2_CFG_IRQ15 0x00 /* Interrupt Level 15 */ |
| 139 | #define RIO_ISA2_CFG_IRQ12 0x10 /* Interrupt Level 12 */ |
| 140 | #define RIO_ISA2_CFG_IRQ11 0x20 /* Interrupt Level 11 */ |
| 141 | #define RIO_ISA2_CFG_IRQ9 0x30 /* Interrupt Level 9 */ |
| 142 | #define RIO_ISA2_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */ |
| 143 | #define RIO_ISA2_CFG_WAITSTATE0 0x80 /* 0 waitstates, else 1 */ |
| 144 | |
| 145 | /***************************************************************************** |
| 146 | ***************************** ****************************** |
| 147 | ***************************** RIO (Jet) ISA ****************************** |
| 148 | ***************************** ****************************** |
| 149 | *****************************************************************************/ |
| 150 | |
| 151 | /* Control Register Definitions... */ |
| 152 | #define RIO_ISA3_IDENT "JET HOST BY KEV#" |
| 153 | |
| 154 | #define RIO_ISA3_CFG_BUSENABLE 0x02 /* Enable processor bus */ |
| 155 | #define RIO_ISA3_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */ |
| 156 | #define RIO_ISA32_CFG_IRQMASK 0xF30 /* Interrupt mask */ |
| 157 | #define RIO_ISA3_CFG_IRQ15 0xF0 /* Interrupt Level 15 */ |
| 158 | #define RIO_ISA3_CFG_IRQ12 0xC0 /* Interrupt Level 12 */ |
| 159 | #define RIO_ISA3_CFG_IRQ11 0xB0 /* Interrupt Level 11 */ |
| 160 | #define RIO_ISA3_CFG_IRQ10 0xA0 /* Interrupt Level 10 */ |
| 161 | #define RIO_ISA3_CFG_IRQ9 0x90 /* Interrupt Level 9 */ |
| 162 | |
| 163 | /***************************************************************************** |
| 164 | ********************************* ******************************** |
| 165 | ********************************* RIO MCA ******************************** |
| 166 | ********************************* ******************************** |
| 167 | *****************************************************************************/ |
| 168 | |
| 169 | /* Control Register Definitions... */ |
| 170 | #define RIO_MCA_IDENT "JBJGPGGHINSMJPJR" |
| 171 | |
| 172 | #define RIO_MCA_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */ |
| 173 | #define RIO_MCA_CFG_BUSENABLE 0x02 /* Enable processor bus */ |
| 174 | #define RIO_MCA_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */ |
| 175 | |
| 176 | /***************************************************************************** |
| 177 | ******************************** ******************************** |
| 178 | ******************************** RIO EISA ******************************** |
| 179 | ******************************** ******************************** |
| 180 | *****************************************************************************/ |
| 181 | |
| 182 | /* EISA Configuration Space Definitions... */ |
| 183 | #define EISA_PRODUCT_ID1 0xC80 |
| 184 | #define EISA_PRODUCT_ID2 0xC81 |
| 185 | #define EISA_PRODUCT_NUMBER 0xC82 |
| 186 | #define EISA_REVISION_NUMBER 0xC83 |
| 187 | #define EISA_CARD_ENABLE 0xC84 |
| 188 | #define EISA_VPD_UNIQUEID4 0xC88 /* READ: Unique Identifier #4 */ |
| 189 | #define EISA_VPD_UNIQUEID3 0xC8A /* READ: Unique Identifier #3 */ |
| 190 | #define EISA_VPD_UNIQUEID2 0xC90 /* READ: Unique Identifier #2 */ |
| 191 | #define EISA_VPD_UNIQUEID1 0xC92 /* READ: Unique Identifier #1 */ |
| 192 | #define EISA_VPD_MANU_YEAR 0xC98 /* READ: Year Of Manufacture (0 = 1970) */ |
| 193 | #define EISA_VPD_MANU_WEEK 0xC9A /* READ: Week Of Manufacture (0 = week 1 Jan) */ |
| 194 | #define EISA_MEM_ADDR_23_16 0xC00 |
| 195 | #define EISA_MEM_ADDR_31_24 0xC01 |
| 196 | #define EISA_RIO_CONFIG 0xC02 /* WRITE: Configuration Register */ |
| 197 | #define EISA_RIO_INTSET 0xC03 /* WRITE: Interrupt Set */ |
| 198 | #define EISA_RIO_INTRESET 0xC03 /* READ: Interrupt Reset */ |
| 199 | |
| 200 | /* Control Register Definitions... */ |
| 201 | #define RIO_EISA_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */ |
| 202 | #define RIO_EISA_CFG_LINK20 0x02 /* 20Mbps link, else 10Mbps */ |
| 203 | #define RIO_EISA_CFG_BUSENABLE 0x04 /* Enable processor bus */ |
| 204 | #define RIO_EISA_CFG_PROCRUN 0x08 /* Processor running, else reset */ |
| 205 | #define RIO_EISA_CFG_IRQMASK 0xF0 /* Interrupt mask */ |
| 206 | #define RIO_EISA_CFG_IRQ15 0xF0 /* Interrupt Level 15 */ |
| 207 | #define RIO_EISA_CFG_IRQ14 0xE0 /* Interrupt Level 14 */ |
| 208 | #define RIO_EISA_CFG_IRQ12 0xC0 /* Interrupt Level 12 */ |
| 209 | #define RIO_EISA_CFG_IRQ11 0xB0 /* Interrupt Level 11 */ |
| 210 | #define RIO_EISA_CFG_IRQ10 0xA0 /* Interrupt Level 10 */ |
| 211 | #define RIO_EISA_CFG_IRQ9 0x90 /* Interrupt Level 9 */ |
| 212 | #define RIO_EISA_CFG_IRQ7 0x70 /* Interrupt Level 7 */ |
| 213 | #define RIO_EISA_CFG_IRQ6 0x60 /* Interrupt Level 6 */ |
| 214 | #define RIO_EISA_CFG_IRQ5 0x50 /* Interrupt Level 5 */ |
| 215 | #define RIO_EISA_CFG_IRQ4 0x40 /* Interrupt Level 4 */ |
| 216 | #define RIO_EISA_CFG_IRQ3 0x30 /* Interrupt Level 3 */ |
| 217 | |
| 218 | /***************************************************************************** |
| 219 | ******************************** ******************************** |
| 220 | ******************************** RIO SBus ******************************** |
| 221 | ******************************** ******************************** |
| 222 | *****************************************************************************/ |
| 223 | |
| 224 | /* Control Register Definitions... */ |
| 225 | #define RIO_SBUS_IDENT "JBPGK#\0\0\0\0\0\0\0\0\0\0" |
| 226 | |
| 227 | #define RIO_SBUS_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */ |
| 228 | #define RIO_SBUS_CFG_BUSENABLE 0x02 /* Enable processor bus */ |
| 229 | #define RIO_SBUS_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */ |
| 230 | #define RIO_SBUS_CFG_IRQMASK 0x38 /* Interrupt mask */ |
| 231 | #define RIO_SBUS_CFG_IRQNONE 0x00 /* No Interrupt */ |
| 232 | #define RIO_SBUS_CFG_IRQ7 0x38 /* Interrupt Level 7 */ |
| 233 | #define RIO_SBUS_CFG_IRQ6 0x30 /* Interrupt Level 6 */ |
| 234 | #define RIO_SBUS_CFG_IRQ5 0x28 /* Interrupt Level 5 */ |
| 235 | #define RIO_SBUS_CFG_IRQ4 0x20 /* Interrupt Level 4 */ |
| 236 | #define RIO_SBUS_CFG_IRQ3 0x18 /* Interrupt Level 3 */ |
| 237 | #define RIO_SBUS_CFG_IRQ2 0x10 /* Interrupt Level 2 */ |
| 238 | #define RIO_SBUS_CFG_IRQ1 0x08 /* Interrupt Level 1 */ |
| 239 | #define RIO_SBUS_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */ |
| 240 | #define RIO_SBUS_CFG_PROC25 0x80 /* 25Mhz processor clock, else 20Mhz */ |
| 241 | |
| 242 | /***************************************************************************** |
| 243 | ********************************* ******************************** |
| 244 | ********************************* RIO PCI ******************************** |
| 245 | ********************************* ******************************** |
| 246 | *****************************************************************************/ |
| 247 | |
| 248 | /* Control Register Definitions... */ |
| 249 | #define RIO_PCI_IDENT "ECDDPGJGJHJRGSK#" |
| 250 | |
| 251 | #define RIO_PCI_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */ |
| 252 | #define RIO_PCI_CFG_BUSENABLE 0x02 /* Enable processor bus */ |
| 253 | #define RIO_PCI_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */ |
| 254 | #define RIO_PCI_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */ |
| 255 | #define RIO_PCI_CFG_PROC25 0x80 /* 25Mhz processor clock, else 20Mhz */ |
| 256 | |
| 257 | /* PCI Definitions... */ |
| 258 | #define SPX_VENDOR_ID 0x11CB /* Assigned by the PCI SIG */ |
| 259 | #define SPX_DEVICE_ID 0x8000 /* RIO bridge boards */ |
| 260 | #define SPX_PLXDEVICE_ID 0x2000 /* PLX bridge boards */ |
| 261 | #define SPX_SUB_VENDOR_ID SPX_VENDOR_ID /* Same as vendor id */ |
| 262 | #define RIO_SUB_SYS_ID 0x0800 /* RIO PCI board */ |
| 263 | |
| 264 | /***************************************************************************** |
| 265 | ***************************** ****************************** |
| 266 | ***************************** RIO (Jet) PCI ****************************** |
| 267 | ***************************** ****************************** |
| 268 | *****************************************************************************/ |
| 269 | |
| 270 | /* Control Register Definitions... */ |
| 271 | #define RIO_PCI2_IDENT "JET HOST BY KEV#" |
| 272 | |
| 273 | #define RIO_PCI2_CFG_BUSENABLE 0x02 /* Enable processor bus */ |
| 274 | #define RIO_PCI2_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */ |
| 275 | |
| 276 | /* PCI Definitions... */ |
| 277 | #define RIO2_SUB_SYS_ID 0x0100 /* RIO (Jet) PCI board */ |
| 278 | |
| 279 | #endif /*_rioboard_h */ |
| 280 | |
| 281 | /* End of RIOBOARD.H */ |