Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1 | #ifndef __MYRI10GE_MCP_H__ |
| 2 | #define __MYRI10GE_MCP_H__ |
| 3 | |
| 4 | #define MXGEFW_VERSION_MAJOR 1 |
| 5 | #define MXGEFW_VERSION_MINOR 4 |
| 6 | |
| 7 | /* 8 Bytes */ |
| 8 | struct mcp_dma_addr { |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 9 | __be32 high; |
| 10 | __be32 low; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 11 | }; |
| 12 | |
Brice Goglin | af793e0 | 2007-10-13 12:32:58 +0200 | [diff] [blame] | 13 | /* 4 Bytes. 8 Bytes for NDIS drivers. */ |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 14 | struct mcp_slot { |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 15 | __sum16 checksum; |
| 16 | __be16 length; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 17 | }; |
| 18 | |
| 19 | /* 64 Bytes */ |
| 20 | struct mcp_cmd { |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 21 | __be32 cmd; |
| 22 | __be32 data0; /* will be low portion if data > 32 bits */ |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 23 | /* 8 */ |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 24 | __be32 data1; /* will be high portion if data > 32 bits */ |
| 25 | __be32 data2; /* currently unused.. */ |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 26 | /* 16 */ |
| 27 | struct mcp_dma_addr response_addr; |
| 28 | /* 24 */ |
| 29 | u8 pad[40]; |
| 30 | }; |
| 31 | |
| 32 | /* 8 Bytes */ |
| 33 | struct mcp_cmd_response { |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 34 | __be32 data; |
| 35 | __be32 result; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 36 | }; |
| 37 | |
Jeff Garzik | 6ed1425 | 2006-05-24 00:28:37 -0400 | [diff] [blame] | 38 | /* |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 39 | * flags used in mcp_kreq_ether_send_t: |
Jeff Garzik | 6ed1425 | 2006-05-24 00:28:37 -0400 | [diff] [blame] | 40 | * |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 41 | * The SMALL flag is only needed in the first segment. It is raised |
| 42 | * for packets that are total less or equal 512 bytes. |
Jeff Garzik | 6ed1425 | 2006-05-24 00:28:37 -0400 | [diff] [blame] | 43 | * |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 44 | * The CKSUM flag must be set in all segments. |
Jeff Garzik | 6ed1425 | 2006-05-24 00:28:37 -0400 | [diff] [blame] | 45 | * |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 46 | * The PADDED flags is set if the packet needs to be padded, and it |
| 47 | * must be set for all segments. |
Jeff Garzik | 6ed1425 | 2006-05-24 00:28:37 -0400 | [diff] [blame] | 48 | * |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 49 | * The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative |
| 50 | * length of all previous segments was odd. |
| 51 | */ |
| 52 | |
| 53 | #define MXGEFW_FLAGS_SMALL 0x1 |
| 54 | #define MXGEFW_FLAGS_TSO_HDR 0x1 |
| 55 | #define MXGEFW_FLAGS_FIRST 0x2 |
| 56 | #define MXGEFW_FLAGS_ALIGN_ODD 0x4 |
| 57 | #define MXGEFW_FLAGS_CKSUM 0x8 |
| 58 | #define MXGEFW_FLAGS_TSO_LAST 0x8 |
| 59 | #define MXGEFW_FLAGS_NO_TSO 0x10 |
| 60 | #define MXGEFW_FLAGS_TSO_CHOP 0x10 |
| 61 | #define MXGEFW_FLAGS_TSO_PLD 0x20 |
| 62 | |
| 63 | #define MXGEFW_SEND_SMALL_SIZE 1520 |
| 64 | #define MXGEFW_MAX_MTU 9400 |
| 65 | |
| 66 | union mcp_pso_or_cumlen { |
| 67 | u16 pseudo_hdr_offset; |
| 68 | u16 cum_len; |
| 69 | }; |
| 70 | |
| 71 | #define MXGEFW_MAX_SEND_DESC 12 |
| 72 | #define MXGEFW_PAD 2 |
| 73 | |
| 74 | /* 16 Bytes */ |
| 75 | struct mcp_kreq_ether_send { |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 76 | __be32 addr_high; |
| 77 | __be32 addr_low; |
| 78 | __be16 pseudo_hdr_offset; |
| 79 | __be16 length; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 80 | u8 pad; |
| 81 | u8 rdma_count; |
| 82 | u8 cksum_offset; /* where to start computing cksum */ |
| 83 | u8 flags; /* as defined above */ |
| 84 | }; |
| 85 | |
| 86 | /* 8 Bytes */ |
| 87 | struct mcp_kreq_ether_recv { |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 88 | __be32 addr_high; |
| 89 | __be32 addr_low; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 90 | }; |
| 91 | |
| 92 | /* Commands */ |
| 93 | |
Brice Goglin | e700f9f | 2006-08-14 17:52:54 -0400 | [diff] [blame] | 94 | #define MXGEFW_BOOT_HANDOFF 0xfc0000 |
| 95 | #define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0 |
| 96 | |
| 97 | #define MXGEFW_ETH_CMD 0xf80000 |
| 98 | #define MXGEFW_ETH_SEND_4 0x200000 |
| 99 | #define MXGEFW_ETH_SEND_1 0x240000 |
| 100 | #define MXGEFW_ETH_SEND_2 0x280000 |
| 101 | #define MXGEFW_ETH_SEND_3 0x2c0000 |
| 102 | #define MXGEFW_ETH_RECV_SMALL 0x300000 |
| 103 | #define MXGEFW_ETH_RECV_BIG 0x340000 |
| 104 | |
| 105 | #define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000)) |
| 106 | #define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 107 | |
| 108 | enum myri10ge_mcp_cmd_type { |
| 109 | MXGEFW_CMD_NONE = 0, |
| 110 | /* Reset the mcp, it is left in a safe state, waiting |
| 111 | * for the driver to set all its parameters */ |
| 112 | MXGEFW_CMD_RESET, |
| 113 | |
| 114 | /* get the version number of the current firmware.. |
| 115 | * (may be available in the eeprom strings..? */ |
| 116 | MXGEFW_GET_MCP_VERSION, |
| 117 | |
| 118 | /* Parameters which must be set by the driver before it can |
| 119 | * issue MXGEFW_CMD_ETHERNET_UP. They persist until the next |
| 120 | * MXGEFW_CMD_RESET is issued */ |
| 121 | |
| 122 | MXGEFW_CMD_SET_INTRQ_DMA, |
| 123 | MXGEFW_CMD_SET_BIG_BUFFER_SIZE, /* in bytes, power of 2 */ |
| 124 | MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, /* in bytes */ |
| 125 | |
Jeff Garzik | 6ed1425 | 2006-05-24 00:28:37 -0400 | [diff] [blame] | 126 | /* Parameters which refer to lanai SRAM addresses where the |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 127 | * driver must issue PIO writes for various things */ |
| 128 | |
| 129 | MXGEFW_CMD_GET_SEND_OFFSET, |
| 130 | MXGEFW_CMD_GET_SMALL_RX_OFFSET, |
| 131 | MXGEFW_CMD_GET_BIG_RX_OFFSET, |
| 132 | MXGEFW_CMD_GET_IRQ_ACK_OFFSET, |
| 133 | MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, |
| 134 | |
| 135 | /* Parameters which refer to rings stored on the MCP, |
| 136 | * and whose size is controlled by the mcp */ |
| 137 | |
| 138 | MXGEFW_CMD_GET_SEND_RING_SIZE, /* in bytes */ |
| 139 | MXGEFW_CMD_GET_RX_RING_SIZE, /* in bytes */ |
| 140 | |
| 141 | /* Parameters which refer to rings stored in the host, |
| 142 | * and whose size is controlled by the host. Note that |
Jeff Garzik | 6ed1425 | 2006-05-24 00:28:37 -0400 | [diff] [blame] | 143 | * all must be physically contiguous and must contain |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 144 | * a power of 2 number of entries. */ |
| 145 | |
| 146 | MXGEFW_CMD_SET_INTRQ_SIZE, /* in bytes */ |
| 147 | |
| 148 | /* command to bring ethernet interface up. Above parameters |
| 149 | * (plus mtu & mac address) must have been exchanged prior |
| 150 | * to issuing this command */ |
| 151 | MXGEFW_CMD_ETHERNET_UP, |
| 152 | |
| 153 | /* command to bring ethernet interface down. No further sends |
| 154 | * or receives may be processed until an MXGEFW_CMD_ETHERNET_UP |
| 155 | * is issued, and all interrupt queues must be flushed prior |
| 156 | * to ack'ing this command */ |
| 157 | |
| 158 | MXGEFW_CMD_ETHERNET_DOWN, |
| 159 | |
| 160 | /* commands the driver may issue live, without resetting |
| 161 | * the nic. Note that increasing the mtu "live" should |
| 162 | * only be done if the driver has already supplied buffers |
| 163 | * sufficiently large to handle the new mtu. Decreasing |
| 164 | * the mtu live is safe */ |
| 165 | |
| 166 | MXGEFW_CMD_SET_MTU, |
| 167 | MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, /* in microseconds */ |
| 168 | MXGEFW_CMD_SET_STATS_INTERVAL, /* in microseconds */ |
Brice Goglin | 85a7ea1 | 2006-08-21 17:36:56 -0400 | [diff] [blame] | 169 | MXGEFW_CMD_SET_STATS_DMA_OBSOLETE, /* replaced by SET_STATS_DMA_V2 */ |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 170 | |
| 171 | MXGEFW_ENABLE_PROMISC, |
| 172 | MXGEFW_DISABLE_PROMISC, |
| 173 | MXGEFW_SET_MAC_ADDRESS, |
| 174 | |
| 175 | MXGEFW_ENABLE_FLOW_CONTROL, |
| 176 | MXGEFW_DISABLE_FLOW_CONTROL, |
| 177 | |
| 178 | /* do a DMA test |
| 179 | * data0,data1 = DMA address |
| 180 | * data2 = RDMA length (MSH), WDMA length (LSH) |
| 181 | * command return data = repetitions (MSH), 0.5-ms ticks (LSH) |
| 182 | */ |
Brice Goglin | 85a7ea1 | 2006-08-21 17:36:56 -0400 | [diff] [blame] | 183 | MXGEFW_DMA_TEST, |
| 184 | |
| 185 | MXGEFW_ENABLE_ALLMULTI, |
| 186 | MXGEFW_DISABLE_ALLMULTI, |
| 187 | |
| 188 | /* returns MXGEFW_CMD_ERROR_MULTICAST |
| 189 | * if there is no room in the cache |
| 190 | * data0,MSH(data1) = multicast group address */ |
| 191 | MXGEFW_JOIN_MULTICAST_GROUP, |
| 192 | /* returns MXGEFW_CMD_ERROR_MULTICAST |
| 193 | * if the address is not in the cache, |
| 194 | * or is equal to FF-FF-FF-FF-FF-FF |
| 195 | * data0,MSH(data1) = multicast group address */ |
| 196 | MXGEFW_LEAVE_MULTICAST_GROUP, |
| 197 | MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, |
| 198 | |
| 199 | MXGEFW_CMD_SET_STATS_DMA_V2, |
| 200 | /* data0, data1 = bus addr, |
| 201 | * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows |
| 202 | * adding new stuff to mcp_irq_data without changing the ABI */ |
Brice Goglin | 772a815 | 2007-05-07 23:49:59 +0200 | [diff] [blame] | 203 | |
| 204 | MXGEFW_CMD_UNALIGNED_TEST, |
| 205 | /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned |
| 206 | * chipset */ |
| 207 | |
Brice Goglin | af793e0 | 2007-10-13 12:32:58 +0200 | [diff] [blame] | 208 | MXGEFW_CMD_UNALIGNED_STATUS, |
| 209 | /* return data = boolean, true if the chipset is known to be unaligned */ |
| 210 | |
| 211 | MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS, |
| 212 | /* data0 = number of big buffers to use. It must be 0 or a power of 2. |
| 213 | * 0 indicates that the NIC consumes as many buffers as they are required |
| 214 | * for packet. This is the default behavior. |
| 215 | * A power of 2 number indicates that the NIC always uses the specified |
| 216 | * number of buffers for each big receive packet. |
| 217 | * It is up to the driver to ensure that this value is big enough for |
| 218 | * the NIC to be able to receive maximum-sized packets. |
| 219 | */ |
| 220 | |
| 221 | MXGEFW_CMD_GET_MAX_RSS_QUEUES, |
| 222 | MXGEFW_CMD_ENABLE_RSS_QUEUES, |
| 223 | /* data0 = number of slices n (0, 1, ..., n-1) to enable |
| 224 | * data1 = interrupt mode. 0=share one INTx/MSI, 1=use one MSI-X per queue. |
| 225 | * If all queues share one interrupt, the driver must have set |
| 226 | * RSS_SHARED_INTERRUPT_DMA before enabling queues. |
| 227 | */ |
| 228 | MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET, |
| 229 | MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA, |
| 230 | /* data0, data1 = bus address lsw, msw */ |
| 231 | MXGEFW_CMD_GET_RSS_TABLE_OFFSET, |
| 232 | /* get the offset of the indirection table */ |
| 233 | MXGEFW_CMD_SET_RSS_TABLE_SIZE, |
| 234 | /* set the size of the indirection table */ |
| 235 | MXGEFW_CMD_GET_RSS_KEY_OFFSET, |
| 236 | /* get the offset of the secret key */ |
| 237 | MXGEFW_CMD_RSS_KEY_UPDATED, |
| 238 | /* tell nic that the secret key's been updated */ |
| 239 | MXGEFW_CMD_SET_RSS_ENABLE, |
| 240 | /* data0 = enable/disable rss |
| 241 | * 0: disable rss. nic does not distribute receive packets. |
| 242 | * 1: enable rss. nic distributes receive packets among queues. |
| 243 | * data1 = hash type |
| 244 | * 1: IPV4 |
| 245 | * 2: TCP_IPV4 |
| 246 | * 3: IPV4 | TCP_IPV4 |
| 247 | */ |
| 248 | |
| 249 | MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE, |
| 250 | /* Return data = the max. size of the entire headers of a IPv6 TSO packet. |
| 251 | * If the header size of a IPv6 TSO packet is larger than the specified |
| 252 | * value, then the driver must not use TSO. |
| 253 | * This size restriction only applies to IPv6 TSO. |
| 254 | * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC |
| 255 | * always has enough header buffer to store maximum-sized headers. |
| 256 | */ |
| 257 | |
| 258 | MXGEFW_CMD_SET_TSO_MODE, |
| 259 | /* data0 = TSO mode. |
| 260 | * 0: Linux/FreeBSD style (NIC default) |
| 261 | * 1: NDIS/NetBSD style |
| 262 | */ |
| 263 | |
| 264 | MXGEFW_CMD_MDIO_READ, |
| 265 | /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */ |
| 266 | MXGEFW_CMD_MDIO_WRITE, |
| 267 | /* data0 = dev_addr, data1 = register/addr, data2 = value */ |
| 268 | |
| 269 | MXGEFW_CMD_XFP_I2C_READ, |
| 270 | /* Starts to get a fresh copy of one byte or of the whole xfp i2c table, the |
| 271 | * obtained data is cached inside the xaui-xfi chip : |
| 272 | * data0 : "all" flag : 0 => get one byte, 1=> get 256 bytes, |
| 273 | * data1 : if (data0 == 0): index of byte to refresh [ not used otherwise ] |
| 274 | * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes |
| 275 | * During the i2c operation, MXGEFW_CMD_XFP_I2C_READ or MXGEFW_CMD_XFP_BYTE attempts |
| 276 | * will return MXGEFW_CMD_ERROR_BUSY |
| 277 | */ |
| 278 | MXGEFW_CMD_XFP_BYTE, |
| 279 | /* Return the last obtained copy of a given byte in the xfp i2c table |
| 280 | * (copy cached during the last relevant MXGEFW_CMD_XFP_I2C_READ) |
| 281 | * data0 : index of the desired table entry |
| 282 | * Return data = the byte stored at the requested index in the table |
| 283 | */ |
| 284 | |
| 285 | MXGEFW_CMD_GET_VPUMP_OFFSET, |
| 286 | /* Return data = NIC memory offset of mcp_vpump_public_global */ |
| 287 | MXGEFW_CMD_RESET_VPUMP, |
| 288 | /* Resets the VPUMP state */ |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 289 | }; |
| 290 | |
| 291 | enum myri10ge_mcp_cmd_status { |
| 292 | MXGEFW_CMD_OK = 0, |
| 293 | MXGEFW_CMD_UNKNOWN, |
| 294 | MXGEFW_CMD_ERROR_RANGE, |
| 295 | MXGEFW_CMD_ERROR_BUSY, |
| 296 | MXGEFW_CMD_ERROR_EMPTY, |
| 297 | MXGEFW_CMD_ERROR_CLOSED, |
| 298 | MXGEFW_CMD_ERROR_HASH_ERROR, |
| 299 | MXGEFW_CMD_ERROR_BAD_PORT, |
Brice Goglin | 85a7ea1 | 2006-08-21 17:36:56 -0400 | [diff] [blame] | 300 | MXGEFW_CMD_ERROR_RESOURCES, |
Brice Goglin | 772a815 | 2007-05-07 23:49:59 +0200 | [diff] [blame] | 301 | MXGEFW_CMD_ERROR_MULTICAST, |
Brice Goglin | af793e0 | 2007-10-13 12:32:58 +0200 | [diff] [blame] | 302 | MXGEFW_CMD_ERROR_UNALIGNED, |
| 303 | MXGEFW_CMD_ERROR_NO_MDIO, |
| 304 | MXGEFW_CMD_ERROR_XFP_FAILURE, |
| 305 | MXGEFW_CMD_ERROR_XFP_ABSENT |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 306 | }; |
| 307 | |
Brice Goglin | 85a7ea1 | 2006-08-21 17:36:56 -0400 | [diff] [blame] | 308 | #define MXGEFW_OLD_IRQ_DATA_LEN 40 |
| 309 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 310 | struct mcp_irq_data { |
Brice Goglin | 85a7ea1 | 2006-08-21 17:36:56 -0400 | [diff] [blame] | 311 | /* add new counters at the beginning */ |
Brice Goglin | cee505d | 2007-05-07 23:49:25 +0200 | [diff] [blame] | 312 | __be32 future_use[1]; |
| 313 | __be32 dropped_pause; |
| 314 | __be32 dropped_unicast_filtered; |
| 315 | __be32 dropped_bad_crc32; |
| 316 | __be32 dropped_bad_phy; |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 317 | __be32 dropped_multicast_filtered; |
Brice Goglin | 85a7ea1 | 2006-08-21 17:36:56 -0400 | [diff] [blame] | 318 | /* 40 Bytes */ |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 319 | __be32 send_done_count; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 320 | |
Brice Goglin | 772a815 | 2007-05-07 23:49:59 +0200 | [diff] [blame] | 321 | #define MXGEFW_LINK_DOWN 0 |
| 322 | #define MXGEFW_LINK_UP 1 |
| 323 | #define MXGEFW_LINK_MYRINET 2 |
| 324 | #define MXGEFW_LINK_UNKNOWN 3 |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 325 | __be32 link_up; |
| 326 | __be32 dropped_link_overflow; |
| 327 | __be32 dropped_link_error_or_filtered; |
| 328 | __be32 dropped_runt; |
| 329 | __be32 dropped_overrun; |
| 330 | __be32 dropped_no_small_buffer; |
| 331 | __be32 dropped_no_big_buffer; |
| 332 | __be32 rdma_tags_available; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 333 | |
| 334 | u8 tx_stopped; |
| 335 | u8 link_down; |
| 336 | u8 stats_updated; |
| 337 | u8 valid; |
| 338 | }; |
| 339 | |
| 340 | #endif /* __MYRI10GE_MCP_H__ */ |