blob: c5ddd937dbf21a438af2cbe8fb0f2c385b88a774 [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
Sergei Shtylyovd44a65f2007-08-10 20:58:46 +040011 * Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
Jeff Garzik669a5db2006-08-29 18:12:40 -040012 *
13 * TODO
Sergei Shtylyovd44a65f2007-08-10 20:58:46 +040014 * Look into engine reset on timeout errors. Should not be required.
Jeff Garzik669a5db2006-08-29 18:12:40 -040015 */
16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/pci.h>
20#include <linux/init.h>
21#include <linux/blkdev.h>
22#include <linux/delay.h>
23#include <scsi/scsi_host.h>
24#include <linux/libata.h>
25
26#define DRV_NAME "pata_hpt37x"
Sergei Shtylyov80b89872007-08-10 21:02:15 +040027#define DRV_VERSION "0.6.9"
Jeff Garzik669a5db2006-08-29 18:12:40 -040028
29struct hpt_clock {
30 u8 xfer_speed;
31 u32 timing;
32};
33
34struct hpt_chip {
35 const char *name;
36 unsigned int base;
37 struct hpt_clock const *clocks[4];
38};
39
40/* key for bus clock timings
41 * bit
42 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
43 * DMA. cycles = value + 1
44 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
45 * DMA. cycles = value + 1
46 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
47 * register access.
48 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
49 * register access.
50 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
51 * during task file register access.
52 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
53 * xfer.
54 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
55 * register access.
56 * 28 UDMA enable
57 * 29 DMA enable
58 * 30 PIO_MST enable. if set, the chip is in bus master mode during
59 * PIO.
60 * 31 FIFO enable.
61 */
62
Alan Coxfcc2f692007-03-08 23:28:52 +000063static struct hpt_clock hpt37x_timings_33[] = {
64 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */
65 { XFER_UDMA_5, 0x12446231 },
66 { XFER_UDMA_4, 0x12446231 },
67 { XFER_UDMA_3, 0x126c6231 },
68 { XFER_UDMA_2, 0x12486231 },
69 { XFER_UDMA_1, 0x124c6233 },
70 { XFER_UDMA_0, 0x12506297 },
Jeff Garzik669a5db2006-08-29 18:12:40 -040071
Alan Coxfcc2f692007-03-08 23:28:52 +000072 { XFER_MW_DMA_2, 0x22406c31 },
73 { XFER_MW_DMA_1, 0x22406c33 },
74 { XFER_MW_DMA_0, 0x22406c97 },
Jeff Garzik669a5db2006-08-29 18:12:40 -040075
Alan Coxfcc2f692007-03-08 23:28:52 +000076 { XFER_PIO_4, 0x06414e31 },
77 { XFER_PIO_3, 0x06414e42 },
78 { XFER_PIO_2, 0x06414e53 },
79 { XFER_PIO_1, 0x06814e93 },
80 { XFER_PIO_0, 0x06814ea7 }
Jeff Garzik669a5db2006-08-29 18:12:40 -040081};
82
Alan Coxfcc2f692007-03-08 23:28:52 +000083static struct hpt_clock hpt37x_timings_50[] = {
84 { XFER_UDMA_6, 0x12848242 },
85 { XFER_UDMA_5, 0x12848242 },
86 { XFER_UDMA_4, 0x12ac8242 },
87 { XFER_UDMA_3, 0x128c8242 },
88 { XFER_UDMA_2, 0x120c8242 },
89 { XFER_UDMA_1, 0x12148254 },
90 { XFER_UDMA_0, 0x121882ea },
Jeff Garzik669a5db2006-08-29 18:12:40 -040091
Alan Coxfcc2f692007-03-08 23:28:52 +000092 { XFER_MW_DMA_2, 0x22808242 },
93 { XFER_MW_DMA_1, 0x22808254 },
94 { XFER_MW_DMA_0, 0x228082ea },
Jeff Garzik669a5db2006-08-29 18:12:40 -040095
Alan Coxfcc2f692007-03-08 23:28:52 +000096 { XFER_PIO_4, 0x0a81f442 },
97 { XFER_PIO_3, 0x0a81f443 },
98 { XFER_PIO_2, 0x0a81f454 },
99 { XFER_PIO_1, 0x0ac1f465 },
100 { XFER_PIO_0, 0x0ac1f48a }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400101};
102
Alan Coxfcc2f692007-03-08 23:28:52 +0000103static struct hpt_clock hpt37x_timings_66[] = {
104 { XFER_UDMA_6, 0x1c869c62 },
105 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */
106 { XFER_UDMA_4, 0x1c8a9c62 },
107 { XFER_UDMA_3, 0x1c8e9c62 },
108 { XFER_UDMA_2, 0x1c929c62 },
109 { XFER_UDMA_1, 0x1c9a9c62 },
110 { XFER_UDMA_0, 0x1c829c62 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400111
Alan Coxfcc2f692007-03-08 23:28:52 +0000112 { XFER_MW_DMA_2, 0x2c829c62 },
113 { XFER_MW_DMA_1, 0x2c829c66 },
114 { XFER_MW_DMA_0, 0x2c829d2e },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400115
Alan Coxfcc2f692007-03-08 23:28:52 +0000116 { XFER_PIO_4, 0x0c829c62 },
117 { XFER_PIO_3, 0x0c829c84 },
118 { XFER_PIO_2, 0x0c829ca6 },
119 { XFER_PIO_1, 0x0d029d26 },
120 { XFER_PIO_0, 0x0d029d5e }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400121};
122
Jeff Garzik669a5db2006-08-29 18:12:40 -0400123
124static const struct hpt_chip hpt370 = {
125 "HPT370",
126 48,
127 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000128 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400129 NULL,
130 NULL,
Alan Coxa4734462007-04-26 00:19:25 -0700131 NULL
Jeff Garzik669a5db2006-08-29 18:12:40 -0400132 }
133};
134
135static const struct hpt_chip hpt370a = {
136 "HPT370A",
137 48,
138 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000139 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400140 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000141 hpt37x_timings_50,
Alan Coxa4734462007-04-26 00:19:25 -0700142 NULL
Jeff Garzik669a5db2006-08-29 18:12:40 -0400143 }
144};
145
146static const struct hpt_chip hpt372 = {
147 "HPT372",
148 55,
149 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000150 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400151 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000152 hpt37x_timings_50,
153 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400154 }
155};
156
157static const struct hpt_chip hpt302 = {
158 "HPT302",
159 66,
160 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000161 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400162 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000163 hpt37x_timings_50,
164 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400165 }
166};
167
168static const struct hpt_chip hpt371 = {
169 "HPT371",
170 66,
171 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000172 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400173 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000174 hpt37x_timings_50,
175 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400176 }
177};
178
179static const struct hpt_chip hpt372a = {
180 "HPT372A",
181 66,
182 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000183 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400184 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000185 hpt37x_timings_50,
186 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400187 }
188};
189
190static const struct hpt_chip hpt374 = {
191 "HPT374",
192 48,
193 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000194 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400195 NULL,
196 NULL,
197 NULL
198 }
199};
200
201/**
202 * hpt37x_find_mode - reset the hpt37x bus
203 * @ap: ATA port
204 * @speed: transfer mode
205 *
206 * Return the 32bit register programming information for this channel
207 * that matches the speed provided.
208 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400209
Jeff Garzik669a5db2006-08-29 18:12:40 -0400210static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
211{
212 struct hpt_clock *clocks = ap->host->private_data;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400213
Jeff Garzik669a5db2006-08-29 18:12:40 -0400214 while(clocks->xfer_speed) {
215 if (clocks->xfer_speed == speed)
216 return clocks->timing;
217 clocks++;
218 }
219 BUG();
220 return 0xffffffffU; /* silence compiler warning */
221}
222
223static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
224{
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900225 unsigned char model_num[ATA_ID_PROD_LEN + 1];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400226 int i = 0;
227
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900228 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400229
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900230 while (list[i] != NULL) {
231 if (!strcmp(list[i], model_num)) {
Jeff Garzik85cd7252006-08-31 00:03:49 -0400232 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
Jeff Garzik669a5db2006-08-29 18:12:40 -0400233 modestr, list[i]);
234 return 1;
235 }
236 i++;
237 }
238 return 0;
239}
240
241static const char *bad_ata33[] = {
242 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
243 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
244 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
245 "Maxtor 90510D4",
246 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
247 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
248 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
249 NULL
250};
251
252static const char *bad_ata100_5[] = {
253 "IBM-DTLA-307075",
254 "IBM-DTLA-307060",
255 "IBM-DTLA-307045",
256 "IBM-DTLA-307030",
257 "IBM-DTLA-307020",
258 "IBM-DTLA-307015",
259 "IBM-DTLA-305040",
260 "IBM-DTLA-305030",
261 "IBM-DTLA-305020",
262 "IC35L010AVER07-0",
263 "IC35L020AVER07-0",
264 "IC35L030AVER07-0",
265 "IC35L040AVER07-0",
266 "IC35L060AVER07-0",
267 "WDC AC310200R",
268 NULL
269};
270
271/**
272 * hpt370_filter - mode selection filter
Jeff Garzik669a5db2006-08-29 18:12:40 -0400273 * @adev: ATA device
274 *
275 * Block UDMA on devices that cause trouble with this controller.
276 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400277
Alan Coxa76b62c2007-03-09 09:34:07 -0500278static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400279{
Alan6929da42007-01-05 16:37:01 -0800280 if (adev->class == ATA_DEV_ATA) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400281 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
282 mask &= ~ATA_MASK_UDMA;
283 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
284 mask &= ~(0x1F << ATA_SHIFT_UDMA);
285 }
Alan Coxa76b62c2007-03-09 09:34:07 -0500286 return ata_pci_default_filter(adev, mask);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400287}
288
289/**
290 * hpt370a_filter - mode selection filter
Jeff Garzik669a5db2006-08-29 18:12:40 -0400291 * @adev: ATA device
292 *
293 * Block UDMA on devices that cause trouble with this controller.
294 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400295
Alan Coxa76b62c2007-03-09 09:34:07 -0500296static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400297{
298 if (adev->class != ATA_DEV_ATA) {
299 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
300 mask &= ~ (0x1F << ATA_SHIFT_UDMA);
301 }
Alan Coxa76b62c2007-03-09 09:34:07 -0500302 return ata_pci_default_filter(adev, mask);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400303}
Jeff Garzik85cd7252006-08-31 00:03:49 -0400304
Jeff Garzik669a5db2006-08-29 18:12:40 -0400305/**
306 * hpt37x_pre_reset - reset the hpt37x bus
307 * @ap: ATA port to reset
Tejun Heod4b2bab2007-02-02 16:50:52 +0900308 * @deadline: deadline jiffies for the operation
Jeff Garzik669a5db2006-08-29 18:12:40 -0400309 *
310 * Perform the initial reset handling for the 370/372 and 374 func 0
311 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400312
Tejun Heod4b2bab2007-02-02 16:50:52 +0900313static int hpt37x_pre_reset(struct ata_port *ap, unsigned long deadline)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400314{
315 u8 scr2, ata66;
316 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Alan Coxb5bf24b2006-11-08 16:18:26 +0000317 static const struct pci_bits hpt37x_enable_bits[] = {
318 { 0x50, 1, 0x04, 0x04 },
319 { 0x54, 1, 0x04, 0x04 }
320 };
321 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
322 return -ENOENT;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500323
Jeff Garzik669a5db2006-08-29 18:12:40 -0400324 pci_read_config_byte(pdev, 0x5B, &scr2);
325 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
326 /* Cable register now active */
327 pci_read_config_byte(pdev, 0x5A, &ata66);
328 /* Restore state */
329 pci_write_config_byte(pdev, 0x5B, scr2);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400330
Jeff Garzik669a5db2006-08-29 18:12:40 -0400331 if (ata66 & (1 << ap->port_no))
332 ap->cbl = ATA_CBL_PATA40;
333 else
334 ap->cbl = ATA_CBL_PATA80;
335
336 /* Reset the state machine */
Alan Coxfcc2f692007-03-08 23:28:52 +0000337 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400338 udelay(100);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400339
Tejun Heod4b2bab2007-02-02 16:50:52 +0900340 return ata_std_prereset(ap, deadline);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400341}
342
343/**
344 * hpt37x_error_handler - reset the hpt374
345 * @ap: ATA port to reset
346 *
347 * Perform probe for HPT37x, except for HPT374 channel 2
348 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400349
Jeff Garzik669a5db2006-08-29 18:12:40 -0400350static void hpt37x_error_handler(struct ata_port *ap)
351{
352 ata_bmdma_drive_eh(ap, hpt37x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
353}
354
Tejun Heod4b2bab2007-02-02 16:50:52 +0900355static int hpt374_pre_reset(struct ata_port *ap, unsigned long deadline)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400356{
Alan Coxb5bf24b2006-11-08 16:18:26 +0000357 static const struct pci_bits hpt37x_enable_bits[] = {
358 { 0x50, 1, 0x04, 0x04 },
359 { 0x54, 1, 0x04, 0x04 }
360 };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400361 u16 mcr3, mcr6;
362 u8 ata66;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400363 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Alan Coxb5bf24b2006-11-08 16:18:26 +0000364
365 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
366 return -ENOENT;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500367
Jeff Garzik669a5db2006-08-29 18:12:40 -0400368 /* Do the extra channel work */
369 pci_read_config_word(pdev, 0x52, &mcr3);
370 pci_read_config_word(pdev, 0x56, &mcr6);
371 /* Set bit 15 of 0x52 to enable TCBLID as input
372 Set bit 15 of 0x56 to enable FCBLID as input
373 */
374 pci_write_config_word(pdev, 0x52, mcr3 | 0x8000);
375 pci_write_config_word(pdev, 0x56, mcr6 | 0x8000);
376 pci_read_config_byte(pdev, 0x5A, &ata66);
377 /* Reset TCBLID/FCBLID to output */
378 pci_write_config_word(pdev, 0x52, mcr3);
379 pci_write_config_word(pdev, 0x56, mcr6);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400380
Jeff Garzik669a5db2006-08-29 18:12:40 -0400381 if (ata66 & (1 << ap->port_no))
382 ap->cbl = ATA_CBL_PATA40;
383 else
384 ap->cbl = ATA_CBL_PATA80;
385
386 /* Reset the state machine */
Alan Coxfcc2f692007-03-08 23:28:52 +0000387 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400388 udelay(100);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400389
Tejun Heod4b2bab2007-02-02 16:50:52 +0900390 return ata_std_prereset(ap, deadline);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400391}
392
393/**
394 * hpt374_error_handler - reset the hpt374
395 * @classes:
396 *
397 * The 374 cable detect is a little different due to the extra
398 * channels. The function 0 channels work like usual but function 1
399 * is special
400 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400401
Jeff Garzik669a5db2006-08-29 18:12:40 -0400402static void hpt374_error_handler(struct ata_port *ap)
403{
404 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400405
Jeff Garzik669a5db2006-08-29 18:12:40 -0400406 if (!(PCI_FUNC(pdev->devfn) & 1))
407 hpt37x_error_handler(ap);
408 else
409 ata_bmdma_drive_eh(ap, hpt374_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
410}
411
412/**
413 * hpt370_set_piomode - PIO setup
414 * @ap: ATA interface
415 * @adev: device on the interface
416 *
Jeff Garzik85cd7252006-08-31 00:03:49 -0400417 * Perform PIO mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400418 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400419
Jeff Garzik669a5db2006-08-29 18:12:40 -0400420static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
421{
422 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
423 u32 addr1, addr2;
424 u32 reg;
425 u32 mode;
426 u8 fast;
427
428 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
429 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400430
Jeff Garzik669a5db2006-08-29 18:12:40 -0400431 /* Fast interrupt prediction disable, hold off interrupt disable */
432 pci_read_config_byte(pdev, addr2, &fast);
433 fast &= ~0x02;
434 fast |= 0x01;
435 pci_write_config_byte(pdev, addr2, fast);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400436
Jeff Garzik669a5db2006-08-29 18:12:40 -0400437 pci_read_config_dword(pdev, addr1, &reg);
438 mode = hpt37x_find_mode(ap, adev->pio_mode);
439 mode &= ~0x8000000; /* No FIFO in PIO */
440 mode &= ~0x30070000; /* Leave config bits alone */
441 reg &= 0x30070000; /* Strip timing bits */
442 pci_write_config_dword(pdev, addr1, reg | mode);
443}
444
445/**
446 * hpt370_set_dmamode - DMA timing setup
447 * @ap: ATA interface
448 * @adev: Device being configured
449 *
450 * Set up the channel for MWDMA or UDMA modes. Much the same as with
451 * PIO, load the mode number and then set MWDMA or UDMA flag.
452 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400453
Jeff Garzik669a5db2006-08-29 18:12:40 -0400454static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
455{
456 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
457 u32 addr1, addr2;
458 u32 reg;
459 u32 mode;
460 u8 fast;
461
462 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
463 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400464
Jeff Garzik669a5db2006-08-29 18:12:40 -0400465 /* Fast interrupt prediction disable, hold off interrupt disable */
466 pci_read_config_byte(pdev, addr2, &fast);
467 fast &= ~0x02;
468 fast |= 0x01;
469 pci_write_config_byte(pdev, addr2, fast);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400470
Jeff Garzik669a5db2006-08-29 18:12:40 -0400471 pci_read_config_dword(pdev, addr1, &reg);
472 mode = hpt37x_find_mode(ap, adev->dma_mode);
473 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
474 mode &= ~0xC0000000; /* Leave config bits alone */
475 reg &= 0xC0000000; /* Strip timing bits */
476 pci_write_config_dword(pdev, addr1, reg | mode);
477}
478
479/**
480 * hpt370_bmdma_start - DMA engine begin
481 * @qc: ATA command
482 *
483 * The 370 and 370A want us to reset the DMA engine each time we
484 * use it. The 372 and later are fine.
485 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400486
Jeff Garzik669a5db2006-08-29 18:12:40 -0400487static void hpt370_bmdma_start(struct ata_queued_cmd *qc)
488{
489 struct ata_port *ap = qc->ap;
490 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
491 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
492 udelay(10);
493 ata_bmdma_start(qc);
494}
495
496/**
497 * hpt370_bmdma_end - DMA engine stop
498 * @qc: ATA command
499 *
500 * Work around the HPT370 DMA engine.
501 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400502
Jeff Garzik669a5db2006-08-29 18:12:40 -0400503static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
504{
505 struct ata_port *ap = qc->ap;
506 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Tejun Heo0d5ff562007-02-01 15:06:36 +0900507 u8 dma_stat = ioread8(ap->ioaddr.bmdma_addr + 2);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400508 u8 dma_cmd;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900509 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400510
Jeff Garzik669a5db2006-08-29 18:12:40 -0400511 if (dma_stat & 0x01) {
512 udelay(20);
Tejun Heo0d5ff562007-02-01 15:06:36 +0900513 dma_stat = ioread8(bmdma + 2);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400514 }
515 if (dma_stat & 0x01) {
516 /* Clear the engine */
517 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
518 udelay(10);
519 /* Stop DMA */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900520 dma_cmd = ioread8(bmdma );
521 iowrite8(dma_cmd & 0xFE, bmdma);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400522 /* Clear Error */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900523 dma_stat = ioread8(bmdma + 2);
524 iowrite8(dma_stat | 0x06 , bmdma + 2);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400525 /* Clear the engine */
526 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
527 udelay(10);
528 }
529 ata_bmdma_stop(qc);
530}
531
532/**
533 * hpt372_set_piomode - PIO setup
534 * @ap: ATA interface
535 * @adev: device on the interface
536 *
Jeff Garzik85cd7252006-08-31 00:03:49 -0400537 * Perform PIO mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400538 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400539
Jeff Garzik669a5db2006-08-29 18:12:40 -0400540static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
541{
542 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
543 u32 addr1, addr2;
544 u32 reg;
545 u32 mode;
546 u8 fast;
547
548 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
549 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400550
Jeff Garzik669a5db2006-08-29 18:12:40 -0400551 /* Fast interrupt prediction disable, hold off interrupt disable */
552 pci_read_config_byte(pdev, addr2, &fast);
553 fast &= ~0x07;
554 pci_write_config_byte(pdev, addr2, fast);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400555
Jeff Garzik669a5db2006-08-29 18:12:40 -0400556 pci_read_config_dword(pdev, addr1, &reg);
557 mode = hpt37x_find_mode(ap, adev->pio_mode);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400558
Jeff Garzik669a5db2006-08-29 18:12:40 -0400559 printk("Find mode for %d reports %X\n", adev->pio_mode, mode);
560 mode &= ~0x80000000; /* No FIFO in PIO */
561 mode &= ~0x30070000; /* Leave config bits alone */
562 reg &= 0x30070000; /* Strip timing bits */
563 pci_write_config_dword(pdev, addr1, reg | mode);
564}
565
566/**
567 * hpt372_set_dmamode - DMA timing setup
568 * @ap: ATA interface
569 * @adev: Device being configured
570 *
571 * Set up the channel for MWDMA or UDMA modes. Much the same as with
572 * PIO, load the mode number and then set MWDMA or UDMA flag.
573 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400574
Jeff Garzik669a5db2006-08-29 18:12:40 -0400575static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
576{
577 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
578 u32 addr1, addr2;
579 u32 reg;
580 u32 mode;
581 u8 fast;
582
583 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
584 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400585
Jeff Garzik669a5db2006-08-29 18:12:40 -0400586 /* Fast interrupt prediction disable, hold off interrupt disable */
587 pci_read_config_byte(pdev, addr2, &fast);
588 fast &= ~0x07;
589 pci_write_config_byte(pdev, addr2, fast);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400590
Jeff Garzik669a5db2006-08-29 18:12:40 -0400591 pci_read_config_dword(pdev, addr1, &reg);
592 mode = hpt37x_find_mode(ap, adev->dma_mode);
593 printk("Find mode for DMA %d reports %X\n", adev->dma_mode, mode);
594 mode &= ~0xC0000000; /* Leave config bits alone */
595 mode |= 0x80000000; /* FIFO in MWDMA or UDMA */
596 reg &= 0xC0000000; /* Strip timing bits */
597 pci_write_config_dword(pdev, addr1, reg | mode);
598}
599
600/**
601 * hpt37x_bmdma_end - DMA engine stop
602 * @qc: ATA command
603 *
604 * Clean up after the HPT372 and later DMA engine
605 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400606
Jeff Garzik669a5db2006-08-29 18:12:40 -0400607static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
608{
609 struct ata_port *ap = qc->ap;
610 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Alan6929da42007-01-05 16:37:01 -0800611 int mscreg = 0x50 + 4 * ap->port_no;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400612 u8 bwsr_stat, msc_stat;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400613
Jeff Garzik669a5db2006-08-29 18:12:40 -0400614 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
615 pci_read_config_byte(pdev, mscreg, &msc_stat);
616 if (bwsr_stat & (1 << ap->port_no))
617 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
618 ata_bmdma_stop(qc);
619}
620
621
622static struct scsi_host_template hpt37x_sht = {
623 .module = THIS_MODULE,
624 .name = DRV_NAME,
625 .ioctl = ata_scsi_ioctl,
626 .queuecommand = ata_scsi_queuecmd,
627 .can_queue = ATA_DEF_QUEUE,
628 .this_id = ATA_SHT_THIS_ID,
629 .sg_tablesize = LIBATA_MAX_PRD,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400630 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
631 .emulated = ATA_SHT_EMULATED,
632 .use_clustering = ATA_SHT_USE_CLUSTERING,
633 .proc_name = DRV_NAME,
634 .dma_boundary = ATA_DMA_BOUNDARY,
635 .slave_configure = ata_scsi_slave_config,
Tejun Heoafdfe892006-11-29 11:26:47 +0900636 .slave_destroy = ata_scsi_slave_destroy,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400637 .bios_param = ata_std_bios_param,
638};
639
640/*
641 * Configuration for HPT370
642 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400643
Jeff Garzik669a5db2006-08-29 18:12:40 -0400644static struct ata_port_operations hpt370_port_ops = {
645 .port_disable = ata_port_disable,
646 .set_piomode = hpt370_set_piomode,
647 .set_dmamode = hpt370_set_dmamode,
648 .mode_filter = hpt370_filter,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400649
Jeff Garzik669a5db2006-08-29 18:12:40 -0400650 .tf_load = ata_tf_load,
651 .tf_read = ata_tf_read,
652 .check_status = ata_check_status,
653 .exec_command = ata_exec_command,
654 .dev_select = ata_std_dev_select,
655
656 .freeze = ata_bmdma_freeze,
657 .thaw = ata_bmdma_thaw,
658 .error_handler = hpt37x_error_handler,
659 .post_internal_cmd = ata_bmdma_post_internal_cmd,
660
661 .bmdma_setup = ata_bmdma_setup,
662 .bmdma_start = hpt370_bmdma_start,
663 .bmdma_stop = hpt370_bmdma_stop,
664 .bmdma_status = ata_bmdma_status,
665
666 .qc_prep = ata_qc_prep,
667 .qc_issue = ata_qc_issue_prot,
Jeff Garzikbda30282006-09-27 05:41:13 -0400668
Tejun Heo0d5ff562007-02-01 15:06:36 +0900669 .data_xfer = ata_data_xfer,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400670
671 .irq_handler = ata_interrupt,
672 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900673 .irq_on = ata_irq_on,
674 .irq_ack = ata_irq_ack,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400675
676 .port_start = ata_port_start,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400677};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400678
679/*
680 * Configuration for HPT370A. Close to 370 but less filters
681 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400682
Jeff Garzik669a5db2006-08-29 18:12:40 -0400683static struct ata_port_operations hpt370a_port_ops = {
684 .port_disable = ata_port_disable,
685 .set_piomode = hpt370_set_piomode,
686 .set_dmamode = hpt370_set_dmamode,
687 .mode_filter = hpt370a_filter,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400688
Jeff Garzik669a5db2006-08-29 18:12:40 -0400689 .tf_load = ata_tf_load,
690 .tf_read = ata_tf_read,
691 .check_status = ata_check_status,
692 .exec_command = ata_exec_command,
693 .dev_select = ata_std_dev_select,
694
695 .freeze = ata_bmdma_freeze,
696 .thaw = ata_bmdma_thaw,
697 .error_handler = hpt37x_error_handler,
698 .post_internal_cmd = ata_bmdma_post_internal_cmd,
699
700 .bmdma_setup = ata_bmdma_setup,
701 .bmdma_start = hpt370_bmdma_start,
702 .bmdma_stop = hpt370_bmdma_stop,
703 .bmdma_status = ata_bmdma_status,
704
705 .qc_prep = ata_qc_prep,
706 .qc_issue = ata_qc_issue_prot,
Jeff Garzikbda30282006-09-27 05:41:13 -0400707
Tejun Heo0d5ff562007-02-01 15:06:36 +0900708 .data_xfer = ata_data_xfer,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400709
710 .irq_handler = ata_interrupt,
711 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900712 .irq_on = ata_irq_on,
713 .irq_ack = ata_irq_ack,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400714
715 .port_start = ata_port_start,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400716};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400717
718/*
719 * Configuration for HPT372, HPT371, HPT302. Slightly different PIO
720 * and DMA mode setting functionality.
721 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400722
Jeff Garzik669a5db2006-08-29 18:12:40 -0400723static struct ata_port_operations hpt372_port_ops = {
724 .port_disable = ata_port_disable,
725 .set_piomode = hpt372_set_piomode,
726 .set_dmamode = hpt372_set_dmamode,
727 .mode_filter = ata_pci_default_filter,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400728
Jeff Garzik669a5db2006-08-29 18:12:40 -0400729 .tf_load = ata_tf_load,
730 .tf_read = ata_tf_read,
731 .check_status = ata_check_status,
732 .exec_command = ata_exec_command,
733 .dev_select = ata_std_dev_select,
734
735 .freeze = ata_bmdma_freeze,
736 .thaw = ata_bmdma_thaw,
737 .error_handler = hpt37x_error_handler,
738 .post_internal_cmd = ata_bmdma_post_internal_cmd,
739
740 .bmdma_setup = ata_bmdma_setup,
741 .bmdma_start = ata_bmdma_start,
742 .bmdma_stop = hpt37x_bmdma_stop,
743 .bmdma_status = ata_bmdma_status,
744
745 .qc_prep = ata_qc_prep,
746 .qc_issue = ata_qc_issue_prot,
Jeff Garzikbda30282006-09-27 05:41:13 -0400747
Tejun Heo0d5ff562007-02-01 15:06:36 +0900748 .data_xfer = ata_data_xfer,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400749
750 .irq_handler = ata_interrupt,
751 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900752 .irq_on = ata_irq_on,
753 .irq_ack = ata_irq_ack,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400754
755 .port_start = ata_port_start,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400756};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400757
758/*
759 * Configuration for HPT374. Mode setting works like 372 and friends
760 * but we have a different cable detection procedure.
761 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400762
Jeff Garzik669a5db2006-08-29 18:12:40 -0400763static struct ata_port_operations hpt374_port_ops = {
764 .port_disable = ata_port_disable,
765 .set_piomode = hpt372_set_piomode,
766 .set_dmamode = hpt372_set_dmamode,
767 .mode_filter = ata_pci_default_filter,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400768
Jeff Garzik669a5db2006-08-29 18:12:40 -0400769 .tf_load = ata_tf_load,
770 .tf_read = ata_tf_read,
771 .check_status = ata_check_status,
772 .exec_command = ata_exec_command,
773 .dev_select = ata_std_dev_select,
774
775 .freeze = ata_bmdma_freeze,
776 .thaw = ata_bmdma_thaw,
777 .error_handler = hpt374_error_handler,
778 .post_internal_cmd = ata_bmdma_post_internal_cmd,
779
780 .bmdma_setup = ata_bmdma_setup,
781 .bmdma_start = ata_bmdma_start,
782 .bmdma_stop = hpt37x_bmdma_stop,
783 .bmdma_status = ata_bmdma_status,
784
785 .qc_prep = ata_qc_prep,
786 .qc_issue = ata_qc_issue_prot,
Jeff Garzikbda30282006-09-27 05:41:13 -0400787
Tejun Heo0d5ff562007-02-01 15:06:36 +0900788 .data_xfer = ata_data_xfer,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400789
790 .irq_handler = ata_interrupt,
791 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900792 .irq_on = ata_irq_on,
793 .irq_ack = ata_irq_ack,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400794
795 .port_start = ata_port_start,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400796};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400797
798/**
799 * htp37x_clock_slot - Turn timing to PC clock entry
800 * @freq: Reported frequency timing
801 * @base: Base timing
802 *
803 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
804 * and 3 for 66Mhz)
805 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400806
Jeff Garzik669a5db2006-08-29 18:12:40 -0400807static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
808{
809 unsigned int f = (base * freq) / 192; /* Mhz */
810 if (f < 40)
811 return 0; /* 33Mhz slot */
812 if (f < 45)
813 return 1; /* 40Mhz slot */
814 if (f < 55)
815 return 2; /* 50Mhz slot */
816 return 3; /* 60Mhz slot */
817}
818
819/**
820 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
Jeff Garzik85cd7252006-08-31 00:03:49 -0400821 * @dev: PCI device
Jeff Garzik669a5db2006-08-29 18:12:40 -0400822 *
823 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
824 * succeeds
825 */
826
827static int hpt37x_calibrate_dpll(struct pci_dev *dev)
828{
829 u8 reg5b;
830 u32 reg5c;
831 int tries;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400832
Jeff Garzik669a5db2006-08-29 18:12:40 -0400833 for(tries = 0; tries < 0x5000; tries++) {
834 udelay(50);
835 pci_read_config_byte(dev, 0x5b, &reg5b);
836 if (reg5b & 0x80) {
837 /* See if it stays set */
838 for(tries = 0; tries < 0x1000; tries ++) {
839 pci_read_config_byte(dev, 0x5b, &reg5b);
840 /* Failed ? */
841 if ((reg5b & 0x80) == 0)
842 return 0;
843 }
844 /* Turn off tuning, we have the DPLL set */
845 pci_read_config_dword(dev, 0x5c, &reg5c);
846 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
847 return 1;
848 }
849 }
850 /* Never went stable */
851 return 0;
852}
853/**
854 * hpt37x_init_one - Initialise an HPT37X/302
855 * @dev: PCI device
856 * @id: Entry in match table
857 *
858 * Initialise an HPT37x device. There are some interesting complications
859 * here. Firstly the chip may report 366 and be one of several variants.
860 * Secondly all the timings depend on the clock for the chip which we must
861 * detect and look up
862 *
863 * This is the known chip mappings. It may be missing a couple of later
864 * releases.
865 *
866 * Chip version PCI Rev Notes
867 * HPT366 4 (HPT366) 0 Other driver
868 * HPT366 4 (HPT366) 1 Other driver
869 * HPT368 4 (HPT366) 2 Other driver
870 * HPT370 4 (HPT366) 3 UDMA100
871 * HPT370A 4 (HPT366) 4 UDMA100
872 * HPT372 4 (HPT366) 5 UDMA133 (1)
873 * HPT372N 4 (HPT366) 6 Other driver
874 * HPT372A 5 (HPT372) 1 UDMA133 (1)
875 * HPT372N 5 (HPT372) 2 Other driver
876 * HPT302 6 (HPT302) 1 UDMA133
877 * HPT302N 6 (HPT302) 2 Other driver
878 * HPT371 7 (HPT371) * UDMA133
879 * HPT374 8 (HPT374) * UDMA133 4 channel
880 * HPT372N 9 (HPT372N) * Other driver
881 *
882 * (1) UDMA133 support depends on the bus clock
883 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400884
Jeff Garzik669a5db2006-08-29 18:12:40 -0400885static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
886{
887 /* HPT370 - UDMA100 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200888 static const struct ata_port_info info_hpt370 = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400889 .sht = &hpt37x_sht,
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400890 .flags = ATA_FLAG_SLAVE_POSS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400891 .pio_mask = 0x1f,
892 .mwdma_mask = 0x07,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400893 .udma_mask = ATA_UDMA5,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400894 .port_ops = &hpt370_port_ops
895 };
896 /* HPT370A - UDMA100 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200897 static const struct ata_port_info info_hpt370a = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400898 .sht = &hpt37x_sht,
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400899 .flags = ATA_FLAG_SLAVE_POSS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400900 .pio_mask = 0x1f,
901 .mwdma_mask = 0x07,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400902 .udma_mask = ATA_UDMA5,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400903 .port_ops = &hpt370a_port_ops
904 };
Alan Coxfcc2f692007-03-08 23:28:52 +0000905 /* HPT370 - UDMA100 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200906 static const struct ata_port_info info_hpt370_33 = {
Alan Coxfcc2f692007-03-08 23:28:52 +0000907 .sht = &hpt37x_sht,
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400908 .flags = ATA_FLAG_SLAVE_POSS,
Alan Coxfcc2f692007-03-08 23:28:52 +0000909 .pio_mask = 0x1f,
910 .mwdma_mask = 0x07,
911 .udma_mask = 0x0f,
912 .port_ops = &hpt370_port_ops
913 };
914 /* HPT370A - UDMA100 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200915 static const struct ata_port_info info_hpt370a_33 = {
Alan Coxfcc2f692007-03-08 23:28:52 +0000916 .sht = &hpt37x_sht,
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400917 .flags = ATA_FLAG_SLAVE_POSS,
Alan Coxfcc2f692007-03-08 23:28:52 +0000918 .pio_mask = 0x1f,
919 .mwdma_mask = 0x07,
920 .udma_mask = 0x0f,
921 .port_ops = &hpt370a_port_ops
922 };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400923 /* HPT371, 372 and friends - UDMA133 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200924 static const struct ata_port_info info_hpt372 = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400925 .sht = &hpt37x_sht,
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400926 .flags = ATA_FLAG_SLAVE_POSS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400927 .pio_mask = 0x1f,
928 .mwdma_mask = 0x07,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400929 .udma_mask = ATA_UDMA6,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400930 .port_ops = &hpt372_port_ops
931 };
Alan Cox62877f62007-06-22 14:17:28 +0100932 /* HPT374 - UDMA100 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200933 static const struct ata_port_info info_hpt374 = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400934 .sht = &hpt37x_sht,
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400935 .flags = ATA_FLAG_SLAVE_POSS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400936 .pio_mask = 0x1f,
937 .mwdma_mask = 0x07,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400938 .udma_mask = ATA_UDMA5,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400939 .port_ops = &hpt374_port_ops
940 };
941
942 static const int MHz[4] = { 33, 40, 50, 66 };
Tejun Heo1626aeb2007-05-04 12:43:58 +0200943 const struct ata_port_info *port;
944 void *private_data = NULL;
945 struct ata_port_info port_info;
946 const struct ata_port_info *ppi[] = { &port_info, NULL };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400947
948 u8 irqmask;
949 u32 class_rev;
Alan Coxfcc2f692007-03-08 23:28:52 +0000950 u8 mcr1;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400951 u32 freq;
Alan Coxfcc2f692007-03-08 23:28:52 +0000952 int prefer_dpll = 1;
Jeff Garzika617c092007-05-21 20:14:23 -0400953
Alan Coxfcc2f692007-03-08 23:28:52 +0000954 unsigned long iobase = pci_resource_start(dev, 4);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400955
956 const struct hpt_chip *chip_table;
957 int clock_slot;
958
959 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
960 class_rev &= 0xFF;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400961
Jeff Garzik669a5db2006-08-29 18:12:40 -0400962 if (dev->device == PCI_DEVICE_ID_TTI_HPT366) {
963 /* May be a later chip in disguise. Check */
964 /* Older chips are in the HPT366 driver. Ignore them */
965 if (class_rev < 3)
966 return -ENODEV;
967 /* N series chips have their own driver. Ignore */
968 if (class_rev == 6)
969 return -ENODEV;
970
Jeff Garzik85cd7252006-08-31 00:03:49 -0400971 switch(class_rev) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400972 case 3:
973 port = &info_hpt370;
974 chip_table = &hpt370;
Alan Coxfcc2f692007-03-08 23:28:52 +0000975 prefer_dpll = 0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400976 break;
977 case 4:
978 port = &info_hpt370a;
979 chip_table = &hpt370a;
Alan Coxfcc2f692007-03-08 23:28:52 +0000980 prefer_dpll = 0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400981 break;
982 case 5:
983 port = &info_hpt372;
984 chip_table = &hpt372;
985 break;
986 default:
987 printk(KERN_ERR "pata_hpt37x: Unknown HPT366 subtype please report (%d).\n", class_rev);
988 return -ENODEV;
989 }
990 } else {
991 switch(dev->device) {
992 case PCI_DEVICE_ID_TTI_HPT372:
993 /* 372N if rev >= 2*/
994 if (class_rev >= 2)
995 return -ENODEV;
996 port = &info_hpt372;
997 chip_table = &hpt372a;
998 break;
999 case PCI_DEVICE_ID_TTI_HPT302:
1000 /* 302N if rev > 1 */
1001 if (class_rev > 1)
1002 return -ENODEV;
1003 port = &info_hpt372;
1004 /* Check this */
1005 chip_table = &hpt302;
1006 break;
1007 case PCI_DEVICE_ID_TTI_HPT371:
Alan Coxfcc2f692007-03-08 23:28:52 +00001008 if (class_rev > 1)
1009 return -ENODEV;
Jeff Garzik669a5db2006-08-29 18:12:40 -04001010 port = &info_hpt372;
1011 chip_table = &hpt371;
Alan Coxa4734462007-04-26 00:19:25 -07001012 /* Single channel device, master is not present
1013 but the BIOS (or us for non x86) must mark it
Alan Coxfcc2f692007-03-08 23:28:52 +00001014 absent */
1015 pci_read_config_byte(dev, 0x50, &mcr1);
1016 mcr1 &= ~0x04;
1017 pci_write_config_byte(dev, 0x50, mcr1);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001018 break;
1019 case PCI_DEVICE_ID_TTI_HPT374:
1020 chip_table = &hpt374;
1021 port = &info_hpt374;
1022 break;
1023 default:
1024 printk(KERN_ERR "pata_hpt37x: PCI table is bogus please report (%d).\n", dev->device);
1025 return -ENODEV;
1026 }
1027 }
1028 /* Ok so this is a chip we support */
1029
1030 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1031 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1032 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1033 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1034
1035 pci_read_config_byte(dev, 0x5A, &irqmask);
1036 irqmask &= ~0x10;
1037 pci_write_config_byte(dev, 0x5a, irqmask);
1038
1039 /*
1040 * default to pci clock. make sure MA15/16 are set to output
1041 * to prevent drives having problems with 40-pin cables. Needed
1042 * for some drives such as IBM-DTLA which will not enter ready
1043 * state on reset when PDIAG is a input.
1044 */
1045
Jeff Garzik85cd7252006-08-31 00:03:49 -04001046 pci_write_config_byte(dev, 0x5b, 0x23);
Jeff Garzika617c092007-05-21 20:14:23 -04001047
Alan Coxfcc2f692007-03-08 23:28:52 +00001048 /*
1049 * HighPoint does this for HPT372A.
1050 * NOTE: This register is only writeable via I/O space.
1051 */
1052 if (chip_table == &hpt372a)
1053 outb(0x0e, iobase + 0x9c);
Jeff Garzik85cd7252006-08-31 00:03:49 -04001054
Alan Coxfcc2f692007-03-08 23:28:52 +00001055 /* Some devices do not let this value be accessed via PCI space
1056 according to the old driver */
1057
1058 freq = inl(iobase + 0x90);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001059 if ((freq >> 12) != 0xABCDE) {
1060 int i;
1061 u8 sr;
1062 u32 total = 0;
Jeff Garzik85cd7252006-08-31 00:03:49 -04001063
Jeff Garzik669a5db2006-08-29 18:12:40 -04001064 printk(KERN_WARNING "pata_hpt37x: BIOS has not set timing clocks.\n");
Jeff Garzik85cd7252006-08-31 00:03:49 -04001065
Jeff Garzik669a5db2006-08-29 18:12:40 -04001066 /* This is the process the HPT371 BIOS is reported to use */
1067 for(i = 0; i < 128; i++) {
1068 pci_read_config_byte(dev, 0x78, &sr);
Alan Coxfcc2f692007-03-08 23:28:52 +00001069 total += sr & 0x1FF;
Jeff Garzik669a5db2006-08-29 18:12:40 -04001070 udelay(15);
1071 }
1072 freq = total / 128;
1073 }
1074 freq &= 0x1FF;
Jeff Garzik85cd7252006-08-31 00:03:49 -04001075
Jeff Garzik669a5db2006-08-29 18:12:40 -04001076 /*
1077 * Turn the frequency check into a band and then find a timing
1078 * table to match it.
1079 */
Jeff Garzika617c092007-05-21 20:14:23 -04001080
Jeff Garzik669a5db2006-08-29 18:12:40 -04001081 clock_slot = hpt37x_clock_slot(freq, chip_table->base);
Alan Coxfcc2f692007-03-08 23:28:52 +00001082 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
Jeff Garzik669a5db2006-08-29 18:12:40 -04001083 /*
1084 * We need to try PLL mode instead
Alan Coxfcc2f692007-03-08 23:28:52 +00001085 *
1086 * For non UDMA133 capable devices we should
1087 * use a 50MHz DPLL by choice
Jeff Garzik669a5db2006-08-29 18:12:40 -04001088 */
Alan Coxfcc2f692007-03-08 23:28:52 +00001089 unsigned int f_low, f_high;
Alan Cox960c8a12007-05-25 20:48:55 +01001090 int dpll, adjust;
Jeff Garzika617c092007-05-21 20:14:23 -04001091
Alan Cox960c8a12007-05-25 20:48:55 +01001092 /* Compute DPLL */
Sergei Shtylyovd44a65f2007-08-10 20:58:46 +04001093 dpll = (port->udma_mask & 0xC0) ? 3 : 2;
Jeff Garzika617c092007-05-21 20:14:23 -04001094
Alan Cox960c8a12007-05-25 20:48:55 +01001095 f_low = (MHz[clock_slot] * 48) / MHz[dpll];
Alan Coxfcc2f692007-03-08 23:28:52 +00001096 f_high = f_low + 2;
Alan Cox960c8a12007-05-25 20:48:55 +01001097 if (clock_slot > 1)
1098 f_high += 2;
Alan Coxfcc2f692007-03-08 23:28:52 +00001099
1100 /* Select the DPLL clock. */
1101 pci_write_config_byte(dev, 0x5b, 0x21);
Alan Cox64a81702007-07-24 15:17:48 +01001102 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
Jeff Garzik85cd7252006-08-31 00:03:49 -04001103
Jeff Garzik669a5db2006-08-29 18:12:40 -04001104 for(adjust = 0; adjust < 8; adjust++) {
1105 if (hpt37x_calibrate_dpll(dev))
1106 break;
1107 /* See if it'll settle at a fractionally different clock */
Alan Cox64a81702007-07-24 15:17:48 +01001108 if (adjust & 1)
1109 f_low -= adjust >> 1;
1110 else
1111 f_high += adjust >> 1;
1112 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001113 }
1114 if (adjust == 8) {
Sergei Shtylyov80b89872007-08-10 21:02:15 +04001115 printk(KERN_ERR "pata_hpt37x: DPLL did not stabilize!\n");
Jeff Garzik669a5db2006-08-29 18:12:40 -04001116 return -ENODEV;
1117 }
Alan Cox960c8a12007-05-25 20:48:55 +01001118 if (dpll == 3)
Tejun Heo1626aeb2007-05-04 12:43:58 +02001119 private_data = (void *)hpt37x_timings_66;
Alan Coxfcc2f692007-03-08 23:28:52 +00001120 else
Tejun Heo1626aeb2007-05-04 12:43:58 +02001121 private_data = (void *)hpt37x_timings_50;
Jeff Garzik85cd7252006-08-31 00:03:49 -04001122
Sergei Shtylyov80b89872007-08-10 21:02:15 +04001123 printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using %dMHz DPLL.\n",
1124 MHz[clock_slot], MHz[dpll]);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001125 } else {
Tejun Heo1626aeb2007-05-04 12:43:58 +02001126 private_data = (void *)chip_table->clocks[clock_slot];
Jeff Garzik669a5db2006-08-29 18:12:40 -04001127 /*
Alan Coxa4734462007-04-26 00:19:25 -07001128 * Perform a final fixup. Note that we will have used the
1129 * DPLL on the HPT372 which means we don't have to worry
1130 * about lack of UDMA133 support on lower clocks
1131 */
Jeff Garzik85cd7252006-08-31 00:03:49 -04001132
Alan Coxfcc2f692007-03-08 23:28:52 +00001133 if (clock_slot < 2 && port == &info_hpt370)
1134 port = &info_hpt370_33;
1135 if (clock_slot < 2 && port == &info_hpt370a)
1136 port = &info_hpt370a_33;
Sergei Shtylyov80b89872007-08-10 21:02:15 +04001137 printk(KERN_INFO "pata_hpt37x: %s using %dMHz bus clock.\n",
1138 chip_table->name, MHz[clock_slot]);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001139 }
Alan Coxfcc2f692007-03-08 23:28:52 +00001140
Jeff Garzik669a5db2006-08-29 18:12:40 -04001141 /* Now kick off ATA set up */
Tejun Heo1626aeb2007-05-04 12:43:58 +02001142 port_info = *port;
1143 port_info.private_data = private_data;
1144
1145 return ata_pci_init_one(dev, ppi);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001146}
1147
Jeff Garzik2d2744f2006-09-28 20:21:59 -04001148static const struct pci_device_id hpt37x[] = {
1149 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
1150 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
1151 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
1152 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
1153 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
1154
1155 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -04001156};
1157
1158static struct pci_driver hpt37x_pci_driver = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -04001159 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -04001160 .id_table = hpt37x,
1161 .probe = hpt37x_init_one,
1162 .remove = ata_pci_remove_one
1163};
1164
1165static int __init hpt37x_init(void)
1166{
1167 return pci_register_driver(&hpt37x_pci_driver);
1168}
1169
Jeff Garzik669a5db2006-08-29 18:12:40 -04001170static void __exit hpt37x_exit(void)
1171{
1172 pci_unregister_driver(&hpt37x_pci_driver);
1173}
1174
Jeff Garzik669a5db2006-08-29 18:12:40 -04001175MODULE_AUTHOR("Alan Cox");
1176MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1177MODULE_LICENSE("GPL");
1178MODULE_DEVICE_TABLE(pci, hpt37x);
1179MODULE_VERSION(DRV_VERSION);
1180
1181module_init(hpt37x_init);
1182module_exit(hpt37x_exit);