Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2005-2011 Atheros Communications Inc. |
| 3 | * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. |
| 4 | * |
| 5 | * Permission to use, copy, modify, and/or distribute this software for any |
| 6 | * purpose with or without fee is hereby granted, provided that the above |
| 7 | * copyright notice and this permission notice appear in all copies. |
| 8 | * |
| 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 16 | */ |
| 17 | |
| 18 | #ifndef _HW_H_ |
| 19 | #define _HW_H_ |
| 20 | |
| 21 | #include "targaddrs.h" |
| 22 | |
Kalle Valo | e01ae68 | 2013-09-01 11:22:14 +0300 | [diff] [blame] | 23 | /* QCA988X 1.0 definitions (unsupported) */ |
| 24 | #define QCA988X_HW_1_0_CHIP_ID_REV 0x0 |
| 25 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 26 | /* QCA988X 2.0 definitions */ |
| 27 | #define QCA988X_HW_2_0_VERSION 0x4100016c |
Kalle Valo | e01ae68 | 2013-09-01 11:22:14 +0300 | [diff] [blame] | 28 | #define QCA988X_HW_2_0_CHIP_ID_REV 0x2 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 29 | #define QCA988X_HW_2_0_FW_DIR "ath10k/QCA988X/hw2.0" |
| 30 | #define QCA988X_HW_2_0_FW_FILE "firmware.bin" |
Michal Kazior | 24c88f7 | 2014-07-25 13:32:17 +0200 | [diff] [blame] | 31 | #define QCA988X_HW_2_0_FW_3_FILE "firmware-3.bin" |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 32 | #define QCA988X_HW_2_0_OTP_FILE "otp.bin" |
| 33 | #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" |
| 34 | #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 |
| 35 | |
Kalle Valo | 1a22243 | 2013-09-27 19:55:07 +0300 | [diff] [blame] | 36 | #define ATH10K_FW_API2_FILE "firmware-2.bin" |
Michal Kazior | 24c88f7 | 2014-07-25 13:32:17 +0200 | [diff] [blame] | 37 | #define ATH10K_FW_API3_FILE "firmware-3.bin" |
Kalle Valo | 1a22243 | 2013-09-27 19:55:07 +0300 | [diff] [blame] | 38 | |
Kalle Valo | 43d2a30 | 2014-09-10 18:23:30 +0300 | [diff] [blame] | 39 | #define ATH10K_FW_UTF_FILE "utf.bin" |
| 40 | |
Kalle Valo | 1a22243 | 2013-09-27 19:55:07 +0300 | [diff] [blame] | 41 | /* includes also the null byte */ |
| 42 | #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K" |
| 43 | |
Ben Greear | 384914b | 2014-08-25 08:37:32 +0300 | [diff] [blame] | 44 | #define REG_DUMP_COUNT_QCA988X 60 |
| 45 | |
Kalle Valo | 7869b4f | 2014-09-24 14:16:58 +0300 | [diff] [blame] | 46 | #define QCA988X_CAL_DATA_LEN 2116 |
| 47 | |
Kalle Valo | 1a22243 | 2013-09-27 19:55:07 +0300 | [diff] [blame] | 48 | struct ath10k_fw_ie { |
| 49 | __le32 id; |
| 50 | __le32 len; |
| 51 | u8 data[0]; |
| 52 | }; |
| 53 | |
| 54 | enum ath10k_fw_ie_type { |
| 55 | ATH10K_FW_IE_FW_VERSION = 0, |
| 56 | ATH10K_FW_IE_TIMESTAMP = 1, |
| 57 | ATH10K_FW_IE_FEATURES = 2, |
| 58 | ATH10K_FW_IE_FW_IMAGE = 3, |
| 59 | ATH10K_FW_IE_OTP_IMAGE = 4, |
| 60 | }; |
| 61 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 62 | /* Known pecularities: |
| 63 | * - current FW doesn't support raw rx mode (last tested v599) |
| 64 | * - current FW dumps upon raw tx mode (last tested v599) |
| 65 | * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap |
| 66 | * - raw have FCS, nwifi doesn't |
| 67 | * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher |
| 68 | * param, llc/snap) are aligned to 4byte boundaries each */ |
| 69 | enum ath10k_hw_txrx_mode { |
| 70 | ATH10K_HW_TXRX_RAW = 0, |
| 71 | ATH10K_HW_TXRX_NATIVE_WIFI = 1, |
| 72 | ATH10K_HW_TXRX_ETHERNET = 2, |
Michal Kazior | 961d4c3 | 2013-08-09 10:13:34 +0200 | [diff] [blame] | 73 | |
| 74 | /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */ |
| 75 | ATH10K_HW_TXRX_MGMT = 3, |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 76 | }; |
| 77 | |
| 78 | enum ath10k_mcast2ucast_mode { |
| 79 | ATH10K_MCAST2UCAST_DISABLED = 0, |
| 80 | ATH10K_MCAST2UCAST_ENABLED = 1, |
| 81 | }; |
| 82 | |
Rajkumar Manoharan | bfdd793 | 2014-10-03 08:02:40 +0300 | [diff] [blame^] | 83 | struct ath10k_pktlog_hdr { |
| 84 | __le16 flags; |
| 85 | __le16 missed_cnt; |
| 86 | __le16 log_type; |
| 87 | __le16 size; |
| 88 | __le32 timestamp; |
| 89 | u8 payload[0]; |
| 90 | } __packed; |
| 91 | |
Bartosz Markowski | ec6a73f | 2013-09-26 17:47:14 +0200 | [diff] [blame] | 92 | /* Target specific defines for MAIN firmware */ |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 93 | #define TARGET_NUM_VDEVS 8 |
| 94 | #define TARGET_NUM_PEER_AST 2 |
| 95 | #define TARGET_NUM_WDS_ENTRIES 32 |
| 96 | #define TARGET_DMA_BURST_SIZE 0 |
| 97 | #define TARGET_MAC_AGGR_DELIM 0 |
| 98 | #define TARGET_AST_SKID_LIMIT 16 |
| 99 | #define TARGET_NUM_PEERS 16 |
| 100 | #define TARGET_NUM_OFFLOAD_PEERS 0 |
| 101 | #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 |
| 102 | #define TARGET_NUM_PEER_KEYS 2 |
| 103 | #define TARGET_NUM_TIDS (2 * ((TARGET_NUM_PEERS) + (TARGET_NUM_VDEVS))) |
| 104 | #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) |
| 105 | #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) |
| 106 | #define TARGET_RX_TIMEOUT_LO_PRI 100 |
| 107 | #define TARGET_RX_TIMEOUT_HI_PRI 40 |
Michal Kazior | 4d316c7 | 2013-09-26 10:12:24 +0300 | [diff] [blame] | 108 | |
| 109 | /* Native Wifi decap mode is used to align IP frames to 4-byte boundaries and |
| 110 | * avoid a very expensive re-alignment in mac80211. */ |
| 111 | #define TARGET_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI |
| 112 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 113 | #define TARGET_SCAN_MAX_PENDING_REQS 4 |
| 114 | #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 |
| 115 | #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 |
| 116 | #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 |
| 117 | #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 |
| 118 | #define TARGET_NUM_MCAST_GROUPS 0 |
| 119 | #define TARGET_NUM_MCAST_TABLE_ELEMS 0 |
| 120 | #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED |
| 121 | #define TARGET_TX_DBG_LOG_SIZE 1024 |
| 122 | #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 |
| 123 | #define TARGET_VOW_CONFIG 0 |
| 124 | #define TARGET_NUM_MSDU_DESC (1024 + 400) |
| 125 | #define TARGET_MAX_FRAG_ENTRIES 0 |
| 126 | |
Bartosz Markowski | ec6a73f | 2013-09-26 17:47:14 +0200 | [diff] [blame] | 127 | /* Target specific defines for 10.X firmware */ |
| 128 | #define TARGET_10X_NUM_VDEVS 16 |
| 129 | #define TARGET_10X_NUM_PEER_AST 2 |
| 130 | #define TARGET_10X_NUM_WDS_ENTRIES 32 |
| 131 | #define TARGET_10X_DMA_BURST_SIZE 0 |
| 132 | #define TARGET_10X_MAC_AGGR_DELIM 0 |
| 133 | #define TARGET_10X_AST_SKID_LIMIT 16 |
| 134 | #define TARGET_10X_NUM_PEERS (128 + (TARGET_10X_NUM_VDEVS)) |
Bartosz Markowski | 0e759f3 | 2014-01-02 14:38:33 +0100 | [diff] [blame] | 135 | #define TARGET_10X_NUM_PEERS_MAX 128 |
Bartosz Markowski | ec6a73f | 2013-09-26 17:47:14 +0200 | [diff] [blame] | 136 | #define TARGET_10X_NUM_OFFLOAD_PEERS 0 |
| 137 | #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 |
| 138 | #define TARGET_10X_NUM_PEER_KEYS 2 |
| 139 | #define TARGET_10X_NUM_TIDS 256 |
| 140 | #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) |
| 141 | #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) |
| 142 | #define TARGET_10X_RX_TIMEOUT_LO_PRI 100 |
| 143 | #define TARGET_10X_RX_TIMEOUT_HI_PRI 40 |
Michal Kazior | 0d1a28f | 2013-10-07 20:00:36 -0700 | [diff] [blame] | 144 | #define TARGET_10X_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI |
Bartosz Markowski | ec6a73f | 2013-09-26 17:47:14 +0200 | [diff] [blame] | 145 | #define TARGET_10X_SCAN_MAX_PENDING_REQS 4 |
| 146 | #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2 |
| 147 | #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2 |
| 148 | #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8 |
| 149 | #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3 |
| 150 | #define TARGET_10X_NUM_MCAST_GROUPS 0 |
| 151 | #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0 |
| 152 | #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED |
| 153 | #define TARGET_10X_TX_DBG_LOG_SIZE 1024 |
| 154 | #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 |
| 155 | #define TARGET_10X_VOW_CONFIG 0 |
| 156 | #define TARGET_10X_NUM_MSDU_DESC (1024 + 400) |
| 157 | #define TARGET_10X_MAX_FRAG_ENTRIES 0 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 158 | |
| 159 | /* Number of Copy Engines supported */ |
| 160 | #define CE_COUNT 8 |
| 161 | |
| 162 | /* |
| 163 | * Total number of PCIe MSI interrupts requested for all interrupt sources. |
| 164 | * PCIe standard forces this to be a power of 2. |
| 165 | * Some Host OS's limit MSI requests that can be granted to 8 |
| 166 | * so for now we abide by this limit and avoid requesting more |
| 167 | * than that. |
| 168 | */ |
| 169 | #define MSI_NUM_REQUEST_LOG2 3 |
| 170 | #define MSI_NUM_REQUEST (1<<MSI_NUM_REQUEST_LOG2) |
| 171 | |
| 172 | /* |
| 173 | * Granted MSIs are assigned as follows: |
| 174 | * Firmware uses the first |
| 175 | * Remaining MSIs, if any, are used by Copy Engines |
| 176 | * This mapping is known to both Target firmware and Host software. |
| 177 | * It may be changed as long as Host and Target are kept in sync. |
| 178 | */ |
| 179 | /* MSI for firmware (errors, etc.) */ |
| 180 | #define MSI_ASSIGN_FW 0 |
| 181 | |
| 182 | /* MSIs for Copy Engines */ |
| 183 | #define MSI_ASSIGN_CE_INITIAL 1 |
| 184 | #define MSI_ASSIGN_CE_MAX 7 |
| 185 | |
| 186 | /* as of IP3.7.1 */ |
| 187 | #define RTC_STATE_V_ON 3 |
| 188 | |
| 189 | #define RTC_STATE_COLD_RESET_MASK 0x00000400 |
| 190 | #define RTC_STATE_V_LSB 0 |
| 191 | #define RTC_STATE_V_MASK 0x00000007 |
| 192 | #define RTC_STATE_ADDRESS 0x0000 |
| 193 | #define PCIE_SOC_WAKE_V_MASK 0x00000001 |
| 194 | #define PCIE_SOC_WAKE_ADDRESS 0x0004 |
| 195 | #define PCIE_SOC_WAKE_RESET 0x00000000 |
| 196 | #define SOC_GLOBAL_RESET_ADDRESS 0x0008 |
| 197 | |
| 198 | #define RTC_SOC_BASE_ADDRESS 0x00004000 |
| 199 | #define RTC_WMAC_BASE_ADDRESS 0x00005000 |
| 200 | #define MAC_COEX_BASE_ADDRESS 0x00006000 |
| 201 | #define BT_COEX_BASE_ADDRESS 0x00007000 |
| 202 | #define SOC_PCIE_BASE_ADDRESS 0x00008000 |
| 203 | #define SOC_CORE_BASE_ADDRESS 0x00009000 |
| 204 | #define WLAN_UART_BASE_ADDRESS 0x0000c000 |
| 205 | #define WLAN_SI_BASE_ADDRESS 0x00010000 |
| 206 | #define WLAN_GPIO_BASE_ADDRESS 0x00014000 |
| 207 | #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 |
| 208 | #define WLAN_MAC_BASE_ADDRESS 0x00020000 |
| 209 | #define EFUSE_BASE_ADDRESS 0x00030000 |
| 210 | #define FPGA_REG_BASE_ADDRESS 0x00039000 |
| 211 | #define WLAN_UART2_BASE_ADDRESS 0x00054c00 |
| 212 | #define CE_WRAPPER_BASE_ADDRESS 0x00057000 |
| 213 | #define CE0_BASE_ADDRESS 0x00057400 |
| 214 | #define CE1_BASE_ADDRESS 0x00057800 |
| 215 | #define CE2_BASE_ADDRESS 0x00057c00 |
| 216 | #define CE3_BASE_ADDRESS 0x00058000 |
| 217 | #define CE4_BASE_ADDRESS 0x00058400 |
| 218 | #define CE5_BASE_ADDRESS 0x00058800 |
| 219 | #define CE6_BASE_ADDRESS 0x00058c00 |
| 220 | #define CE7_BASE_ADDRESS 0x00059000 |
| 221 | #define DBI_BASE_ADDRESS 0x00060000 |
| 222 | #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 |
| 223 | #define PCIE_LOCAL_BASE_ADDRESS 0x00080000 |
| 224 | |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 225 | #define SOC_RESET_CONTROL_ADDRESS 0x00000000 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 226 | #define SOC_RESET_CONTROL_OFFSET 0x00000000 |
| 227 | #define SOC_RESET_CONTROL_SI0_RST_MASK 0x00000001 |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 228 | #define SOC_RESET_CONTROL_CE_RST_MASK 0x00040000 |
| 229 | #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 230 | #define SOC_CPU_CLOCK_OFFSET 0x00000020 |
| 231 | #define SOC_CPU_CLOCK_STANDARD_LSB 0 |
| 232 | #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 |
| 233 | #define SOC_CLOCK_CONTROL_OFFSET 0x00000028 |
| 234 | #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 |
| 235 | #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 |
| 236 | #define SOC_LPO_CAL_OFFSET 0x000000e0 |
| 237 | #define SOC_LPO_CAL_ENABLE_LSB 20 |
| 238 | #define SOC_LPO_CAL_ENABLE_MASK 0x00100000 |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 239 | #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 |
| 240 | #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 241 | |
Kalle Valo | e01ae68 | 2013-09-01 11:22:14 +0300 | [diff] [blame] | 242 | #define SOC_CHIP_ID_ADDRESS 0x000000ec |
| 243 | #define SOC_CHIP_ID_REV_LSB 8 |
| 244 | #define SOC_CHIP_ID_REV_MASK 0x00000f00 |
| 245 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 246 | #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 |
| 247 | #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 |
| 248 | #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 |
| 249 | #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 |
| 250 | |
| 251 | #define WLAN_GPIO_PIN0_ADDRESS 0x00000028 |
| 252 | #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 |
| 253 | #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c |
| 254 | #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 |
| 255 | #define WLAN_GPIO_PIN10_ADDRESS 0x00000050 |
| 256 | #define WLAN_GPIO_PIN11_ADDRESS 0x00000054 |
| 257 | #define WLAN_GPIO_PIN12_ADDRESS 0x00000058 |
| 258 | #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c |
| 259 | |
| 260 | #define CLOCK_GPIO_OFFSET 0xffffffff |
| 261 | #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 |
| 262 | #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 |
| 263 | |
| 264 | #define SI_CONFIG_OFFSET 0x00000000 |
| 265 | #define SI_CONFIG_BIDIR_OD_DATA_LSB 18 |
| 266 | #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 |
| 267 | #define SI_CONFIG_I2C_LSB 16 |
| 268 | #define SI_CONFIG_I2C_MASK 0x00010000 |
| 269 | #define SI_CONFIG_POS_SAMPLE_LSB 7 |
| 270 | #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 |
| 271 | #define SI_CONFIG_INACTIVE_DATA_LSB 5 |
| 272 | #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 |
| 273 | #define SI_CONFIG_INACTIVE_CLK_LSB 4 |
| 274 | #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 |
| 275 | #define SI_CONFIG_DIVIDER_LSB 0 |
| 276 | #define SI_CONFIG_DIVIDER_MASK 0x0000000f |
| 277 | #define SI_CS_OFFSET 0x00000004 |
| 278 | #define SI_CS_DONE_ERR_MASK 0x00000400 |
| 279 | #define SI_CS_DONE_INT_MASK 0x00000200 |
| 280 | #define SI_CS_START_LSB 8 |
| 281 | #define SI_CS_START_MASK 0x00000100 |
| 282 | #define SI_CS_RX_CNT_LSB 4 |
| 283 | #define SI_CS_RX_CNT_MASK 0x000000f0 |
| 284 | #define SI_CS_TX_CNT_LSB 0 |
| 285 | #define SI_CS_TX_CNT_MASK 0x0000000f |
| 286 | |
| 287 | #define SI_TX_DATA0_OFFSET 0x00000008 |
| 288 | #define SI_TX_DATA1_OFFSET 0x0000000c |
| 289 | #define SI_RX_DATA0_OFFSET 0x00000010 |
| 290 | #define SI_RX_DATA1_OFFSET 0x00000014 |
| 291 | |
| 292 | #define CORE_CTRL_CPU_INTR_MASK 0x00002000 |
| 293 | #define CORE_CTRL_ADDRESS 0x0000 |
| 294 | #define PCIE_INTR_ENABLE_ADDRESS 0x0008 |
Michal Kazior | e539887 | 2013-11-25 14:06:20 +0100 | [diff] [blame] | 295 | #define PCIE_INTR_CAUSE_ADDRESS 0x000c |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 296 | #define PCIE_INTR_CLR_ADDRESS 0x0014 |
| 297 | #define SCRATCH_3_ADDRESS 0x0030 |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 298 | #define CPU_INTR_ADDRESS 0x0010 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 299 | |
| 300 | /* Firmware indications to the Host via SCRATCH_3 register. */ |
| 301 | #define FW_INDICATOR_ADDRESS (SOC_CORE_BASE_ADDRESS + SCRATCH_3_ADDRESS) |
| 302 | #define FW_IND_EVENT_PENDING 1 |
| 303 | #define FW_IND_INITIALIZED 2 |
| 304 | |
| 305 | /* HOST_REG interrupt from firmware */ |
| 306 | #define PCIE_INTR_FIRMWARE_MASK 0x00000400 |
| 307 | #define PCIE_INTR_CE_MASK_ALL 0x0007f800 |
| 308 | |
| 309 | #define DRAM_BASE_ADDRESS 0x00400000 |
| 310 | |
| 311 | #define MISSING 0 |
| 312 | |
| 313 | #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET |
| 314 | #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET |
| 315 | #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET |
| 316 | #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET |
| 317 | #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK |
| 318 | #define RESET_CONTROL_MBOX_RST_MASK MISSING |
| 319 | #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK |
| 320 | #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS |
| 321 | #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS |
| 322 | #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS |
| 323 | #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK |
| 324 | #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK |
| 325 | #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS |
| 326 | #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS |
| 327 | #define LOCAL_SCRATCH_OFFSET 0x18 |
| 328 | #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET |
| 329 | #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET |
| 330 | #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS |
| 331 | #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS |
| 332 | #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS |
| 333 | #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS |
| 334 | #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB |
| 335 | #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK |
| 336 | #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB |
| 337 | #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK |
| 338 | #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS |
| 339 | #define MBOX_BASE_ADDRESS MISSING |
| 340 | #define INT_STATUS_ENABLE_ERROR_LSB MISSING |
| 341 | #define INT_STATUS_ENABLE_ERROR_MASK MISSING |
| 342 | #define INT_STATUS_ENABLE_CPU_LSB MISSING |
| 343 | #define INT_STATUS_ENABLE_CPU_MASK MISSING |
| 344 | #define INT_STATUS_ENABLE_COUNTER_LSB MISSING |
| 345 | #define INT_STATUS_ENABLE_COUNTER_MASK MISSING |
| 346 | #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING |
| 347 | #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING |
| 348 | #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING |
| 349 | #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING |
| 350 | #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING |
| 351 | #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING |
| 352 | #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING |
| 353 | #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING |
| 354 | #define INT_STATUS_ENABLE_ADDRESS MISSING |
| 355 | #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING |
| 356 | #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING |
| 357 | #define HOST_INT_STATUS_ADDRESS MISSING |
| 358 | #define CPU_INT_STATUS_ADDRESS MISSING |
| 359 | #define ERROR_INT_STATUS_ADDRESS MISSING |
| 360 | #define ERROR_INT_STATUS_WAKEUP_MASK MISSING |
| 361 | #define ERROR_INT_STATUS_WAKEUP_LSB MISSING |
| 362 | #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING |
| 363 | #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING |
| 364 | #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING |
| 365 | #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING |
| 366 | #define COUNT_DEC_ADDRESS MISSING |
| 367 | #define HOST_INT_STATUS_CPU_MASK MISSING |
| 368 | #define HOST_INT_STATUS_CPU_LSB MISSING |
| 369 | #define HOST_INT_STATUS_ERROR_MASK MISSING |
| 370 | #define HOST_INT_STATUS_ERROR_LSB MISSING |
| 371 | #define HOST_INT_STATUS_COUNTER_MASK MISSING |
| 372 | #define HOST_INT_STATUS_COUNTER_LSB MISSING |
| 373 | #define RX_LOOKAHEAD_VALID_ADDRESS MISSING |
| 374 | #define WINDOW_DATA_ADDRESS MISSING |
| 375 | #define WINDOW_READ_ADDR_ADDRESS MISSING |
| 376 | #define WINDOW_WRITE_ADDR_ADDRESS MISSING |
| 377 | |
| 378 | #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) |
| 379 | |
| 380 | #endif /* _HW_H_ */ |