| Andy Shevchenko | 61a7649 | 2013-06-05 15:26:44 +0300 | [diff] [blame] | 1 | # |
| 2 | # DMA engine configuration for dw |
| 3 | # |
| 4 | |
| Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 5 | config DW_DMAC_CORE |
| Vinod Koul | cdde0e6 | 2015-04-22 12:24:13 +0530 | [diff] [blame] | 6 | tristate |
| Andy Shevchenko | 61a7649 | 2013-06-05 15:26:44 +0300 | [diff] [blame] | 7 | select DMA_ENGINE |
| Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 8 | |
| Vinod Koul | 6c310c4 | 2015-08-24 13:43:14 +0530 | [diff] [blame] | 9 | config DW_DMAC_BIG_ENDIAN_IO |
| 10 | bool |
| 11 | |
| Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 12 | config DW_DMAC |
| 13 | tristate "Synopsys DesignWare AHB DMA platform driver" |
| 14 | select DW_DMAC_CORE |
| Vinod Koul | e368b51 | 2013-06-12 13:39:57 +0530 | [diff] [blame] | 15 | select DW_DMAC_BIG_ENDIAN_IO if AVR32 |
| Andy Shevchenko | 61a7649 | 2013-06-05 15:26:44 +0300 | [diff] [blame] | 16 | default y if CPU_AT32AP7000 |
| 17 | help |
| 18 | Support the Synopsys DesignWare AHB DMA controller. This |
| 19 | can be integrated in chips such as the Atmel AT32ap7000. |
| 20 | |
| Andy Shevchenko | fed42c1 | 2013-06-05 15:26:46 +0300 | [diff] [blame] | 21 | config DW_DMAC_PCI |
| 22 | tristate "Synopsys DesignWare AHB DMA PCI driver" |
| 23 | depends on PCI |
| 24 | select DW_DMAC_CORE |
| 25 | help |
| 26 | Support the Synopsys DesignWare AHB DMA controller on the |
| 27 | platfroms that enumerate it as a PCI device. For example, |
| 28 | Intel Medfield has integrated this GPDMA controller. |