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gerrit-public.fairphone.software / kernel / msm-4.9 / bfe514279cc011304de9093a4923db09ef4eb459 / . / sound / pci / ice1712 / wm8776.c
blob: dc333cefbc759a2bf306ea53b16d7d0202c5abd3 [file] [log] [blame]
Ondrej Zarybfe514272012-10-14 21:09:21 +0200[diff] [blame^]1/*
2 * ALSA driver for ICEnsemble VT17xx
3 *
4 * Lowlevel functions for WM8776 codec
5 *
6 * Copyright (c) 2012 Ondrej Zary <linux@rainbow-software.org>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <linux/delay.h>
25#include <sound/core.h>
26#include <sound/control.h>
27#include <sound/tlv.h>
28#include "wm8776.h"
29
30/* low-level access */
31
32static void snd_wm8776_write(struct snd_wm8776 *wm, u16 addr, u16 data)
33{
34 u8 bus_addr = addr << 1 | data >> 8; /* addr + 9th data bit */
35 u8 bus_data = data & 0xff; /* remaining 8 data bits */
36
37 if (addr < WM8776_REG_RESET)
38 wm->regs[addr] = data;
39 wm->ops.write(wm, bus_addr, bus_data);
40}
41
42/* register-level functions */
43
44static void snd_wm8776_activate_ctl(struct snd_wm8776 *wm, char *ctl_name,
45 bool active)
46{
47 struct snd_card *card = wm->card;
48 struct snd_kcontrol *kctl;
49 struct snd_kcontrol_volatile *vd;
50 struct snd_ctl_elem_id elem_id;
51 unsigned int index_offset;
52
53 memset(&elem_id, 0, sizeof(elem_id));
54 strncpy(elem_id.name, ctl_name, sizeof(elem_id.name));
55 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
56 kctl = snd_ctl_find_id(card, &elem_id);
57 if (!kctl)
58 return;
59 index_offset = snd_ctl_get_ioff(kctl, &kctl->id);
60 vd = &kctl->vd[index_offset];
61 if (active)
62 vd->access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
63 else
64 vd->access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
65 snd_ctl_notify(card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
66}
67
68static void snd_wm8776_update_agc_ctl(struct snd_wm8776 *wm)
69{
70 int i, flags_on = 0, flags_off = 0;
71
72 switch (wm->agc_mode) {
73 case WM8776_AGC_OFF:
74 flags_off = WM8776_FLAG_LIM | WM8776_FLAG_ALC;
75 break;
76 case WM8776_AGC_LIM:
77 flags_off = WM8776_FLAG_ALC;
78 flags_on = WM8776_FLAG_LIM;
79 break;
80 case WM8776_AGC_ALC_R:
81 case WM8776_AGC_ALC_L:
82 case WM8776_AGC_ALC_STEREO:
83 flags_off = WM8776_FLAG_LIM;
84 flags_on = WM8776_FLAG_ALC;
85 break;
86 }
87
88 for (i = 0; i < WM8776_CTL_COUNT; i++)
89 if (wm->ctl[i].flags & flags_off)
90 snd_wm8776_activate_ctl(wm, wm->ctl[i].name, false);
91 else if (wm->ctl[i].flags & flags_on)
92 snd_wm8776_activate_ctl(wm, wm->ctl[i].name, true);
93}
94
95static void snd_wm8776_set_agc(struct snd_wm8776 *wm, u16 agc, u16 nothing)
96{
97 u16 alc1 = wm->regs[WM8776_REG_ALCCTRL1] & ~WM8776_ALC1_LCT_MASK;
98 u16 alc2 = wm->regs[WM8776_REG_ALCCTRL2] & ~WM8776_ALC2_LCEN;
99
100 switch (agc) {
101 case 0: /* Off */
102 wm->agc_mode = WM8776_AGC_OFF;
103 break;
104 case 1: /* Limiter */
105 alc2 |= WM8776_ALC2_LCEN;
106 wm->agc_mode = WM8776_AGC_LIM;
107 break;
108 case 2: /* ALC Right */
109 alc1 |= WM8776_ALC1_LCSEL_ALCR;
110 alc2 |= WM8776_ALC2_LCEN;
111 wm->agc_mode = WM8776_AGC_ALC_R;
112 break;
113 case 3: /* ALC Left */
114 alc1 |= WM8776_ALC1_LCSEL_ALCL;
115 alc2 |= WM8776_ALC2_LCEN;
116 wm->agc_mode = WM8776_AGC_ALC_L;
117 break;
118 case 4: /* ALC Stereo */
119 alc1 |= WM8776_ALC1_LCSEL_ALCSTEREO;
120 alc2 |= WM8776_ALC2_LCEN;
121 wm->agc_mode = WM8776_AGC_ALC_STEREO;
122 break;
123 }
124 snd_wm8776_write(wm, WM8776_REG_ALCCTRL1, alc1);
125 snd_wm8776_write(wm, WM8776_REG_ALCCTRL2, alc2);
126 snd_wm8776_update_agc_ctl(wm);
127}
128
129static void snd_wm8776_get_agc(struct snd_wm8776 *wm, u16 *mode, u16 *nothing)
130{
131 *mode = wm->agc_mode;
132}
133
134/* mixer controls */
135
136static const DECLARE_TLV_DB_SCALE(wm8776_hp_tlv, -7400, 100, 1);
137static const DECLARE_TLV_DB_SCALE(wm8776_dac_tlv, -12750, 50, 1);
138static const DECLARE_TLV_DB_SCALE(wm8776_adc_tlv, -10350, 50, 1);
139static const DECLARE_TLV_DB_SCALE(wm8776_lct_tlv, -1600, 100, 0);
140static const DECLARE_TLV_DB_SCALE(wm8776_maxgain_tlv, 0, 400, 0);
141static const DECLARE_TLV_DB_SCALE(wm8776_ngth_tlv, -7800, 600, 0);
142static const DECLARE_TLV_DB_SCALE(wm8776_maxatten_lim_tlv, -1200, 100, 0);
143static const DECLARE_TLV_DB_SCALE(wm8776_maxatten_alc_tlv, -2100, 400, 0);
144
145static struct snd_wm8776_ctl snd_wm8776_default_ctl[WM8776_CTL_COUNT] = {
146 [WM8776_CTL_DAC_VOL] = {
147 .name = "Master Playback Volume",
148 .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
149 .tlv = wm8776_dac_tlv,
150 .reg1 = WM8776_REG_DACLVOL,
151 .reg2 = WM8776_REG_DACRVOL,
152 .mask1 = WM8776_DACVOL_MASK,
153 .mask2 = WM8776_DACVOL_MASK,
154 .max = 0xff,
155 .flags = WM8776_FLAG_STEREO | WM8776_FLAG_VOL_UPDATE,
156 },
157 [WM8776_CTL_DAC_SW] = {
158 .name = "Master Playback Switch",
159 .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
160 .reg1 = WM8776_REG_DACCTRL1,
161 .reg2 = WM8776_REG_DACCTRL1,
162 .mask1 = WM8776_DAC_PL_LL,
163 .mask2 = WM8776_DAC_PL_RR,
164 .flags = WM8776_FLAG_STEREO,
165 },
166 [WM8776_CTL_DAC_ZC_SW] = {
167 .name = "Master Zero Cross Detect Playback Switch",
168 .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
169 .reg1 = WM8776_REG_DACCTRL1,
170 .mask1 = WM8776_DAC_DZCEN,
171 },
172 [WM8776_CTL_HP_VOL] = {
173 .name = "Headphone Playback Volume",
174 .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
175 .tlv = wm8776_hp_tlv,
176 .reg1 = WM8776_REG_HPLVOL,
177 .reg2 = WM8776_REG_HPRVOL,
178 .mask1 = WM8776_HPVOL_MASK,
179 .mask2 = WM8776_HPVOL_MASK,
180 .min = 0x2f,
181 .max = 0x7f,
182 .flags = WM8776_FLAG_STEREO | WM8776_FLAG_VOL_UPDATE,
183 },
184 [WM8776_CTL_HP_SW] = {
185 .name = "Headphone Playback Switch",
186 .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
187 .reg1 = WM8776_REG_PWRDOWN,
188 .mask1 = WM8776_PWR_HPPD,
189 .flags = WM8776_FLAG_INVERT,
190 },
191 [WM8776_CTL_HP_ZC_SW] = {
192 .name = "Headphone Zero Cross Detect Playback Switch",
193 .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
194 .reg1 = WM8776_REG_HPLVOL,
195 .reg2 = WM8776_REG_HPRVOL,
196 .mask1 = WM8776_VOL_HPZCEN,
197 .mask2 = WM8776_VOL_HPZCEN,
198 .flags = WM8776_FLAG_STEREO,
199 },
200 [WM8776_CTL_AUX_SW] = {
201 .name = "AUX Playback Switch",
202 .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
203 .reg1 = WM8776_REG_OUTMUX,
204 .mask1 = WM8776_OUTMUX_AUX,
205 },
206 [WM8776_CTL_BYPASS_SW] = {
207 .name = "Bypass Playback Switch",
208 .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
209 .reg1 = WM8776_REG_OUTMUX,
210 .mask1 = WM8776_OUTMUX_BYPASS,
211 },
212 [WM8776_CTL_DAC_IZD_SW] = {
213 .name = "Infinite Zero Detect Playback Switch",
214 .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
215 .reg1 = WM8776_REG_DACCTRL1,
216 .mask1 = WM8776_DAC_IZD,
217 },
218 [WM8776_CTL_PHASE_SW] = {
219 .name = "Phase Invert Playback Switch",
220 .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
221 .reg1 = WM8776_REG_PHASESWAP,
222 .reg2 = WM8776_REG_PHASESWAP,
223 .mask1 = WM8776_PHASE_INVERTL,
224 .mask2 = WM8776_PHASE_INVERTR,
225 .flags = WM8776_FLAG_STEREO,
226 },
227 [WM8776_CTL_DEEMPH_SW] = {
228 .name = "Deemphasis Playback Switch",
229 .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
230 .reg1 = WM8776_REG_DACCTRL2,
231 .mask1 = WM8776_DAC2_DEEMPH,
232 },
233 [WM8776_CTL_ADC_VOL] = {
234 .name = "Input Capture Volume",
235 .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
236 .tlv = wm8776_adc_tlv,
237 .reg1 = WM8776_REG_ADCLVOL,
238 .reg2 = WM8776_REG_ADCRVOL,
239 .mask1 = WM8776_ADC_GAIN_MASK,
240 .mask2 = WM8776_ADC_GAIN_MASK,
241 .max = 0xff,
242 .flags = WM8776_FLAG_STEREO | WM8776_FLAG_VOL_UPDATE,
243 },
244 [WM8776_CTL_ADC_SW] = {
245 .name = "Input Capture Switch",
246 .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
247 .reg1 = WM8776_REG_ADCMUX,
248 .reg2 = WM8776_REG_ADCMUX,
249 .mask1 = WM8776_ADC_MUTEL,
250 .mask2 = WM8776_ADC_MUTER,
251 .flags = WM8776_FLAG_STEREO | WM8776_FLAG_INVERT,
252 },
253 [WM8776_CTL_INPUT1_SW] = {
254 .name = "AIN1 Capture Switch",
255 .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
256 .reg1 = WM8776_REG_ADCMUX,
257 .mask1 = WM8776_ADC_MUX_AIN1,
258 },
259 [WM8776_CTL_INPUT2_SW] = {
260 .name = "AIN2 Capture Switch",
261 .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
262 .reg1 = WM8776_REG_ADCMUX,
263 .mask1 = WM8776_ADC_MUX_AIN2,
264 },
265 [WM8776_CTL_INPUT3_SW] = {
266 .name = "AIN3 Capture Switch",
267 .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
268 .reg1 = WM8776_REG_ADCMUX,
269 .mask1 = WM8776_ADC_MUX_AIN3,
270 },
271 [WM8776_CTL_INPUT4_SW] = {
272 .name = "AIN4 Capture Switch",
273 .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
274 .reg1 = WM8776_REG_ADCMUX,
275 .mask1 = WM8776_ADC_MUX_AIN4,
276 },
277 [WM8776_CTL_INPUT5_SW] = {
278 .name = "AIN5 Capture Switch",
279 .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
280 .reg1 = WM8776_REG_ADCMUX,
281 .mask1 = WM8776_ADC_MUX_AIN5,
282 },
283 [WM8776_CTL_AGC_SEL] = {
284 .name = "AGC Select Capture Enum",
285 .type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
286 .enum_names = { "Off", "Limiter", "ALC Right", "ALC Left",
287 "ALC Stereo" },
288 .max = 5, /* .enum_names item count */
289 .set = snd_wm8776_set_agc,
290 .get = snd_wm8776_get_agc,
291 },
292 [WM8776_CTL_LIM_THR] = {
293 .name = "Limiter Threshold Capture Volume",
294 .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
295 .tlv = wm8776_lct_tlv,
296 .reg1 = WM8776_REG_ALCCTRL1,
297 .mask1 = WM8776_ALC1_LCT_MASK,
298 .max = 15,
299 .flags = WM8776_FLAG_LIM,
300 },
301 [WM8776_CTL_LIM_ATK] = {
302 .name = "Limiter Attack Time Capture Enum",
303 .type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
304 .enum_names = { "0.25 ms", "0.5 ms", "1 ms", "2 ms", "4 ms",
305 "8 ms", "16 ms", "32 ms", "64 ms", "128 ms", "256 ms" },
306 .max = 11, /* .enum_names item count */
307 .reg1 = WM8776_REG_ALCCTRL3,
308 .mask1 = WM8776_ALC3_ATK_MASK,
309 .flags = WM8776_FLAG_LIM,
310 },
311 [WM8776_CTL_LIM_DCY] = {
312 .name = "Limiter Decay Time Capture Enum",
313 .type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
314 .enum_names = { "1.2 ms", "2.4 ms", "4.8 ms", "9.6 ms",
315 "19.2 ms", "38.4 ms", "76.8 ms", "154 ms", "307 ms",
316 "614 ms", "1.23 s" },
317 .max = 11, /* .enum_names item count */
318 .reg1 = WM8776_REG_ALCCTRL3,
319 .mask1 = WM8776_ALC3_DCY_MASK,
320 .flags = WM8776_FLAG_LIM,
321 },
322 [WM8776_CTL_LIM_TRANWIN] = {
323 .name = "Limiter Transient Window Capture Enum",
324 .type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
325 .enum_names = { "0 us", "62.5 us", "125 us", "250 us", "500 us",
326 "1 ms", "2 ms", "4 ms" },
327 .max = 8, /* .enum_names item count */
328 .reg1 = WM8776_REG_LIMITER,
329 .mask1 = WM8776_LIM_TRANWIN_MASK,
330 .flags = WM8776_FLAG_LIM,
331 },
332 [WM8776_CTL_LIM_MAXATTN] = {
333 .name = "Limiter Maximum Attenuation Capture Volume",
334 .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
335 .tlv = wm8776_maxatten_lim_tlv,
336 .reg1 = WM8776_REG_LIMITER,
337 .mask1 = WM8776_LIM_MAXATTEN_MASK,
338 .min = 3,
339 .max = 12,
340 .flags = WM8776_FLAG_LIM | WM8776_FLAG_INVERT,
341 },
342 [WM8776_CTL_ALC_TGT] = {
343 .name = "ALC Target Level Capture Volume",
344 .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
345 .tlv = wm8776_lct_tlv,
346 .reg1 = WM8776_REG_ALCCTRL1,
347 .mask1 = WM8776_ALC1_LCT_MASK,
348 .max = 15,
349 .flags = WM8776_FLAG_ALC,
350 },
351 [WM8776_CTL_ALC_ATK] = {
352 .name = "ALC Attack Time Capture Enum",
353 .type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
354 .enum_names = { "8.40 ms", "16.8 ms", "33.6 ms", "67.2 ms",
355 "134 ms", "269 ms", "538 ms", "1.08 s", "2.15 s",
356 "4.3 s", "8.6 s" },
357 .max = 11, /* .enum_names item count */
358 .reg1 = WM8776_REG_ALCCTRL3,
359 .mask1 = WM8776_ALC3_ATK_MASK,
360 .flags = WM8776_FLAG_ALC,
361 },
362 [WM8776_CTL_ALC_DCY] = {
363 .name = "ALC Decay Time Capture Enum",
364 .type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
365 .enum_names = { "33.5 ms", "67.0 ms", "134 ms", "268 ms",
366 "536 ms", "1.07 s", "2.14 s", "4.29 s", "8.58 s",
367 "17.2 s", "34.3 s" },
368 .max = 11, /* .enum_names item count */
369 .reg1 = WM8776_REG_ALCCTRL3,
370 .mask1 = WM8776_ALC3_DCY_MASK,
371 .flags = WM8776_FLAG_ALC,
372 },
373 [WM8776_CTL_ALC_MAXGAIN] = {
374 .name = "ALC Maximum Gain Capture Volume",
375 .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
376 .tlv = wm8776_maxgain_tlv,
377 .reg1 = WM8776_REG_ALCCTRL1,
378 .mask1 = WM8776_ALC1_MAXGAIN_MASK,
379 .min = 1,
380 .max = 7,
381 .flags = WM8776_FLAG_ALC,
382 },
383 [WM8776_CTL_ALC_MAXATTN] = {
384 .name = "ALC Maximum Attenuation Capture Volume",
385 .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
386 .tlv = wm8776_maxatten_alc_tlv,
387 .reg1 = WM8776_REG_LIMITER,
388 .mask1 = WM8776_LIM_MAXATTEN_MASK,
389 .min = 10,
390 .max = 15,
391 .flags = WM8776_FLAG_ALC | WM8776_FLAG_INVERT,
392 },
393 [WM8776_CTL_ALC_HLD] = {
394 .name = "ALC Hold Time Capture Enum",
395 .type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
396 .enum_names = { "0 ms", "2.67 ms", "5.33 ms", "10.6 ms",
397 "21.3 ms", "42.7 ms", "85.3 ms", "171 ms", "341 ms",
398 "683 ms", "1.37 s", "2.73 s", "5.46 s", "10.9 s",
399 "21.8 s", "43.7 s" },
400 .max = 16, /* .enum_names item count */
401 .reg1 = WM8776_REG_ALCCTRL2,
402 .mask1 = WM8776_ALC2_HOLD_MASK,
403 .flags = WM8776_FLAG_ALC,
404 },
405 [WM8776_CTL_NGT_SW] = {
406 .name = "Noise Gate Capture Switch",
407 .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
408 .reg1 = WM8776_REG_NOISEGATE,
409 .mask1 = WM8776_NGAT_ENABLE,
410 .flags = WM8776_FLAG_ALC,
411 },
412 [WM8776_CTL_NGT_THR] = {
413 .name = "Noise Gate Threshold Capture Volume",
414 .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
415 .tlv = wm8776_ngth_tlv,
416 .reg1 = WM8776_REG_NOISEGATE,
417 .mask1 = WM8776_NGAT_THR_MASK,
418 .max = 7,
419 .flags = WM8776_FLAG_ALC,
420 },
421};
422
423/* exported functions */
424
425void snd_wm8776_init(struct snd_wm8776 *wm)
426{
427 int i;
428 static const u16 default_values[] = {
429 0x000, 0x100, 0x000,
430 0x000, 0x100, 0x000,
431 0x000, 0x090, 0x000, 0x000,
432 0x022, 0x022, 0x022,
433 0x008, 0x0cf, 0x0cf, 0x07b, 0x000,
434 0x032, 0x000, 0x0a6, 0x001, 0x001
435 };
436
437 memcpy(wm->ctl, snd_wm8776_default_ctl, sizeof(wm->ctl));
438
439 snd_wm8776_write(wm, WM8776_REG_RESET, 0x00); /* reset */
440 udelay(10);
441 /* load defaults */
442 for (i = 0; i < ARRAY_SIZE(default_values); i++)
443 snd_wm8776_write(wm, i, default_values[i]);
444}
445
446void snd_wm8776_resume(struct snd_wm8776 *wm)
447{
448 int i;
449
450 for (i = 0; i < WM8776_REG_COUNT; i++)
451 snd_wm8776_write(wm, i, wm->regs[i]);
452}
453
454void snd_wm8776_set_dac_if(struct snd_wm8776 *wm, u16 dac)
455{
456 snd_wm8776_write(wm, WM8776_REG_DACIFCTRL, dac);
457}
458
459void snd_wm8776_set_adc_if(struct snd_wm8776 *wm, u16 adc)
460{
461 snd_wm8776_write(wm, WM8776_REG_ADCIFCTRL, adc);
462}
463
464void snd_wm8776_set_master_mode(struct snd_wm8776 *wm, u16 mode)
465{
466 snd_wm8776_write(wm, WM8776_REG_MSTRCTRL, mode);
467}
468
469void snd_wm8776_set_power(struct snd_wm8776 *wm, u16 power)
470{
471 snd_wm8776_write(wm, WM8776_REG_PWRDOWN, power);
472}
473
474void snd_wm8776_volume_restore(struct snd_wm8776 *wm)
475{
476 u16 val = wm->regs[WM8776_REG_DACRVOL];
477 /* restore volume after MCLK stopped */
478 snd_wm8776_write(wm, WM8776_REG_DACRVOL, val | WM8776_VOL_UPDATE);
479}
480
481/* mixer callbacks */
482
483static int snd_wm8776_volume_info(struct snd_kcontrol *kcontrol,
484 struct snd_ctl_elem_info *uinfo)
485{
486 struct snd_wm8776 *wm = snd_kcontrol_chip(kcontrol);
487 int n = kcontrol->private_value;
488
489 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
490 uinfo->count = (wm->ctl[n].flags & WM8776_FLAG_STEREO) ? 2 : 1;
491 uinfo->value.integer.min = wm->ctl[n].min;
492 uinfo->value.integer.max = wm->ctl[n].max;
493
494 return 0;
495}
496
497static int snd_wm8776_enum_info(struct snd_kcontrol *kcontrol,
498 struct snd_ctl_elem_info *uinfo)
499{
500 struct snd_wm8776 *wm = snd_kcontrol_chip(kcontrol);
501 int n = kcontrol->private_value;
502
503 return snd_ctl_enum_info(uinfo, 1, wm->ctl[n].max,
504 wm->ctl[n].enum_names);
505}
506
507static int snd_wm8776_ctl_get(struct snd_kcontrol *kcontrol,
508 struct snd_ctl_elem_value *ucontrol)
509{
510 struct snd_wm8776 *wm = snd_kcontrol_chip(kcontrol);
511 int n = kcontrol->private_value;
512 u16 val1, val2;
513
514 if (wm->ctl[n].get)
515 wm->ctl[n].get(wm, &val1, &val2);
516 else {
517 val1 = wm->regs[wm->ctl[n].reg1] & wm->ctl[n].mask1;
518 val1 >>= __ffs(wm->ctl[n].mask1);
519 if (wm->ctl[n].flags & WM8776_FLAG_STEREO) {
520 val2 = wm->regs[wm->ctl[n].reg2] & wm->ctl[n].mask2;
521 val2 >>= __ffs(wm->ctl[n].mask2);
522 if (wm->ctl[n].flags & WM8776_FLAG_VOL_UPDATE)
523 val2 &= ~WM8776_VOL_UPDATE;
524 }
525 }
526 if (wm->ctl[n].flags & WM8776_FLAG_INVERT) {
527 val1 = wm->ctl[n].max - (val1 - wm->ctl[n].min);
528 val2 = wm->ctl[n].max - (val2 - wm->ctl[n].min);
529 }
530 ucontrol->value.integer.value[0] = val1;
531 if (wm->ctl[n].flags & WM8776_FLAG_STEREO)
532 ucontrol->value.integer.value[1] = val2;
533
534 return 0;
535}
536
537static int snd_wm8776_ctl_put(struct snd_kcontrol *kcontrol,
538 struct snd_ctl_elem_value *ucontrol)
539{
540 struct snd_wm8776 *wm = snd_kcontrol_chip(kcontrol);
541 int n = kcontrol->private_value;
542 u16 val, regval1, regval2;
543
544 /* this also works for enum because value is an union */
545 regval1 = ucontrol->value.integer.value[0];
546 regval2 = ucontrol->value.integer.value[1];
547 if (wm->ctl[n].flags & WM8776_FLAG_INVERT) {
548 regval1 = wm->ctl[n].max - (regval1 - wm->ctl[n].min);
549 regval2 = wm->ctl[n].max - (regval2 - wm->ctl[n].min);
550 }
551 if (wm->ctl[n].set)
552 wm->ctl[n].set(wm, regval1, regval2);
553 else {
554 val = wm->regs[wm->ctl[n].reg1] & ~wm->ctl[n].mask1;
555 val |= regval1 << __ffs(wm->ctl[n].mask1);
556 /* both stereo controls in one register */
557 if (wm->ctl[n].flags & WM8776_FLAG_STEREO &&
558 wm->ctl[n].reg1 == wm->ctl[n].reg2) {
559 val &= ~wm->ctl[n].mask2;
560 val |= regval2 << __ffs(wm->ctl[n].mask2);
561 }
562 snd_wm8776_write(wm, wm->ctl[n].reg1, val);
563 /* stereo controls in different registers */
564 if (wm->ctl[n].flags & WM8776_FLAG_STEREO &&
565 wm->ctl[n].reg1 != wm->ctl[n].reg2) {
566 val = wm->regs[wm->ctl[n].reg2] & ~wm->ctl[n].mask2;
567 val |= regval2 << __ffs(wm->ctl[n].mask2);
568 if (wm->ctl[n].flags & WM8776_FLAG_VOL_UPDATE)
569 val |= WM8776_VOL_UPDATE;
570 snd_wm8776_write(wm, wm->ctl[n].reg2, val);
571 }
572 }
573
574 return 0;
575}
576
577static int snd_wm8776_add_control(struct snd_wm8776 *wm, int num)
578{
579 struct snd_kcontrol_new cont;
580 struct snd_kcontrol *ctl;
581
582 memset(&cont, 0, sizeof(cont));
583 cont.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
584 cont.private_value = num;
585 cont.name = wm->ctl[num].name;
586 cont.access = SNDRV_CTL_ELEM_ACCESS_READWRITE;
587 if (wm->ctl[num].flags & WM8776_FLAG_LIM ||
588 wm->ctl[num].flags & WM8776_FLAG_ALC)
589 cont.access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
590 cont.tlv.p = NULL;
591 cont.get = snd_wm8776_ctl_get;
592 cont.put = snd_wm8776_ctl_put;
593
594 switch (wm->ctl[num].type) {
595 case SNDRV_CTL_ELEM_TYPE_INTEGER:
596 cont.info = snd_wm8776_volume_info;
597 cont.access |= SNDRV_CTL_ELEM_ACCESS_TLV_READ;
598 cont.tlv.p = wm->ctl[num].tlv;
599 break;
600 case SNDRV_CTL_ELEM_TYPE_BOOLEAN:
601 wm->ctl[num].max = 1;
602 if (wm->ctl[num].flags & WM8776_FLAG_STEREO)
603 cont.info = snd_ctl_boolean_stereo_info;
604 else
605 cont.info = snd_ctl_boolean_mono_info;
606 break;
607 case SNDRV_CTL_ELEM_TYPE_ENUMERATED:
608 cont.info = snd_wm8776_enum_info;
609 break;
610 default:
611 return -EINVAL;
612 }
613 ctl = snd_ctl_new1(&cont, wm);
614 if (!ctl)
615 return -ENOMEM;
616
617 return snd_ctl_add(wm->card, ctl);
618}
619
620int snd_wm8776_build_controls(struct snd_wm8776 *wm)
621{
622 int err, i;
623
624 for (i = 0; i < WM8776_CTL_COUNT; i++)
625 if (wm->ctl[i].name) {
626 err = snd_wm8776_add_control(wm, i);
627 if (err < 0)
628 return err;
629 }
630
631 return 0;
632}