Yevgeny Petrilin | c27a02c | 2008-10-22 15:47:49 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. |
| 3 | * |
| 4 | * This software is available to you under a choice of one of two |
| 5 | * licenses. You may choose to be licensed under the terms of the GNU |
| 6 | * General Public License (GPL) Version 2, available from the file |
| 7 | * COPYING in the main directory of this source tree, or the |
| 8 | * OpenIB.org BSD license below: |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or |
| 11 | * without modification, are permitted provided that the following |
| 12 | * conditions are met: |
| 13 | * |
| 14 | * - Redistributions of source code must retain the above |
| 15 | * copyright notice, this list of conditions and the following |
| 16 | * disclaimer. |
| 17 | * |
| 18 | * - Redistributions in binary form must reproduce the above |
| 19 | * copyright notice, this list of conditions and the following |
| 20 | * disclaimer in the documentation and/or other materials |
| 21 | * provided with the distribution. |
| 22 | * |
| 23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 30 | * SOFTWARE. |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #include <asm/page.h> |
| 35 | #include <linux/mlx4/cq.h> |
| 36 | #include <linux/mlx4/qp.h> |
| 37 | #include <linux/skbuff.h> |
| 38 | #include <linux/if_vlan.h> |
| 39 | #include <linux/vmalloc.h> |
| 40 | |
| 41 | #include "mlx4_en.h" |
| 42 | |
| 43 | enum { |
| 44 | MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */ |
| 45 | }; |
| 46 | |
| 47 | static int inline_thold __read_mostly = MAX_INLINE; |
| 48 | |
| 49 | module_param_named(inline_thold, inline_thold, int, 0444); |
| 50 | MODULE_PARM_DESC(inline_thold, "treshold for using inline data"); |
| 51 | |
| 52 | int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, |
| 53 | struct mlx4_en_tx_ring *ring, u32 size, |
| 54 | u16 stride) |
| 55 | { |
| 56 | struct mlx4_en_dev *mdev = priv->mdev; |
| 57 | int tmp; |
| 58 | int err; |
| 59 | |
| 60 | ring->size = size; |
| 61 | ring->size_mask = size - 1; |
| 62 | ring->stride = stride; |
| 63 | |
| 64 | inline_thold = min(inline_thold, MAX_INLINE); |
| 65 | |
| 66 | spin_lock_init(&ring->comp_lock); |
| 67 | |
| 68 | tmp = size * sizeof(struct mlx4_en_tx_info); |
| 69 | ring->tx_info = vmalloc(tmp); |
| 70 | if (!ring->tx_info) { |
| 71 | mlx4_err(mdev, "Failed allocating tx_info ring\n"); |
| 72 | return -ENOMEM; |
| 73 | } |
| 74 | mlx4_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", |
| 75 | ring->tx_info, tmp); |
| 76 | |
| 77 | ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); |
| 78 | if (!ring->bounce_buf) { |
| 79 | mlx4_err(mdev, "Failed allocating bounce buffer\n"); |
| 80 | err = -ENOMEM; |
| 81 | goto err_tx; |
| 82 | } |
| 83 | ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE); |
| 84 | |
| 85 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size, |
| 86 | 2 * PAGE_SIZE); |
| 87 | if (err) { |
| 88 | mlx4_err(mdev, "Failed allocating hwq resources\n"); |
| 89 | goto err_bounce; |
| 90 | } |
| 91 | |
| 92 | err = mlx4_en_map_buffer(&ring->wqres.buf); |
| 93 | if (err) { |
| 94 | mlx4_err(mdev, "Failed to map TX buffer\n"); |
| 95 | goto err_hwq_res; |
| 96 | } |
| 97 | |
| 98 | ring->buf = ring->wqres.buf.direct.buf; |
| 99 | |
| 100 | mlx4_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d " |
| 101 | "buf_size:%d dma:%llx\n", ring, ring->buf, ring->size, |
| 102 | ring->buf_size, (unsigned long long) ring->wqres.buf.direct.map); |
| 103 | |
| 104 | err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn); |
| 105 | if (err) { |
| 106 | mlx4_err(mdev, "Failed reserving qp for tx ring.\n"); |
| 107 | goto err_map; |
| 108 | } |
| 109 | |
| 110 | err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp); |
| 111 | if (err) { |
| 112 | mlx4_err(mdev, "Failed allocating qp %d\n", ring->qpn); |
| 113 | goto err_reserve; |
| 114 | } |
| 115 | |
| 116 | return 0; |
| 117 | |
| 118 | err_reserve: |
| 119 | mlx4_qp_release_range(mdev->dev, ring->qpn, 1); |
| 120 | err_map: |
| 121 | mlx4_en_unmap_buffer(&ring->wqres.buf); |
| 122 | err_hwq_res: |
| 123 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); |
| 124 | err_bounce: |
| 125 | kfree(ring->bounce_buf); |
| 126 | ring->bounce_buf = NULL; |
| 127 | err_tx: |
| 128 | vfree(ring->tx_info); |
| 129 | ring->tx_info = NULL; |
| 130 | return err; |
| 131 | } |
| 132 | |
| 133 | void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, |
| 134 | struct mlx4_en_tx_ring *ring) |
| 135 | { |
| 136 | struct mlx4_en_dev *mdev = priv->mdev; |
| 137 | mlx4_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); |
| 138 | |
| 139 | mlx4_qp_remove(mdev->dev, &ring->qp); |
| 140 | mlx4_qp_free(mdev->dev, &ring->qp); |
| 141 | mlx4_qp_release_range(mdev->dev, ring->qpn, 1); |
| 142 | mlx4_en_unmap_buffer(&ring->wqres.buf); |
| 143 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); |
| 144 | kfree(ring->bounce_buf); |
| 145 | ring->bounce_buf = NULL; |
| 146 | vfree(ring->tx_info); |
| 147 | ring->tx_info = NULL; |
| 148 | } |
| 149 | |
| 150 | int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, |
| 151 | struct mlx4_en_tx_ring *ring, |
| 152 | int cq, int srqn) |
| 153 | { |
| 154 | struct mlx4_en_dev *mdev = priv->mdev; |
| 155 | int err; |
| 156 | |
| 157 | ring->cqn = cq; |
| 158 | ring->prod = 0; |
| 159 | ring->cons = 0xffffffff; |
| 160 | ring->last_nr_txbb = 1; |
| 161 | ring->poll_cnt = 0; |
| 162 | ring->blocked = 0; |
| 163 | memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); |
| 164 | memset(ring->buf, 0, ring->buf_size); |
| 165 | |
| 166 | ring->qp_state = MLX4_QP_STATE_RST; |
| 167 | ring->doorbell_qpn = swab32(ring->qp.qpn << 8); |
| 168 | |
| 169 | mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn, |
| 170 | ring->cqn, srqn, &ring->context); |
| 171 | |
| 172 | err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context, |
| 173 | &ring->qp, &ring->qp_state); |
| 174 | |
| 175 | return err; |
| 176 | } |
| 177 | |
| 178 | void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, |
| 179 | struct mlx4_en_tx_ring *ring) |
| 180 | { |
| 181 | struct mlx4_en_dev *mdev = priv->mdev; |
| 182 | |
| 183 | mlx4_qp_modify(mdev->dev, NULL, ring->qp_state, |
| 184 | MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp); |
| 185 | } |
| 186 | |
| 187 | |
| 188 | static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, |
| 189 | struct mlx4_en_tx_ring *ring, |
| 190 | int index, u8 owner) |
| 191 | { |
| 192 | struct mlx4_en_dev *mdev = priv->mdev; |
| 193 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; |
| 194 | struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; |
| 195 | struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; |
| 196 | struct sk_buff *skb = tx_info->skb; |
| 197 | struct skb_frag_struct *frag; |
| 198 | void *end = ring->buf + ring->buf_size; |
| 199 | int frags = skb_shinfo(skb)->nr_frags; |
| 200 | int i; |
| 201 | __be32 *ptr = (__be32 *)tx_desc; |
| 202 | __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); |
| 203 | |
| 204 | /* Optimize the common case when there are no wraparounds */ |
| 205 | if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { |
| 206 | if (tx_info->linear) { |
| 207 | pci_unmap_single(mdev->pdev, |
| 208 | (dma_addr_t) be64_to_cpu(data->addr), |
| 209 | be32_to_cpu(data->byte_count), |
| 210 | PCI_DMA_TODEVICE); |
| 211 | ++data; |
| 212 | } |
| 213 | |
| 214 | for (i = 0; i < frags; i++) { |
| 215 | frag = &skb_shinfo(skb)->frags[i]; |
| 216 | pci_unmap_page(mdev->pdev, |
| 217 | (dma_addr_t) be64_to_cpu(data[i].addr), |
| 218 | frag->size, PCI_DMA_TODEVICE); |
| 219 | } |
| 220 | /* Stamp the freed descriptor */ |
| 221 | for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) { |
| 222 | *ptr = stamp; |
| 223 | ptr += STAMP_DWORDS; |
| 224 | } |
| 225 | |
| 226 | } else { |
| 227 | if ((void *) data >= end) { |
| 228 | data = (struct mlx4_wqe_data_seg *) |
| 229 | (ring->buf + ((void *) data - end)); |
| 230 | } |
| 231 | |
| 232 | if (tx_info->linear) { |
| 233 | pci_unmap_single(mdev->pdev, |
| 234 | (dma_addr_t) be64_to_cpu(data->addr), |
| 235 | be32_to_cpu(data->byte_count), |
| 236 | PCI_DMA_TODEVICE); |
| 237 | ++data; |
| 238 | } |
| 239 | |
| 240 | for (i = 0; i < frags; i++) { |
| 241 | /* Check for wraparound before unmapping */ |
| 242 | if ((void *) data >= end) |
| 243 | data = (struct mlx4_wqe_data_seg *) ring->buf; |
| 244 | frag = &skb_shinfo(skb)->frags[i]; |
| 245 | pci_unmap_page(mdev->pdev, |
| 246 | (dma_addr_t) be64_to_cpu(data->addr), |
| 247 | frag->size, PCI_DMA_TODEVICE); |
| 248 | } |
| 249 | /* Stamp the freed descriptor */ |
| 250 | for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) { |
| 251 | *ptr = stamp; |
| 252 | ptr += STAMP_DWORDS; |
| 253 | if ((void *) ptr >= end) { |
| 254 | ptr = ring->buf; |
| 255 | stamp ^= cpu_to_be32(0x80000000); |
| 256 | } |
| 257 | } |
| 258 | |
| 259 | } |
| 260 | dev_kfree_skb_any(skb); |
| 261 | return tx_info->nr_txbb; |
| 262 | } |
| 263 | |
| 264 | |
| 265 | int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) |
| 266 | { |
| 267 | struct mlx4_en_priv *priv = netdev_priv(dev); |
| 268 | int cnt = 0; |
| 269 | |
| 270 | /* Skip last polled descriptor */ |
| 271 | ring->cons += ring->last_nr_txbb; |
| 272 | mlx4_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", |
| 273 | ring->cons, ring->prod); |
| 274 | |
| 275 | if ((u32) (ring->prod - ring->cons) > ring->size) { |
| 276 | if (netif_msg_tx_err(priv)) |
| 277 | mlx4_warn(priv->mdev, "Tx consumer passed producer!\n"); |
| 278 | return 0; |
| 279 | } |
| 280 | |
| 281 | while (ring->cons != ring->prod) { |
| 282 | ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring, |
| 283 | ring->cons & ring->size_mask, |
| 284 | !!(ring->cons & ring->size)); |
| 285 | ring->cons += ring->last_nr_txbb; |
| 286 | cnt++; |
| 287 | } |
| 288 | |
| 289 | if (cnt) |
| 290 | mlx4_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); |
| 291 | |
| 292 | return cnt; |
| 293 | } |
| 294 | |
| 295 | void mlx4_en_set_prio_map(struct mlx4_en_priv *priv, u16 *prio_map, u32 ring_num) |
| 296 | { |
| 297 | int block = 8 / ring_num; |
| 298 | int extra = 8 - (block * ring_num); |
| 299 | int num = 0; |
| 300 | u16 ring = 1; |
| 301 | int prio; |
| 302 | |
| 303 | if (ring_num == 1) { |
| 304 | for (prio = 0; prio < 8; prio++) |
| 305 | prio_map[prio] = 0; |
| 306 | return; |
| 307 | } |
| 308 | |
| 309 | for (prio = 0; prio < 8; prio++) { |
| 310 | if (extra && (num == block + 1)) { |
| 311 | ring++; |
| 312 | num = 0; |
| 313 | extra--; |
| 314 | } else if (!extra && (num == block)) { |
| 315 | ring++; |
| 316 | num = 0; |
| 317 | } |
| 318 | prio_map[prio] = ring; |
| 319 | mlx4_dbg(DRV, priv, " prio:%d --> ring:%d\n", prio, ring); |
| 320 | num++; |
| 321 | } |
| 322 | } |
| 323 | |
| 324 | static void mlx4_en_process_tx_cq(struct net_device *dev, struct mlx4_en_cq *cq) |
| 325 | { |
| 326 | struct mlx4_en_priv *priv = netdev_priv(dev); |
| 327 | struct mlx4_cq *mcq = &cq->mcq; |
| 328 | struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring]; |
| 329 | struct mlx4_cqe *cqe = cq->buf; |
| 330 | u16 index; |
| 331 | u16 new_index; |
| 332 | u32 txbbs_skipped = 0; |
| 333 | u32 cq_last_sav; |
| 334 | |
| 335 | /* index always points to the first TXBB of the last polled descriptor */ |
| 336 | index = ring->cons & ring->size_mask; |
| 337 | new_index = be16_to_cpu(cqe->wqe_index) & ring->size_mask; |
| 338 | if (index == new_index) |
| 339 | return; |
| 340 | |
| 341 | if (!priv->port_up) |
| 342 | return; |
| 343 | |
| 344 | /* |
| 345 | * We use a two-stage loop: |
| 346 | * - the first samples the HW-updated CQE |
| 347 | * - the second frees TXBBs until the last sample |
| 348 | * This lets us amortize CQE cache misses, while still polling the CQ |
| 349 | * until is quiescent. |
| 350 | */ |
| 351 | cq_last_sav = mcq->cons_index; |
| 352 | do { |
| 353 | do { |
| 354 | /* Skip over last polled CQE */ |
| 355 | index = (index + ring->last_nr_txbb) & ring->size_mask; |
| 356 | txbbs_skipped += ring->last_nr_txbb; |
| 357 | |
| 358 | /* Poll next CQE */ |
| 359 | ring->last_nr_txbb = mlx4_en_free_tx_desc( |
| 360 | priv, ring, index, |
| 361 | !!((ring->cons + txbbs_skipped) & |
| 362 | ring->size)); |
| 363 | ++mcq->cons_index; |
| 364 | |
| 365 | } while (index != new_index); |
| 366 | |
| 367 | new_index = be16_to_cpu(cqe->wqe_index) & ring->size_mask; |
| 368 | } while (index != new_index); |
| 369 | AVG_PERF_COUNTER(priv->pstats.tx_coal_avg, |
| 370 | (u32) (mcq->cons_index - cq_last_sav)); |
| 371 | |
| 372 | /* |
| 373 | * To prevent CQ overflow we first update CQ consumer and only then |
| 374 | * the ring consumer. |
| 375 | */ |
| 376 | mlx4_cq_set_ci(mcq); |
| 377 | wmb(); |
| 378 | ring->cons += txbbs_skipped; |
| 379 | |
| 380 | /* Wakeup Tx queue if this ring stopped it */ |
| 381 | if (unlikely(ring->blocked)) { |
Yevgeny Petrilin | c03ea21 | 2008-12-25 18:14:04 -0800 | [diff] [blame^] | 382 | if ((u32) (ring->prod - ring->cons) <= |
| 383 | ring->size - HEADROOM - MAX_DESC_TXBBS) { |
Yevgeny Petrilin | c27a02c | 2008-10-22 15:47:49 -0700 | [diff] [blame] | 384 | |
| 385 | /* TODO: support multiqueue netdevs. Currently, we block |
| 386 | * when *any* ring is full. Note that: |
| 387 | * - 2 Tx rings can unblock at the same time and call |
| 388 | * netif_wake_queue(), which is OK since this |
| 389 | * operation is idempotent. |
| 390 | * - We might wake the queue just after another ring |
| 391 | * stopped it. This is no big deal because the next |
| 392 | * transmission on that ring would stop the queue. |
| 393 | */ |
| 394 | ring->blocked = 0; |
| 395 | netif_wake_queue(dev); |
| 396 | priv->port_stats.wake_queue++; |
| 397 | } |
| 398 | } |
| 399 | } |
| 400 | |
| 401 | void mlx4_en_tx_irq(struct mlx4_cq *mcq) |
| 402 | { |
| 403 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); |
| 404 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); |
| 405 | struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring]; |
| 406 | |
Yevgeny Petrilin | 48374dd | 2008-12-25 18:13:45 -0800 | [diff] [blame] | 407 | if (!spin_trylock(&ring->comp_lock)) |
| 408 | return; |
Yevgeny Petrilin | c27a02c | 2008-10-22 15:47:49 -0700 | [diff] [blame] | 409 | mlx4_en_process_tx_cq(cq->dev, cq); |
Yevgeny Petrilin | 48374dd | 2008-12-25 18:13:45 -0800 | [diff] [blame] | 410 | mod_timer(&cq->timer, jiffies + 1); |
| 411 | spin_unlock(&ring->comp_lock); |
Yevgeny Petrilin | c27a02c | 2008-10-22 15:47:49 -0700 | [diff] [blame] | 412 | } |
| 413 | |
| 414 | |
| 415 | void mlx4_en_poll_tx_cq(unsigned long data) |
| 416 | { |
| 417 | struct mlx4_en_cq *cq = (struct mlx4_en_cq *) data; |
| 418 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); |
| 419 | struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring]; |
| 420 | u32 inflight; |
| 421 | |
| 422 | INC_PERF_COUNTER(priv->pstats.tx_poll); |
| 423 | |
Yevgeny Petrilin | 48374dd | 2008-12-25 18:13:45 -0800 | [diff] [blame] | 424 | if (!spin_trylock(&ring->comp_lock)) { |
| 425 | mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT); |
| 426 | return; |
| 427 | } |
Yevgeny Petrilin | c27a02c | 2008-10-22 15:47:49 -0700 | [diff] [blame] | 428 | mlx4_en_process_tx_cq(cq->dev, cq); |
| 429 | inflight = (u32) (ring->prod - ring->cons - ring->last_nr_txbb); |
| 430 | |
| 431 | /* If there are still packets in flight and the timer has not already |
| 432 | * been scheduled by the Tx routine then schedule it here to guarantee |
| 433 | * completion processing of these packets */ |
| 434 | if (inflight && priv->port_up) |
| 435 | mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT); |
| 436 | |
Yevgeny Petrilin | 48374dd | 2008-12-25 18:13:45 -0800 | [diff] [blame] | 437 | spin_unlock(&ring->comp_lock); |
Yevgeny Petrilin | c27a02c | 2008-10-22 15:47:49 -0700 | [diff] [blame] | 438 | } |
| 439 | |
| 440 | static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, |
| 441 | struct mlx4_en_tx_ring *ring, |
| 442 | u32 index, |
| 443 | unsigned int desc_size) |
| 444 | { |
| 445 | u32 copy = (ring->size - index) * TXBB_SIZE; |
| 446 | int i; |
| 447 | |
| 448 | for (i = desc_size - copy - 4; i >= 0; i -= 4) { |
| 449 | if ((i & (TXBB_SIZE - 1)) == 0) |
| 450 | wmb(); |
| 451 | |
| 452 | *((u32 *) (ring->buf + i)) = |
| 453 | *((u32 *) (ring->bounce_buf + copy + i)); |
| 454 | } |
| 455 | |
| 456 | for (i = copy - 4; i >= 4 ; i -= 4) { |
| 457 | if ((i & (TXBB_SIZE - 1)) == 0) |
| 458 | wmb(); |
| 459 | |
| 460 | *((u32 *) (ring->buf + index * TXBB_SIZE + i)) = |
| 461 | *((u32 *) (ring->bounce_buf + i)); |
| 462 | } |
| 463 | |
| 464 | /* Return real descriptor location */ |
| 465 | return ring->buf + index * TXBB_SIZE; |
| 466 | } |
| 467 | |
| 468 | static inline void mlx4_en_xmit_poll(struct mlx4_en_priv *priv, int tx_ind) |
| 469 | { |
| 470 | struct mlx4_en_cq *cq = &priv->tx_cq[tx_ind]; |
| 471 | struct mlx4_en_tx_ring *ring = &priv->tx_ring[tx_ind]; |
| 472 | |
| 473 | /* If we don't have a pending timer, set one up to catch our recent |
| 474 | post in case the interface becomes idle */ |
| 475 | if (!timer_pending(&cq->timer)) |
| 476 | mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT); |
| 477 | |
| 478 | /* Poll the CQ every mlx4_en_TX_MODER_POLL packets */ |
| 479 | if ((++ring->poll_cnt & (MLX4_EN_TX_POLL_MODER - 1)) == 0) |
Yevgeny Petrilin | 48374dd | 2008-12-25 18:13:45 -0800 | [diff] [blame] | 480 | if (spin_trylock(&ring->comp_lock)) { |
| 481 | mlx4_en_process_tx_cq(priv->dev, cq); |
| 482 | spin_unlock(&ring->comp_lock); |
| 483 | } |
Yevgeny Petrilin | c27a02c | 2008-10-22 15:47:49 -0700 | [diff] [blame] | 484 | } |
| 485 | |
| 486 | static void *get_frag_ptr(struct sk_buff *skb) |
| 487 | { |
| 488 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; |
| 489 | struct page *page = frag->page; |
| 490 | void *ptr; |
| 491 | |
| 492 | ptr = page_address(page); |
| 493 | if (unlikely(!ptr)) |
| 494 | return NULL; |
| 495 | |
| 496 | return ptr + frag->page_offset; |
| 497 | } |
| 498 | |
| 499 | static int is_inline(struct sk_buff *skb, void **pfrag) |
| 500 | { |
| 501 | void *ptr; |
| 502 | |
| 503 | if (inline_thold && !skb_is_gso(skb) && skb->len <= inline_thold) { |
| 504 | if (skb_shinfo(skb)->nr_frags == 1) { |
| 505 | ptr = get_frag_ptr(skb); |
| 506 | if (unlikely(!ptr)) |
| 507 | return 0; |
| 508 | |
| 509 | if (pfrag) |
| 510 | *pfrag = ptr; |
| 511 | |
| 512 | return 1; |
| 513 | } else if (unlikely(skb_shinfo(skb)->nr_frags)) |
| 514 | return 0; |
| 515 | else |
| 516 | return 1; |
| 517 | } |
| 518 | |
| 519 | return 0; |
| 520 | } |
| 521 | |
| 522 | static int inline_size(struct sk_buff *skb) |
| 523 | { |
| 524 | if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) |
| 525 | <= MLX4_INLINE_ALIGN) |
| 526 | return ALIGN(skb->len + CTRL_SIZE + |
| 527 | sizeof(struct mlx4_wqe_inline_seg), 16); |
| 528 | else |
| 529 | return ALIGN(skb->len + CTRL_SIZE + 2 * |
| 530 | sizeof(struct mlx4_wqe_inline_seg), 16); |
| 531 | } |
| 532 | |
| 533 | static int get_real_size(struct sk_buff *skb, struct net_device *dev, |
| 534 | int *lso_header_size) |
| 535 | { |
| 536 | struct mlx4_en_priv *priv = netdev_priv(dev); |
| 537 | struct mlx4_en_dev *mdev = priv->mdev; |
| 538 | int real_size; |
| 539 | |
| 540 | if (skb_is_gso(skb)) { |
| 541 | *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); |
| 542 | real_size = CTRL_SIZE + skb_shinfo(skb)->nr_frags * DS_SIZE + |
| 543 | ALIGN(*lso_header_size + 4, DS_SIZE); |
| 544 | if (unlikely(*lso_header_size != skb_headlen(skb))) { |
| 545 | /* We add a segment for the skb linear buffer only if |
| 546 | * it contains data */ |
| 547 | if (*lso_header_size < skb_headlen(skb)) |
| 548 | real_size += DS_SIZE; |
| 549 | else { |
| 550 | if (netif_msg_tx_err(priv)) |
| 551 | mlx4_warn(mdev, "Non-linear headers\n"); |
| 552 | dev_kfree_skb_any(skb); |
| 553 | return 0; |
| 554 | } |
| 555 | } |
| 556 | if (unlikely(*lso_header_size > MAX_LSO_HDR_SIZE)) { |
| 557 | if (netif_msg_tx_err(priv)) |
| 558 | mlx4_warn(mdev, "LSO header size too big\n"); |
| 559 | dev_kfree_skb_any(skb); |
| 560 | return 0; |
| 561 | } |
| 562 | } else { |
| 563 | *lso_header_size = 0; |
| 564 | if (!is_inline(skb, NULL)) |
| 565 | real_size = CTRL_SIZE + (skb_shinfo(skb)->nr_frags + 1) * DS_SIZE; |
| 566 | else |
| 567 | real_size = inline_size(skb); |
| 568 | } |
| 569 | |
| 570 | return real_size; |
| 571 | } |
| 572 | |
| 573 | static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, struct sk_buff *skb, |
| 574 | int real_size, u16 *vlan_tag, int tx_ind, void *fragptr) |
| 575 | { |
| 576 | struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; |
| 577 | int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl; |
| 578 | |
| 579 | if (skb->len <= spc) { |
| 580 | inl->byte_count = cpu_to_be32(1 << 31 | skb->len); |
| 581 | skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb)); |
| 582 | if (skb_shinfo(skb)->nr_frags) |
| 583 | memcpy(((void *)(inl + 1)) + skb_headlen(skb), fragptr, |
| 584 | skb_shinfo(skb)->frags[0].size); |
| 585 | |
| 586 | } else { |
| 587 | inl->byte_count = cpu_to_be32(1 << 31 | spc); |
| 588 | if (skb_headlen(skb) <= spc) { |
| 589 | skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb)); |
| 590 | if (skb_headlen(skb) < spc) { |
| 591 | memcpy(((void *)(inl + 1)) + skb_headlen(skb), |
| 592 | fragptr, spc - skb_headlen(skb)); |
| 593 | fragptr += spc - skb_headlen(skb); |
| 594 | } |
| 595 | inl = (void *) (inl + 1) + spc; |
| 596 | memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); |
| 597 | } else { |
| 598 | skb_copy_from_linear_data(skb, inl + 1, spc); |
| 599 | inl = (void *) (inl + 1) + spc; |
| 600 | skb_copy_from_linear_data_offset(skb, spc, inl + 1, |
| 601 | skb_headlen(skb) - spc); |
| 602 | if (skb_shinfo(skb)->nr_frags) |
| 603 | memcpy(((void *)(inl + 1)) + skb_headlen(skb) - spc, |
| 604 | fragptr, skb_shinfo(skb)->frags[0].size); |
| 605 | } |
| 606 | |
| 607 | wmb(); |
| 608 | inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); |
| 609 | } |
| 610 | tx_desc->ctrl.vlan_tag = cpu_to_be16(*vlan_tag); |
| 611 | tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN * !!(*vlan_tag); |
| 612 | tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f; |
| 613 | } |
| 614 | |
| 615 | static int get_vlan_info(struct mlx4_en_priv *priv, struct sk_buff *skb, |
| 616 | u16 *vlan_tag) |
| 617 | { |
| 618 | int tx_ind; |
| 619 | |
| 620 | /* Obtain VLAN information if present */ |
| 621 | if (priv->vlgrp && vlan_tx_tag_present(skb)) { |
| 622 | *vlan_tag = vlan_tx_tag_get(skb); |
| 623 | /* Set the Tx ring to use according to vlan priority */ |
| 624 | tx_ind = priv->tx_prio_map[*vlan_tag >> 13]; |
| 625 | } else { |
| 626 | *vlan_tag = 0; |
| 627 | tx_ind = 0; |
| 628 | } |
| 629 | return tx_ind; |
| 630 | } |
| 631 | |
| 632 | int mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) |
| 633 | { |
| 634 | struct mlx4_en_priv *priv = netdev_priv(dev); |
| 635 | struct mlx4_en_dev *mdev = priv->mdev; |
| 636 | struct mlx4_en_tx_ring *ring; |
| 637 | struct mlx4_en_cq *cq; |
| 638 | struct mlx4_en_tx_desc *tx_desc; |
| 639 | struct mlx4_wqe_data_seg *data; |
| 640 | struct skb_frag_struct *frag; |
| 641 | struct mlx4_en_tx_info *tx_info; |
| 642 | int tx_ind = 0; |
| 643 | int nr_txbb; |
| 644 | int desc_size; |
| 645 | int real_size; |
| 646 | dma_addr_t dma; |
| 647 | u32 index; |
| 648 | __be32 op_own; |
| 649 | u16 vlan_tag; |
| 650 | int i; |
| 651 | int lso_header_size; |
| 652 | void *fragptr; |
| 653 | |
| 654 | if (unlikely(!skb->len)) { |
| 655 | dev_kfree_skb_any(skb); |
| 656 | return NETDEV_TX_OK; |
| 657 | } |
| 658 | real_size = get_real_size(skb, dev, &lso_header_size); |
| 659 | if (unlikely(!real_size)) |
| 660 | return NETDEV_TX_OK; |
| 661 | |
| 662 | /* Allign descriptor to TXBB size */ |
| 663 | desc_size = ALIGN(real_size, TXBB_SIZE); |
| 664 | nr_txbb = desc_size / TXBB_SIZE; |
| 665 | if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { |
| 666 | if (netif_msg_tx_err(priv)) |
| 667 | mlx4_warn(mdev, "Oversized header or SG list\n"); |
| 668 | dev_kfree_skb_any(skb); |
| 669 | return NETDEV_TX_OK; |
| 670 | } |
| 671 | |
| 672 | tx_ind = get_vlan_info(priv, skb, &vlan_tag); |
| 673 | ring = &priv->tx_ring[tx_ind]; |
| 674 | |
| 675 | /* Check available TXBBs And 2K spare for prefetch */ |
| 676 | if (unlikely(((int)(ring->prod - ring->cons)) > |
| 677 | ring->size - HEADROOM - MAX_DESC_TXBBS)) { |
| 678 | /* every full Tx ring stops queue. |
| 679 | * TODO: implement multi-queue support (per-queue stop) */ |
| 680 | netif_stop_queue(dev); |
| 681 | ring->blocked = 1; |
| 682 | priv->port_stats.queue_stopped++; |
| 683 | |
| 684 | /* Use interrupts to find out when queue opened */ |
| 685 | cq = &priv->tx_cq[tx_ind]; |
| 686 | mlx4_en_arm_cq(priv, cq); |
| 687 | return NETDEV_TX_BUSY; |
| 688 | } |
| 689 | |
| 690 | /* Now that we know what Tx ring to use */ |
| 691 | if (unlikely(!priv->port_up)) { |
| 692 | if (netif_msg_tx_err(priv)) |
| 693 | mlx4_warn(mdev, "xmit: port down!\n"); |
| 694 | dev_kfree_skb_any(skb); |
| 695 | return NETDEV_TX_OK; |
| 696 | } |
| 697 | |
| 698 | /* Track current inflight packets for performance analysis */ |
| 699 | AVG_PERF_COUNTER(priv->pstats.inflight_avg, |
| 700 | (u32) (ring->prod - ring->cons - 1)); |
| 701 | |
| 702 | /* Packet is good - grab an index and transmit it */ |
| 703 | index = ring->prod & ring->size_mask; |
| 704 | |
| 705 | /* See if we have enough space for whole descriptor TXBB for setting |
| 706 | * SW ownership on next descriptor; if not, use a bounce buffer. */ |
| 707 | if (likely(index + nr_txbb <= ring->size)) |
| 708 | tx_desc = ring->buf + index * TXBB_SIZE; |
| 709 | else |
| 710 | tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; |
| 711 | |
| 712 | /* Save skb in tx_info ring */ |
| 713 | tx_info = &ring->tx_info[index]; |
| 714 | tx_info->skb = skb; |
| 715 | tx_info->nr_txbb = nr_txbb; |
| 716 | |
| 717 | /* Prepare ctrl segement apart opcode+ownership, which depends on |
| 718 | * whether LSO is used */ |
| 719 | tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag); |
| 720 | tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN * !!vlan_tag; |
| 721 | tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f; |
| 722 | tx_desc->ctrl.srcrb_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE | |
| 723 | MLX4_WQE_CTRL_SOLICITED); |
| 724 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { |
| 725 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | |
| 726 | MLX4_WQE_CTRL_TCP_UDP_CSUM); |
| 727 | priv->port_stats.tx_chksum_offload++; |
| 728 | } |
| 729 | |
| 730 | /* Handle LSO (TSO) packets */ |
| 731 | if (lso_header_size) { |
| 732 | /* Mark opcode as LSO */ |
| 733 | op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | |
| 734 | ((ring->prod & ring->size) ? |
| 735 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); |
| 736 | |
| 737 | /* Fill in the LSO prefix */ |
| 738 | tx_desc->lso.mss_hdr_size = cpu_to_be32( |
| 739 | skb_shinfo(skb)->gso_size << 16 | lso_header_size); |
| 740 | |
| 741 | /* Copy headers; |
| 742 | * note that we already verified that it is linear */ |
| 743 | memcpy(tx_desc->lso.header, skb->data, lso_header_size); |
| 744 | data = ((void *) &tx_desc->lso + |
| 745 | ALIGN(lso_header_size + 4, DS_SIZE)); |
| 746 | |
| 747 | priv->port_stats.tso_packets++; |
| 748 | i = ((skb->len - lso_header_size) / skb_shinfo(skb)->gso_size) + |
| 749 | !!((skb->len - lso_header_size) % skb_shinfo(skb)->gso_size); |
| 750 | ring->bytes += skb->len + (i - 1) * lso_header_size; |
| 751 | ring->packets += i; |
| 752 | } else { |
| 753 | /* Normal (Non LSO) packet */ |
| 754 | op_own = cpu_to_be32(MLX4_OPCODE_SEND) | |
| 755 | ((ring->prod & ring->size) ? |
| 756 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); |
| 757 | data = &tx_desc->data; |
| 758 | ring->bytes += max(skb->len, (unsigned int) ETH_ZLEN); |
| 759 | ring->packets++; |
| 760 | |
| 761 | } |
| 762 | AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); |
| 763 | |
| 764 | |
| 765 | /* valid only for none inline segments */ |
| 766 | tx_info->data_offset = (void *) data - (void *) tx_desc; |
| 767 | |
| 768 | tx_info->linear = (lso_header_size < skb_headlen(skb) && !is_inline(skb, NULL)) ? 1 : 0; |
| 769 | data += skb_shinfo(skb)->nr_frags + tx_info->linear - 1; |
| 770 | |
| 771 | if (!is_inline(skb, &fragptr)) { |
| 772 | /* Map fragments */ |
| 773 | for (i = skb_shinfo(skb)->nr_frags - 1; i >= 0; i--) { |
| 774 | frag = &skb_shinfo(skb)->frags[i]; |
| 775 | dma = pci_map_page(mdev->dev->pdev, frag->page, frag->page_offset, |
| 776 | frag->size, PCI_DMA_TODEVICE); |
| 777 | data->addr = cpu_to_be64(dma); |
| 778 | data->lkey = cpu_to_be32(mdev->mr.key); |
| 779 | wmb(); |
| 780 | data->byte_count = cpu_to_be32(frag->size); |
| 781 | --data; |
| 782 | } |
| 783 | |
| 784 | /* Map linear part */ |
| 785 | if (tx_info->linear) { |
| 786 | dma = pci_map_single(mdev->dev->pdev, skb->data + lso_header_size, |
| 787 | skb_headlen(skb) - lso_header_size, PCI_DMA_TODEVICE); |
| 788 | data->addr = cpu_to_be64(dma); |
| 789 | data->lkey = cpu_to_be32(mdev->mr.key); |
| 790 | wmb(); |
| 791 | data->byte_count = cpu_to_be32(skb_headlen(skb) - lso_header_size); |
| 792 | } |
| 793 | } else |
| 794 | build_inline_wqe(tx_desc, skb, real_size, &vlan_tag, tx_ind, fragptr); |
| 795 | |
| 796 | ring->prod += nr_txbb; |
| 797 | |
| 798 | /* If we used a bounce buffer then copy descriptor back into place */ |
| 799 | if (tx_desc == (struct mlx4_en_tx_desc *) ring->bounce_buf) |
| 800 | tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); |
| 801 | |
| 802 | /* Run destructor before passing skb to HW */ |
| 803 | if (likely(!skb_shared(skb))) |
| 804 | skb_orphan(skb); |
| 805 | |
| 806 | /* Ensure new descirptor hits memory |
| 807 | * before setting ownership of this descriptor to HW */ |
| 808 | wmb(); |
| 809 | tx_desc->ctrl.owner_opcode = op_own; |
| 810 | |
| 811 | /* Ring doorbell! */ |
| 812 | wmb(); |
| 813 | writel(ring->doorbell_qpn, mdev->uar_map + MLX4_SEND_DOORBELL); |
| 814 | dev->trans_start = jiffies; |
| 815 | |
| 816 | /* Poll CQ here */ |
| 817 | mlx4_en_xmit_poll(priv, tx_ind); |
| 818 | |
| 819 | return 0; |
| 820 | } |
| 821 | |