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ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +02001/*
2 * Atmel SDMMC controller driver.
3 *
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/clk.h>
Ludovic Desroches4e289a72016-04-07 11:13:09 +020018#include <linux/delay.h>
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +020019#include <linux/err.h>
20#include <linux/io.h>
Ludovic Desroches44064332016-04-28 14:59:26 +020021#include <linux/kernel.h>
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +020022#include <linux/mmc/host.h>
ludovic.desroches@atmel.com64e5cd72016-03-17 14:54:34 +010023#include <linux/mmc/slot-gpio.h>
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +020024#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
ludovic.desroches@atmel.comf5f17812015-11-11 19:11:48 +010027#include <linux/pm.h>
28#include <linux/pm_runtime.h>
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +020029
30#include "sdhci-pltfm.h"
31
32#define SDMMC_CACR 0x230
33#define SDMMC_CACR_CAPWREN BIT(0)
34#define SDMMC_CACR_KEY (0x46 << 8)
35
Ludovic Desroches44064332016-04-28 14:59:26 +020036#define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */
37
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +020038struct sdhci_at91_priv {
39 struct clk *hclock;
40 struct clk *gck;
41 struct clk *mainck;
42};
43
Ludovic Desroches4e289a72016-04-07 11:13:09 +020044static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
45{
46 u16 clk;
47 unsigned long timeout;
48
49 host->mmc->actual_clock = 0;
50
51 /*
52 * There is no requirement to disable the internal clock before
53 * changing the SD clock configuration. Moreover, disabling the
54 * internal clock, changing the configuration and re-enabling the
55 * internal clock causes some bugs. It can prevent to get the internal
56 * clock stable flag ready and an unexpected switch to the base clock
57 * when using presets.
58 */
59 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
60 clk &= SDHCI_CLOCK_INT_EN;
61 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
62
63 if (clock == 0)
64 return;
65
66 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
67
68 clk |= SDHCI_CLOCK_INT_EN;
69 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
70
71 /* Wait max 20 ms */
72 timeout = 20;
73 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
74 & SDHCI_CLOCK_INT_STABLE)) {
75 if (timeout == 0) {
76 pr_err("%s: Internal clock never stabilised.\n",
77 mmc_hostname(host->mmc));
78 return;
79 }
80 timeout--;
81 mdelay(1);
82 }
83
84 clk |= SDHCI_CLOCK_CARD_EN;
85 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
86}
87
Romain Izardace22e62017-03-09 16:18:20 +010088/*
89 * In this specific implementation of the SDHCI controller, the power register
90 * needs to have a valid voltage set even when the power supply is managed by
91 * an external regulator.
92 */
93static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode,
94 unsigned short vdd)
95{
96 if (!IS_ERR(host->mmc->supply.vmmc)) {
97 struct mmc_host *mmc = host->mmc;
98
99 spin_unlock_irq(&host->lock);
100 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
101 spin_lock_irq(&host->lock);
102 }
103 sdhci_set_power_noreg(host, mode, vdd);
104}
105
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200106static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
Ludovic Desroches4e289a72016-04-07 11:13:09 +0200107 .set_clock = sdhci_at91_set_clock,
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200108 .set_bus_width = sdhci_set_bus_width,
109 .reset = sdhci_reset,
110 .set_uhs_signaling = sdhci_set_uhs_signaling,
Romain Izardace22e62017-03-09 16:18:20 +0100111 .set_power = sdhci_at91_set_power,
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200112};
113
114static const struct sdhci_pltfm_data soc_data_sama5d2 = {
115 .ops = &sdhci_at91_sama5d2_ops,
116};
117
118static const struct of_device_id sdhci_at91_dt_match[] = {
119 { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
120 {}
121};
122
ludovic.desroches@atmel.comf5f17812015-11-11 19:11:48 +0100123#ifdef CONFIG_PM
124static int sdhci_at91_runtime_suspend(struct device *dev)
125{
126 struct sdhci_host *host = dev_get_drvdata(dev);
127 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang10f1c132016-02-16 21:08:25 +0800128 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
ludovic.desroches@atmel.comf5f17812015-11-11 19:11:48 +0100129 int ret;
130
131 ret = sdhci_runtime_suspend_host(host);
132
133 clk_disable_unprepare(priv->gck);
134 clk_disable_unprepare(priv->hclock);
135 clk_disable_unprepare(priv->mainck);
136
137 return ret;
138}
139
140static int sdhci_at91_runtime_resume(struct device *dev)
141{
142 struct sdhci_host *host = dev_get_drvdata(dev);
143 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang10f1c132016-02-16 21:08:25 +0800144 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
ludovic.desroches@atmel.comf5f17812015-11-11 19:11:48 +0100145 int ret;
146
147 ret = clk_prepare_enable(priv->mainck);
148 if (ret) {
149 dev_err(dev, "can't enable mainck\n");
150 return ret;
151 }
152
153 ret = clk_prepare_enable(priv->hclock);
154 if (ret) {
155 dev_err(dev, "can't enable hclock\n");
156 return ret;
157 }
158
159 ret = clk_prepare_enable(priv->gck);
160 if (ret) {
161 dev_err(dev, "can't enable gck\n");
162 return ret;
163 }
164
165 return sdhci_runtime_resume_host(host);
166}
167#endif /* CONFIG_PM */
168
169static const struct dev_pm_ops sdhci_at91_dev_pm_ops = {
170 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
171 pm_runtime_force_resume)
172 SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend,
173 sdhci_at91_runtime_resume,
174 NULL)
175};
176
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200177static int sdhci_at91_probe(struct platform_device *pdev)
178{
179 const struct of_device_id *match;
180 const struct sdhci_pltfm_data *soc_data;
181 struct sdhci_host *host;
182 struct sdhci_pltfm_host *pltfm_host;
183 struct sdhci_at91_priv *priv;
184 unsigned int caps0, caps1;
185 unsigned int clk_base, clk_mul;
186 unsigned int gck_rate, real_gck_rate;
187 int ret;
Ludovic Desroches44064332016-04-28 14:59:26 +0200188 unsigned int preset_div;
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200189
190 match = of_match_device(sdhci_at91_dt_match, &pdev->dev);
191 if (!match)
192 return -EINVAL;
193 soc_data = match->data;
194
Jisheng Zhang10f1c132016-02-16 21:08:25 +0800195 host = sdhci_pltfm_init(pdev, soc_data, sizeof(*priv));
196 if (IS_ERR(host))
197 return PTR_ERR(host);
198
199 pltfm_host = sdhci_priv(host);
200 priv = sdhci_pltfm_priv(pltfm_host);
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200201
202 priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
203 if (IS_ERR(priv->mainck)) {
204 dev_err(&pdev->dev, "failed to get baseclk\n");
205 return PTR_ERR(priv->mainck);
206 }
207
208 priv->hclock = devm_clk_get(&pdev->dev, "hclock");
209 if (IS_ERR(priv->hclock)) {
210 dev_err(&pdev->dev, "failed to get hclock\n");
211 return PTR_ERR(priv->hclock);
212 }
213
214 priv->gck = devm_clk_get(&pdev->dev, "multclk");
215 if (IS_ERR(priv->gck)) {
216 dev_err(&pdev->dev, "failed to get multclk\n");
217 return PTR_ERR(priv->gck);
218 }
219
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200220 /*
221 * The mult clock is provided by as a generated clock by the PMC
222 * controller. In order to set the rate of gck, we have to get the
223 * base clock rate and the clock mult from capabilities.
224 */
225 clk_prepare_enable(priv->hclock);
226 caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
227 caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
228 clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
229 clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
230 gck_rate = clk_base * 1000000 * (clk_mul + 1);
231 ret = clk_set_rate(priv->gck, gck_rate);
232 if (ret < 0) {
233 dev_err(&pdev->dev, "failed to set gck");
234 goto hclock_disable_unprepare;
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200235 }
236 /*
237 * We need to check if we have the requested rate for gck because in
238 * some cases this rate could be not supported. If it happens, the rate
239 * is the closest one gck can provide. We have to update the value
240 * of clk mul.
241 */
242 real_gck_rate = clk_get_rate(priv->gck);
243 if (real_gck_rate != gck_rate) {
244 clk_mul = real_gck_rate / (clk_base * 1000000) - 1;
245 caps1 &= (~SDHCI_CLOCK_MUL_MASK);
246 caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) & SDHCI_CLOCK_MUL_MASK);
247 /* Set capabilities in r/w mode. */
248 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR);
249 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
250 /* Set capabilities in ro mode. */
251 writel(0, host->ioaddr + SDMMC_CACR);
252 dev_info(&pdev->dev, "update clk mul to %u as gck rate is %u Hz\n",
253 clk_mul, real_gck_rate);
254 }
255
Ludovic Desroches44064332016-04-28 14:59:26 +0200256 /*
257 * We have to set preset values because it depends on the clk_mul
258 * value. Moreover, SDR104 is supported in a degraded mode since the
259 * maximum sd clock value is 120 MHz instead of 208 MHz. For that
260 * reason, we need to use presets to support SDR104.
261 */
262 preset_div = DIV_ROUND_UP(real_gck_rate, 24000000) - 1;
263 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
264 host->ioaddr + SDHCI_PRESET_FOR_SDR12);
265 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
266 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
267 host->ioaddr + SDHCI_PRESET_FOR_SDR25);
268 preset_div = DIV_ROUND_UP(real_gck_rate, 100000000) - 1;
269 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
270 host->ioaddr + SDHCI_PRESET_FOR_SDR50);
271 preset_div = DIV_ROUND_UP(real_gck_rate, 120000000) - 1;
272 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
273 host->ioaddr + SDHCI_PRESET_FOR_SDR104);
274 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
275 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
276 host->ioaddr + SDHCI_PRESET_FOR_DDR50);
277
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200278 clk_prepare_enable(priv->mainck);
279 clk_prepare_enable(priv->gck);
280
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200281 ret = mmc_of_parse(host->mmc);
282 if (ret)
283 goto clocks_disable_unprepare;
284
285 sdhci_get_of_property(pdev);
286
ludovic.desroches@atmel.comf5f17812015-11-11 19:11:48 +0100287 pm_runtime_get_noresume(&pdev->dev);
288 pm_runtime_set_active(&pdev->dev);
289 pm_runtime_enable(&pdev->dev);
290 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
291 pm_runtime_use_autosuspend(&pdev->dev);
292
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200293 ret = sdhci_add_host(host);
294 if (ret)
ludovic.desroches@atmel.comf5f17812015-11-11 19:11:48 +0100295 goto pm_runtime_disable;
296
ludovic.desroches@atmel.com64e5cd72016-03-17 14:54:34 +0100297 /*
298 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes
299 * the assumption that all the clocks of the controller are disabled.
300 * It means we can't get irq from it when it is runtime suspended.
301 * For that reason, it is not planned to wake-up on a card detect irq
302 * from the controller.
303 * If we want to use runtime PM and to be able to wake-up on card
304 * insertion, we have to use a GPIO for the card detection or we can
305 * use polling. Be aware that using polling will resume/suspend the
306 * controller between each attempt.
307 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries
308 * to enable polling via device tree with broken-cd property.
309 */
Jaehoon Chung860951c2016-06-21 10:13:26 +0900310 if (mmc_card_is_removable(host->mmc) &&
Arnd Bergmann287980e2016-05-27 23:23:25 +0200311 mmc_gpio_get_cd(host->mmc) < 0) {
ludovic.desroches@atmel.com64e5cd72016-03-17 14:54:34 +0100312 host->mmc->caps |= MMC_CAP_NEEDS_POLL;
313 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
314 }
315
ludovic.desroches@atmel.comf5f17812015-11-11 19:11:48 +0100316 pm_runtime_put_autosuspend(&pdev->dev);
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200317
318 return 0;
319
ludovic.desroches@atmel.comf5f17812015-11-11 19:11:48 +0100320pm_runtime_disable:
321 pm_runtime_disable(&pdev->dev);
322 pm_runtime_set_suspended(&pdev->dev);
Jisheng Zhang2df9d582016-02-02 19:55:06 +0800323 pm_runtime_put_noidle(&pdev->dev);
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200324clocks_disable_unprepare:
325 clk_disable_unprepare(priv->gck);
326 clk_disable_unprepare(priv->mainck);
327hclock_disable_unprepare:
328 clk_disable_unprepare(priv->hclock);
329 sdhci_pltfm_free(pdev);
330 return ret;
331}
332
333static int sdhci_at91_remove(struct platform_device *pdev)
334{
335 struct sdhci_host *host = platform_get_drvdata(pdev);
336 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang10f1c132016-02-16 21:08:25 +0800337 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
338 struct clk *gck = priv->gck;
339 struct clk *hclock = priv->hclock;
340 struct clk *mainck = priv->mainck;
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200341
ludovic.desroches@atmel.comf5f17812015-11-11 19:11:48 +0100342 pm_runtime_get_sync(&pdev->dev);
343 pm_runtime_disable(&pdev->dev);
344 pm_runtime_put_noidle(&pdev->dev);
345
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200346 sdhci_pltfm_unregister(pdev);
347
Jisheng Zhang10f1c132016-02-16 21:08:25 +0800348 clk_disable_unprepare(gck);
349 clk_disable_unprepare(hclock);
350 clk_disable_unprepare(mainck);
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200351
352 return 0;
353}
354
355static struct platform_driver sdhci_at91_driver = {
356 .driver = {
357 .name = "sdhci-at91",
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200358 .of_match_table = sdhci_at91_dt_match,
ludovic.desroches@atmel.comf5f17812015-11-11 19:11:48 +0100359 .pm = &sdhci_at91_dev_pm_ops,
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200360 },
361 .probe = sdhci_at91_probe,
362 .remove = sdhci_at91_remove,
363};
364
365module_platform_driver(sdhci_at91_driver);
366
367MODULE_DESCRIPTION("SDHCI driver for at91");
368MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
369MODULE_LICENSE("GPL v2");