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gerrit-public.fairphone.software / kernel / msm-4.9 / c115739da801ea1ea20c48e2991ce6761496bef1 / . / arch / arm / boot / dts / socfpga.dtsi
blob: 936d2306e7e12e9e46fd09294b6af54e41f0ccb3 [file] [log] [blame]
Dinh Nguyen66314222012-07-18 16:07:18 -0600[diff] [blame]1/*
2 * Copyright (C) 2012 Altera <www.altera.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18/include/ "skeleton.dtsi"
19
20/ {
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 aliases {
25 ethernet0 = &gmac0;
26 serial0 = &uart0;
27 serial1 = &uart1;
Dinh Nguyenc2ad2842013-02-11 17:30:30 -0600[diff] [blame]28 timer0 = &timer0;
29 timer1 = &timer1;
30 timer2 = &timer2;
31 timer3 = &timer3;
Dinh Nguyen66314222012-07-18 16:07:18 -0600[diff] [blame]32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu@0 {
39 compatible = "arm,cortex-a9";
40 device_type = "cpu";
41 reg = <0>;
42 next-level-cache = <&L2>;
43 };
44 cpu@1 {
45 compatible = "arm,cortex-a9";
46 device_type = "cpu";
47 reg = <1>;
48 next-level-cache = <&L2>;
49 };
50 };
51
52 intc: intc@fffed000 {
53 compatible = "arm,cortex-a9-gic";
54 #interrupt-cells = <3>;
55 interrupt-controller;
56 reg = <0xfffed000 0x1000>,
57 <0xfffec100 0x100>;
58 };
59
60 soc {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 compatible = "simple-bus";
64 device_type = "soc";
65 interrupt-parent = <&intc>;
66 ranges;
67
68 amba {
69 compatible = "arm,amba-bus";
70 #address-cells = <1>;
71 #size-cells = <1>;
72 ranges;
73
74 pdma: pdma@ffe01000 {
75 compatible = "arm,pl330", "arm,primecell";
76 reg = <0xffe01000 0x1000>;
77 interrupts = <0 180 4>;
78 };
79 };
80
81 gmac0: stmmac@ff700000 {
82 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
83 reg = <0xff700000 0x2000>;
84 interrupts = <0 115 4>;
85 interrupt-names = "macirq";
86 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
87 phy-mode = "gmii";
88 };
89
90 L2: l2-cache@fffef000 {
91 compatible = "arm,pl310-cache";
92 reg = <0xfffef000 0x1000>;
93 interrupts = <0 38 0x04>;
94 cache-unified;
95 cache-level = <2>;
96 };
97
98 /* Local timer */
99 timer@fffec600 {
100 compatible = "arm,cortex-a9-twd-timer";
101 reg = <0xfffec600 0x100>;
102 interrupts = <1 13 0xf04>;
103 };
104
Dinh Nguyenc2ad2842013-02-11 17:30:30 -0600[diff] [blame]105 timer0: timer0@ffc08000 {
Dinh Nguyen66314222012-07-18 16:07:18 -0600[diff] [blame]106 compatible = "snps,dw-apb-timer-sp";
107 interrupts = <0 167 4>;
Dinh Nguyen66314222012-07-18 16:07:18 -0600[diff] [blame]108 reg = <0xffc08000 0x1000>;
109 };
110
Dinh Nguyenc2ad2842013-02-11 17:30:30 -0600[diff] [blame]111 timer1: timer1@ffc09000 {
Dinh Nguyen66314222012-07-18 16:07:18 -0600[diff] [blame]112 compatible = "snps,dw-apb-timer-sp";
113 interrupts = <0 168 4>;
Dinh Nguyen66314222012-07-18 16:07:18 -0600[diff] [blame]114 reg = <0xffc09000 0x1000>;
115 };
116
Dinh Nguyenc2ad2842013-02-11 17:30:30 -0600[diff] [blame]117 timer2: timer2@ffd00000 {
Dinh Nguyen66314222012-07-18 16:07:18 -0600[diff] [blame]118 compatible = "snps,dw-apb-timer-osc";
119 interrupts = <0 169 4>;
Dinh Nguyen66314222012-07-18 16:07:18 -0600[diff] [blame]120 reg = <0xffd00000 0x1000>;
121 };
122
Dinh Nguyenc2ad2842013-02-11 17:30:30 -0600[diff] [blame]123 timer3: timer3@ffd01000 {
Dinh Nguyen66314222012-07-18 16:07:18 -0600[diff] [blame]124 compatible = "snps,dw-apb-timer-osc";
125 interrupts = <0 170 4>;
Dinh Nguyen66314222012-07-18 16:07:18 -0600[diff] [blame]126 reg = <0xffd01000 0x1000>;
127 };
128
Dinh Nguyenc2ad2842013-02-11 17:30:30 -0600[diff] [blame]129 uart0: serial0@ffc02000 {
Dinh Nguyen66314222012-07-18 16:07:18 -0600[diff] [blame]130 compatible = "snps,dw-apb-uart";
131 reg = <0xffc02000 0x1000>;
Dinh Nguyen66314222012-07-18 16:07:18 -0600[diff] [blame]132 interrupts = <0 162 4>;
133 reg-shift = <2>;
134 reg-io-width = <4>;
135 };
136
Dinh Nguyenc2ad2842013-02-11 17:30:30 -0600[diff] [blame]137 uart1: serial1@ffc03000 {
Dinh Nguyen66314222012-07-18 16:07:18 -0600[diff] [blame]138 compatible = "snps,dw-apb-uart";
139 reg = <0xffc03000 0x1000>;
Dinh Nguyen66314222012-07-18 16:07:18 -0600[diff] [blame]140 interrupts = <0 163 4>;
141 reg-shift = <2>;
142 reg-io-width = <4>;
143 };
Dinh Nguyen9c4566a2012-10-25 10:41:39 -0600[diff] [blame]144
145 rstmgr@ffd05000 {
146 compatible = "altr,rst-mgr";
147 reg = <0xffd05000 0x1000>;
148 };
149
150 sysmgr@ffd08000 {
151 compatible = "altr,sys-mgr";
152 reg = <0xffd08000 0x4000>;
153 };
Dinh Nguyen66314222012-07-18 16:07:18 -0600[diff] [blame]154 };
155};