Micky Ching | fa590c2 | 2013-11-12 17:16:08 +0800 | [diff] [blame] | 1 | /* Driver for Realtek PCI-Express card reader |
| 2 | * Header file |
| 3 | * |
| 4 | * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License as published by the |
| 8 | * Free Software Foundation; either version 2, or (at your option) any |
| 9 | * later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, but |
| 12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along |
| 17 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 18 | * |
| 19 | * Author: |
| 20 | * Wei WANG (wei_wang@realsil.com.cn) |
| 21 | * Micky Ching (micky_ching@realsil.com.cn) |
| 22 | */ |
| 23 | |
| 24 | #ifndef __REALTEK_RTSX_XD_H |
| 25 | #define __REALTEK_RTSX_XD_H |
| 26 | |
| 27 | #define XD_DELAY_WRITE |
| 28 | |
| 29 | /* Error Codes */ |
| 30 | #define XD_NO_ERROR 0x00 |
| 31 | #define XD_NO_MEMORY 0x80 |
| 32 | #define XD_PRG_ERROR 0x40 |
| 33 | #define XD_NO_CARD 0x20 |
| 34 | #define XD_READ_FAIL 0x10 |
| 35 | #define XD_ERASE_FAIL 0x08 |
| 36 | #define XD_WRITE_FAIL 0x04 |
| 37 | #define XD_ECC_ERROR 0x02 |
| 38 | #define XD_TO_ERROR 0x01 |
| 39 | |
| 40 | /* XD Commands */ |
| 41 | #define READ1_1 0x00 |
| 42 | #define READ1_2 0x01 |
| 43 | #define READ2 0x50 |
| 44 | #define READ_ID 0x90 |
| 45 | #define RESET 0xff |
| 46 | #define PAGE_PRG_1 0x80 |
| 47 | #define PAGE_PRG_2 0x10 |
| 48 | #define BLK_ERASE_1 0x60 |
| 49 | #define BLK_ERASE_2 0xD0 |
| 50 | #define READ_STS 0x70 |
| 51 | #define READ_xD_ID 0x9A |
| 52 | #define COPY_BACK_512 0x8A |
| 53 | #define COPY_BACK_2K 0x85 |
| 54 | #define READ1_1_2 0x30 |
| 55 | #define READ1_1_3 0x35 |
| 56 | #define CHG_DAT_OUT_1 0x05 |
| 57 | #define RDM_DAT_OUT_1 0x05 |
| 58 | #define CHG_DAT_OUT_2 0xE0 |
| 59 | #define RDM_DAT_OUT_2 0xE0 |
| 60 | #define CHG_DAT_OUT_2 0xE0 |
| 61 | #define CHG_DAT_IN_1 0x85 |
| 62 | #define CACHE_PRG 0x15 |
| 63 | |
| 64 | /* Redundant Area Related */ |
| 65 | #define XD_EXTRA_SIZE 0x10 |
| 66 | #define XD_2K_EXTRA_SIZE 0x40 |
| 67 | |
| 68 | #define NOT_WRITE_PROTECTED 0x80 |
| 69 | #define READY_STATE 0x40 |
| 70 | #define PROGRAM_ERROR 0x01 |
| 71 | #define PROGRAM_ERROR_N_1 0x02 |
| 72 | #define INTERNAL_READY 0x20 |
| 73 | #define READY_FLAG 0x5F |
| 74 | |
| 75 | #define XD_8M_X8_512 0xE6 |
| 76 | #define XD_16M_X8_512 0x73 |
| 77 | #define XD_32M_X8_512 0x75 |
| 78 | #define XD_64M_X8_512 0x76 |
| 79 | #define XD_128M_X8_512 0x79 |
| 80 | #define XD_256M_X8_512 0x71 |
| 81 | #define XD_128M_X8_2048 0xF1 |
| 82 | #define XD_256M_X8_2048 0xDA |
| 83 | #define XD_512M_X8 0xDC |
| 84 | #define XD_128M_X16_2048 0xC1 |
| 85 | #define XD_4M_X8_512_1 0xE3 |
| 86 | #define XD_4M_X8_512_2 0xE5 |
| 87 | #define xD_1G_X8_512 0xD3 |
| 88 | #define xD_2G_X8_512 0xD5 |
| 89 | |
| 90 | #define XD_ID_CODE 0xB5 |
| 91 | |
| 92 | #define VENDOR_BLOCK 0xEFFF |
| 93 | #define CIS_BLOCK 0xDFFF |
| 94 | |
| 95 | #define BLK_NOT_FOUND 0xFFFFFFFF |
| 96 | |
| 97 | #define NO_NEW_BLK 0xFFFFFFFF |
| 98 | |
| 99 | #define PAGE_CORRECTABLE 0x0 |
| 100 | #define PAGE_NOTCORRECTABLE 0x1 |
| 101 | |
| 102 | #define NO_OFFSET 0x0 |
| 103 | #define WITH_OFFSET 0x1 |
| 104 | |
| 105 | #define Sect_Per_Page 4 |
| 106 | #define XD_ADDR_MODE_2C XD_ADDR_MODE_2A |
| 107 | |
| 108 | #define ZONE0_BAD_BLOCK 23 |
| 109 | #define NOT_ZONE0_BAD_BLOCK 24 |
| 110 | |
| 111 | #define XD_RW_ADDR 0x01 |
| 112 | #define XD_ERASE_ADDR 0x02 |
| 113 | |
| 114 | #define XD_PAGE_512(xd_card) \ |
| 115 | do { \ |
| 116 | (xd_card)->block_shift = 5; \ |
| 117 | (xd_card)->page_off = 0x1F; \ |
| 118 | } while (0) |
| 119 | |
| 120 | #define XD_SET_BAD_NEWBLK(xd_card) ((xd_card)->multi_flag |= 0x01) |
| 121 | #define XD_CLR_BAD_NEWBLK(xd_card) ((xd_card)->multi_flag &= ~0x01) |
| 122 | #define XD_CHK_BAD_NEWBLK(xd_card) ((xd_card)->multi_flag & 0x01) |
| 123 | |
| 124 | #define XD_SET_BAD_OLDBLK(xd_card) ((xd_card)->multi_flag |= 0x02) |
| 125 | #define XD_CLR_BAD_OLDBLK(xd_card) ((xd_card)->multi_flag &= ~0x02) |
| 126 | #define XD_CHK_BAD_OLDBLK(xd_card) ((xd_card)->multi_flag & 0x02) |
| 127 | |
| 128 | #define XD_SET_MBR_FAIL(xd_card) ((xd_card)->multi_flag |= 0x04) |
| 129 | #define XD_CLR_MBR_FAIL(xd_card) ((xd_card)->multi_flag &= ~0x04) |
| 130 | #define XD_CHK_MBR_FAIL(xd_card) ((xd_card)->multi_flag & 0x04) |
| 131 | |
| 132 | #define XD_SET_ECC_FLD_ERR(xd_card) ((xd_card)->multi_flag |= 0x08) |
| 133 | #define XD_CLR_ECC_FLD_ERR(xd_card) ((xd_card)->multi_flag &= ~0x08) |
| 134 | #define XD_CHK_ECC_FLD_ERR(xd_card) ((xd_card)->multi_flag & 0x08) |
| 135 | |
| 136 | #define XD_SET_4MB(xd_card) ((xd_card)->multi_flag |= 0x10) |
| 137 | #define XD_CLR_4MB(xd_card) ((xd_card)->multi_flag &= ~0x10) |
| 138 | #define XD_CHK_4MB(xd_card) ((xd_card)->multi_flag & 0x10) |
| 139 | |
| 140 | #define XD_SET_ECC_ERR(xd_card) ((xd_card)->multi_flag |= 0x40) |
| 141 | #define XD_CLR_ECC_ERR(xd_card) ((xd_card)->multi_flag &= ~0x40) |
| 142 | #define XD_CHK_ECC_ERR(xd_card) ((xd_card)->multi_flag & 0x40) |
| 143 | |
| 144 | #define PAGE_STATUS 0 |
| 145 | #define BLOCK_STATUS 1 |
| 146 | #define BLOCK_ADDR1_L 2 |
| 147 | #define BLOCK_ADDR1_H 3 |
| 148 | #define BLOCK_ADDR2_L 4 |
| 149 | #define BLOCK_ADDR2_H 5 |
| 150 | #define RESERVED0 6 |
| 151 | #define RESERVED1 7 |
| 152 | #define RESERVED2 8 |
| 153 | #define RESERVED3 9 |
| 154 | #define PARITY 10 |
| 155 | |
| 156 | #define CIS0_0 0 |
| 157 | #define CIS0_1 1 |
| 158 | #define CIS0_2 2 |
| 159 | #define CIS0_3 3 |
| 160 | #define CIS0_4 4 |
| 161 | #define CIS0_5 5 |
| 162 | #define CIS0_6 6 |
| 163 | #define CIS0_7 7 |
| 164 | #define CIS0_8 8 |
| 165 | #define CIS0_9 9 |
| 166 | #define CIS1_0 256 |
| 167 | #define CIS1_1 (256 + 1) |
| 168 | #define CIS1_2 (256 + 2) |
| 169 | #define CIS1_3 (256 + 3) |
| 170 | #define CIS1_4 (256 + 4) |
| 171 | #define CIS1_5 (256 + 5) |
| 172 | #define CIS1_6 (256 + 6) |
| 173 | #define CIS1_7 (256 + 7) |
| 174 | #define CIS1_8 (256 + 8) |
| 175 | #define CIS1_9 (256 + 9) |
| 176 | |
| 177 | int reset_xd_card(struct rtsx_chip *chip); |
| 178 | #ifdef XD_DELAY_WRITE |
| 179 | int xd_delay_write(struct rtsx_chip *chip); |
| 180 | #endif |
| 181 | int xd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, |
| 182 | u32 start_sector, u16 sector_cnt); |
| 183 | void xd_free_l2p_tbl(struct rtsx_chip *chip); |
| 184 | void xd_cleanup_work(struct rtsx_chip *chip); |
| 185 | int xd_power_off_card3v3(struct rtsx_chip *chip); |
| 186 | int release_xd_card(struct rtsx_chip *chip); |
| 187 | |
| 188 | #endif /* __REALTEK_RTSX_XD_H */ |