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Ben Dooksa21765a2007-02-11 18:31:01 +01001/* linux/arch/arm/plat-s3c24xx/s3c244x.c
Ben Dooks96ce2382006-06-18 23:06:41 +01002 *
3 * Copyright (c) 2004-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
Ben Dookse4d06e32007-02-16 12:12:31 +01006 * Samsung S3C2440 and S3C2442 Mobile CPU support (not S3C2443)
Ben Dooks96ce2382006-06-18 23:06:41 +01007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
Ben Dooksb6d1f542006-12-17 23:22:26 +010019#include <linux/serial_core.h>
Ben Dooks96ce2382006-06-18 23:06:41 +010020#include <linux/platform_device.h>
Kay Sievers4a858cf2011-12-21 16:01:38 -080021#include <linux/device.h>
Rafael J. Wysockibb072c32011-04-22 22:03:21 +020022#include <linux/syscore_ops.h>
Ben Dooks96ce2382006-06-18 23:06:41 +010023#include <linux/clk.h>
Russell Kingfced80c2008-09-06 12:10:45 +010024#include <linux/io.h>
Ben Dooks96ce2382006-06-18 23:06:41 +010025
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/mach/irq.h>
29
Russell Kinga09e64f2008-08-05 16:14:15 +010030#include <mach/hardware.h>
Ben Dooks96ce2382006-06-18 23:06:41 +010031#include <asm/irq.h>
32
Ben Dookse4253822008-10-21 14:06:38 +010033#include <plat/cpu-freq.h>
34
Russell Kinga09e64f2008-08-05 16:14:15 +010035#include <mach/regs-clock.h>
Ben Dooksa2b7ba92008-10-07 22:26:09 +010036#include <plat/regs-serial.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010037#include <mach/regs-gpio.h>
38#include <mach/regs-gpioj.h>
39#include <mach/regs-dsc.h>
Ben Dooks96ce2382006-06-18 23:06:41 +010040
Ben Dooksa2b7ba92008-10-07 22:26:09 +010041#include <plat/s3c2410.h>
Ben Dooks58bac7b2010-01-26 16:47:41 +090042#include <plat/s3c244x.h>
Ben Dooksd5120ae2008-10-07 23:09:51 +010043#include <plat/clock.h>
Ben Dooksa2b7ba92008-10-07 22:26:09 +010044#include <plat/devs.h>
45#include <plat/cpu.h>
46#include <plat/pm.h>
Ben Dookse24b8642008-10-21 14:06:34 +010047#include <plat/pll.h>
Atul Dahiyaef3f2dd2010-10-18 19:56:45 +090048#include <plat/nand-core.h>
Heiko Stuebnerc1ba5442012-03-01 13:23:32 +090049#include <plat/watchdog-reset.h>
Ben Dooks96ce2382006-06-18 23:06:41 +010050
51static struct map_desc s3c244x_iodesc[] __initdata = {
52 IODESC_ENT(CLKPWR),
53 IODESC_ENT(TIMER),
54 IODESC_ENT(WATCHDOG),
Ben Dooks96ce2382006-06-18 23:06:41 +010055};
56
57/* uart initialisation */
58
59void __init s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no)
60{
61 s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
62}
63
Ben Dooks74b265d2008-10-21 14:06:31 +010064void __init s3c244x_map_io(void)
Ben Dooks96ce2382006-06-18 23:06:41 +010065{
66 /* register our io-tables */
67
68 iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc));
Ben Dooks96ce2382006-06-18 23:06:41 +010069
70 /* rename any peripherals used differing from the s3c2410 */
71
Ben Dooks90239bb2008-05-21 10:24:17 +010072 s3c_device_sdi.name = "s3c2440-sdi";
Ben Dooks3e1b7762008-10-31 16:14:40 +000073 s3c_device_i2c0.name = "s3c2440-i2c";
Atul Dahiyaef3f2dd2010-10-18 19:56:45 +090074 s3c_nand_setname("s3c2440-nand");
Arnaud Patardce8877b2009-12-23 19:25:05 +000075 s3c_device_ts.name = "s3c2440-ts";
Ben Dooksb8ccca42006-06-27 22:53:03 +010076 s3c_device_usbgadget.name = "s3c2440-usbgadget";
Ben Dooks96ce2382006-06-18 23:06:41 +010077}
78
Ben Dookse4253822008-10-21 14:06:38 +010079void __init_or_cpufreq s3c244x_setup_clocks(void)
Ben Dooks96ce2382006-06-18 23:06:41 +010080{
Ben Dookse4253822008-10-21 14:06:38 +010081 struct clk *xtal_clk;
Ben Dooks96ce2382006-06-18 23:06:41 +010082 unsigned long clkdiv;
83 unsigned long camdiv;
Ben Dookse4253822008-10-21 14:06:38 +010084 unsigned long xtal;
Ben Dooks96ce2382006-06-18 23:06:41 +010085 unsigned long hclk, fclk, pclk;
86 int hdiv = 1;
87
Ben Dookse4253822008-10-21 14:06:38 +010088 xtal_clk = clk_get(NULL, "xtal");
89 xtal = clk_get_rate(xtal_clk);
90 clk_put(xtal_clk);
Ben Dooks96ce2382006-06-18 23:06:41 +010091
Ben Dookse24b8642008-10-21 14:06:34 +010092 fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
Ben Dooks96ce2382006-06-18 23:06:41 +010093
94 clkdiv = __raw_readl(S3C2410_CLKDIVN);
95 camdiv = __raw_readl(S3C2440_CAMDIVN);
96
97 /* work out clock scalings */
98
99 switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
100 case S3C2440_CLKDIVN_HDIVN_1:
101 hdiv = 1;
102 break;
103
104 case S3C2440_CLKDIVN_HDIVN_2:
105 hdiv = 2;
106 break;
107
108 case S3C2440_CLKDIVN_HDIVN_4_8:
109 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
110 break;
111
112 case S3C2440_CLKDIVN_HDIVN_3_6:
113 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
114 break;
115 }
116
117 hclk = fclk / hdiv;
Ben Dookse4253822008-10-21 14:06:38 +0100118 pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);
Ben Dooks96ce2382006-06-18 23:06:41 +0100119
120 /* print brief summary of clocks, etc */
121
122 printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
123 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
124
Ben Dookse4253822008-10-21 14:06:38 +0100125 s3c24xx_setup_clocks(fclk, hclk, pclk);
126}
127
128void __init s3c244x_init_clocks(int xtal)
129{
Ben Dooks96ce2382006-06-18 23:06:41 +0100130 /* initialise the clocks here, to allow other things like the
131 * console to use them, and to add new ones after the initialisation
132 */
133
Ben Dookse4253822008-10-21 14:06:38 +0100134 s3c24xx_register_baseclocks(xtal);
135 s3c244x_setup_clocks();
Ben Dooks99c13852006-06-22 22:18:20 +0100136 s3c2410_baseclk_add();
Ben Dooks96ce2382006-06-18 23:06:41 +0100137}
138
Kay Sievers4a858cf2011-12-21 16:01:38 -0800139/* Since the S3C2442 and S3C2440 share items, put both subsystems here */
Ben Dooks96ce2382006-06-18 23:06:41 +0100140
Kay Sievers4a858cf2011-12-21 16:01:38 -0800141struct bus_type s3c2440_subsys = {
Kay Sieversaf5ca3f2007-12-20 02:09:39 +0100142 .name = "s3c2440-core",
Kay Sievers4a858cf2011-12-21 16:01:38 -0800143 .dev_name = "s3c2440-core",
Ben Dooks96ce2382006-06-18 23:06:41 +0100144};
145
Kay Sievers4a858cf2011-12-21 16:01:38 -0800146struct bus_type s3c2442_subsys = {
Kay Sieversaf5ca3f2007-12-20 02:09:39 +0100147 .name = "s3c2442-core",
Kay Sievers4a858cf2011-12-21 16:01:38 -0800148 .dev_name = "s3c2442-core",
Ben Dooks96ce2382006-06-18 23:06:41 +0100149};
150
Kay Sievers4a858cf2011-12-21 16:01:38 -0800151/* need to register the subsystem before we actually register the device, and
Ben Dooks96ce2382006-06-18 23:06:41 +0100152 * we also need to ensure that it has been initialised before any of the
153 * drivers even try to use it (even if not on an s3c2440 based system)
154 * as a driver which may support both 2410 and 2440 may try and use it.
155*/
156
157static int __init s3c2440_core_init(void)
158{
Kay Sievers4a858cf2011-12-21 16:01:38 -0800159 return subsys_system_register(&s3c2440_subsys, NULL);
Ben Dooks96ce2382006-06-18 23:06:41 +0100160}
161
162core_initcall(s3c2440_core_init);
163
164static int __init s3c2442_core_init(void)
165{
Kay Sievers4a858cf2011-12-21 16:01:38 -0800166 return subsys_system_register(&s3c2442_subsys, NULL);
Ben Dooks96ce2382006-06-18 23:06:41 +0100167}
168
169core_initcall(s3c2442_core_init);
Rafael J. Wysockibb072c32011-04-22 22:03:21 +0200170
171
172#ifdef CONFIG_PM
173static struct sleep_save s3c244x_sleep[] = {
174 SAVE_ITEM(S3C2440_DSC0),
175 SAVE_ITEM(S3C2440_DSC1),
176 SAVE_ITEM(S3C2440_GPJDAT),
177 SAVE_ITEM(S3C2440_GPJCON),
178 SAVE_ITEM(S3C2440_GPJUP)
179};
180
181static int s3c244x_suspend(void)
182{
183 s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
184 return 0;
185}
186
187static void s3c244x_resume(void)
188{
189 s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
190}
191#else
192#define s3c244x_suspend NULL
193#define s3c244x_resume NULL
194#endif
195
196struct syscore_ops s3c244x_pm_syscore_ops = {
197 .suspend = s3c244x_suspend,
198 .resume = s3c244x_resume,
199};
Heiko Stuebnerc1ba5442012-03-01 13:23:32 +0900200
201void s3c244x_restart(char mode, const char *cmd)
202{
203 if (mode == 's')
204 soft_restart(0);
205
206 arch_wdt_reset();
207
208 /* we'll take a jump through zero as a poor second */
209 soft_restart(0);