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Aurelien Jarno1c0c13e2007-09-25 15:40:12 +02001/*
2 * Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
12 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
13 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
14 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
15 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
16 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
17 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
18 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25
26#include <linux/init.h>
27#include <linux/ssb/ssb.h>
28#include <asm/time.h>
29#include <bcm47xx.h>
30
Ralf Baechle4b550482007-10-11 23:46:08 +010031void __init plat_time_init(void)
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +020032{
Hauke Mehrtens08ccf5722011-07-23 01:20:12 +020033 unsigned long hz = 0;
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +020034
35 /*
36 * Use deterministic values for initial counter interrupt
37 * so that calibrate delay avoids encountering a counter wrap.
38 */
39 write_c0_count(0);
40 write_c0_compare(0xffff);
41
Hauke Mehrtens08ccf5722011-07-23 01:20:12 +020042 switch (bcm47xx_bus_type) {
Hauke Mehrtensa656ffc2011-07-23 01:20:13 +020043#ifdef CONFIG_BCM47XX_SSB
Hauke Mehrtens08ccf5722011-07-23 01:20:12 +020044 case BCM47XX_BUS_TYPE_SSB:
45 hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2;
46 break;
Hauke Mehrtensa656ffc2011-07-23 01:20:13 +020047#endif
Hauke Mehrtensc1d1c5d2011-07-23 01:20:14 +020048#ifdef CONFIG_BCM47XX_BCMA
49 case BCM47XX_BUS_TYPE_BCMA:
50 hz = bcma_cpu_clock(&bcm47xx_bus.bcma.bus.drv_mips) / 2;
51 break;
52#endif
Hauke Mehrtens08ccf5722011-07-23 01:20:12 +020053 }
54
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +020055 if (!hz)
56 hz = 100000000;
57
58 /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
59 mips_hpt_frequency = hz;
60}