Manjunath Hadli | f7fa454 | 2012-11-28 02:06:17 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Texas Instruments Inc |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License as |
| 6 | * published by the Free Software Foundation version 2. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program; if not, write to the Free Software |
| 15 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 16 | * |
| 17 | * Contributors: |
| 18 | * Manjunath Hadli <manjunath.hadli@ti.com> |
| 19 | * Prabhakar Lad <prabhakar.lad@ti.com> |
| 20 | */ |
| 21 | |
| 22 | #ifndef _DAVINCI_VPFE_DM365_IPIPEIF_H |
| 23 | #define _DAVINCI_VPFE_DM365_IPIPEIF_H |
| 24 | |
| 25 | #include <linux/platform_device.h> |
| 26 | |
| 27 | #include <media/davinci/vpss.h> |
| 28 | #include <media/v4l2-ctrls.h> |
| 29 | #include <media/v4l2-subdev.h> |
| 30 | |
| 31 | #include "dm365_ipipeif_user.h" |
| 32 | #include "vpfe_video.h" |
| 33 | |
| 34 | /* IPIPE base specific types */ |
| 35 | enum ipipeif_data_shift { |
| 36 | IPIPEIF_BITS15_2 = 0, |
| 37 | IPIPEIF_BITS14_1 = 1, |
| 38 | IPIPEIF_BITS13_0 = 2, |
| 39 | IPIPEIF_BITS12_0 = 3, |
| 40 | IPIPEIF_BITS11_0 = 4, |
| 41 | IPIPEIF_BITS10_0 = 5, |
| 42 | IPIPEIF_BITS9_0 = 6, |
| 43 | }; |
| 44 | |
| 45 | enum ipipeif_clkdiv { |
| 46 | IPIPEIF_DIVIDE_HALF = 0, |
| 47 | IPIPEIF_DIVIDE_THIRD = 1, |
| 48 | IPIPEIF_DIVIDE_FOURTH = 2, |
| 49 | IPIPEIF_DIVIDE_FIFTH = 3, |
| 50 | IPIPEIF_DIVIDE_SIXTH = 4, |
| 51 | IPIPEIF_DIVIDE_EIGHTH = 5, |
| 52 | IPIPEIF_DIVIDE_SIXTEENTH = 6, |
| 53 | IPIPEIF_DIVIDE_THIRTY = 7, |
| 54 | }; |
| 55 | |
| 56 | enum ipipeif_pack_mode { |
| 57 | IPIPEIF_PACK_16_BIT = 0, |
| 58 | IPIPEIF_PACK_8_BIT = 1, |
| 59 | }; |
| 60 | |
| 61 | enum ipipeif_5_1_pack_mode { |
| 62 | IPIPEIF_5_1_PACK_16_BIT = 0, |
| 63 | IPIPEIF_5_1_PACK_8_BIT = 1, |
| 64 | IPIPEIF_5_1_PACK_8_BIT_A_LAW = 2, |
| 65 | IPIPEIF_5_1_PACK_12_BIT = 3 |
| 66 | }; |
| 67 | |
| 68 | enum ipipeif_input_source { |
| 69 | IPIPEIF_CCDC = 0, |
| 70 | IPIPEIF_SDRAM_RAW = 1, |
| 71 | IPIPEIF_CCDC_DARKFM = 2, |
| 72 | IPIPEIF_SDRAM_YUV = 3, |
| 73 | }; |
| 74 | |
| 75 | enum ipipeif_ialaw { |
| 76 | IPIPEIF_ALAW_OFF = 0, |
| 77 | IPIPEIF_ALAW_ON = 1, |
| 78 | }; |
| 79 | |
| 80 | enum ipipeif_input_src1 { |
| 81 | IPIPEIF_SRC1_PARALLEL_PORT = 0, |
| 82 | IPIPEIF_SRC1_SDRAM_RAW = 1, |
| 83 | IPIPEIF_SRC1_ISIF_DARKFM = 2, |
| 84 | IPIPEIF_SRC1_SDRAM_YUV = 3, |
| 85 | }; |
| 86 | |
| 87 | enum ipipeif_dfs_dir { |
| 88 | IPIPEIF_PORT_MINUS_SDRAM = 0, |
| 89 | IPIPEIF_SDRAM_MINUS_PORT = 1, |
| 90 | }; |
| 91 | |
| 92 | enum ipipeif_chroma_phase { |
| 93 | IPIPEIF_CBCR_Y = 0, |
| 94 | IPIPEIF_Y_CBCR = 1, |
| 95 | }; |
| 96 | |
| 97 | enum ipipeif_dpcm_type { |
| 98 | IPIPEIF_DPCM_8BIT_10BIT = 0, |
| 99 | IPIPEIF_DPCM_8BIT_12BIT = 1, |
| 100 | }; |
| 101 | |
| 102 | /* data shift for IPIPE 5.1 */ |
| 103 | enum ipipeif_5_1_data_shift { |
| 104 | IPIPEIF_5_1_BITS11_0 = 0, |
| 105 | IPIPEIF_5_1_BITS10_0 = 1, |
| 106 | IPIPEIF_5_1_BITS9_0 = 2, |
| 107 | IPIPEIF_5_1_BITS8_0 = 3, |
| 108 | IPIPEIF_5_1_BITS7_0 = 4, |
| 109 | IPIPEIF_5_1_BITS15_4 = 5, |
| 110 | }; |
| 111 | |
| 112 | #define IPIPEIF_PAD_SINK 0 |
| 113 | #define IPIPEIF_PAD_SOURCE 1 |
| 114 | |
| 115 | #define IPIPEIF_NUM_PADS 2 |
| 116 | |
| 117 | enum ipipeif_input_entity { |
| 118 | IPIPEIF_INPUT_NONE = 0, |
| 119 | IPIPEIF_INPUT_ISIF = 1, |
| 120 | IPIPEIF_INPUT_MEMORY = 2, |
| 121 | }; |
| 122 | |
| 123 | enum ipipeif_output_entity { |
| 124 | IPIPEIF_OUTPUT_NONE = 0, |
| 125 | IPIPEIF_OUTPUT_IPIPE = 1, |
| 126 | IPIPEIF_OUTPUT_RESIZER = 2, |
| 127 | }; |
| 128 | |
| 129 | struct vpfe_ipipeif_device { |
| 130 | struct v4l2_subdev subdev; |
| 131 | struct media_pad pads[IPIPEIF_NUM_PADS]; |
| 132 | struct v4l2_mbus_framefmt formats[IPIPEIF_NUM_PADS]; |
| 133 | enum ipipeif_input_entity input; |
| 134 | unsigned int output; |
| 135 | struct vpfe_video_device video_in; |
| 136 | struct v4l2_ctrl_handler ctrls; |
| 137 | void *__iomem ipipeif_base_addr; |
| 138 | struct ipipeif_params config; |
| 139 | int dpcm_predictor; |
| 140 | int gain; |
| 141 | }; |
| 142 | |
| 143 | /* IPIPEIF Register Offsets from the base address */ |
| 144 | #define IPIPEIF_ENABLE 0x00 |
| 145 | #define IPIPEIF_CFG1 0x04 |
| 146 | #define IPIPEIF_PPLN 0x08 |
| 147 | #define IPIPEIF_LPFR 0x0c |
| 148 | #define IPIPEIF_HNUM 0x10 |
| 149 | #define IPIPEIF_VNUM 0x14 |
| 150 | #define IPIPEIF_ADDRU 0x18 |
| 151 | #define IPIPEIF_ADDRL 0x1c |
| 152 | #define IPIPEIF_ADOFS 0x20 |
| 153 | #define IPIPEIF_RSZ 0x24 |
| 154 | #define IPIPEIF_GAIN 0x28 |
| 155 | |
| 156 | /* Below registers are available only on IPIPE 5.1 */ |
| 157 | #define IPIPEIF_DPCM 0x2c |
| 158 | #define IPIPEIF_CFG2 0x30 |
| 159 | #define IPIPEIF_INIRSZ 0x34 |
| 160 | #define IPIPEIF_OCLIP 0x38 |
| 161 | #define IPIPEIF_DTUDF 0x3c |
| 162 | #define IPIPEIF_CLKDIV 0x40 |
| 163 | #define IPIPEIF_DPC1 0x44 |
| 164 | #define IPIPEIF_DPC2 0x48 |
| 165 | #define IPIPEIF_DFSGVL 0x4c |
| 166 | #define IPIPEIF_DFSGTH 0x50 |
| 167 | #define IPIPEIF_RSZ3A 0x54 |
| 168 | #define IPIPEIF_INIRSZ3A 0x58 |
| 169 | #define IPIPEIF_RSZ_MIN 16 |
| 170 | #define IPIPEIF_RSZ_MAX 112 |
| 171 | #define IPIPEIF_RSZ_CONST 16 |
| 172 | #define SETBIT(reg, bit) (reg = ((reg) | ((0x00000001)<<(bit)))) |
| 173 | #define RESETBIT(reg, bit) (reg = ((reg) & (~(0x00000001<<(bit))))) |
| 174 | |
| 175 | #define IPIPEIF_ADOFS_LSB_MASK 0x1ff |
| 176 | #define IPIPEIF_ADOFS_LSB_SHIFT 5 |
| 177 | #define IPIPEIF_ADOFS_MSB_MASK 0x200 |
| 178 | #define IPIPEIF_ADDRU_MASK 0x7ff |
| 179 | #define IPIPEIF_ADDRL_SHIFT 5 |
| 180 | #define IPIPEIF_ADDRL_MASK 0xffff |
| 181 | #define IPIPEIF_ADDRU_SHIFT 21 |
| 182 | #define IPIPEIF_ADDRMSB_SHIFT 31 |
| 183 | #define IPIPEIF_ADDRMSB_LEFT_SHIFT 10 |
| 184 | |
| 185 | /* CFG1 Masks and shifts */ |
| 186 | #define ONESHOT_SHIFT 0 |
| 187 | #define DECIM_SHIFT 1 |
| 188 | #define INPSRC_SHIFT 2 |
| 189 | #define CLKDIV_SHIFT 4 |
| 190 | #define AVGFILT_SHIFT 7 |
| 191 | #define PACK8IN_SHIFT 8 |
| 192 | #define IALAW_SHIFT 9 |
| 193 | #define CLKSEL_SHIFT 10 |
| 194 | #define DATASFT_SHIFT 11 |
| 195 | #define INPSRC1_SHIFT 14 |
| 196 | |
| 197 | /* DPC2 */ |
| 198 | #define IPIPEIF_DPC2_EN_SHIFT 12 |
| 199 | #define IPIPEIF_DPC2_THR_MASK 0xfff |
| 200 | /* Applicable for IPIPE 5.1 */ |
| 201 | #define IPIPEIF_DF_GAIN_EN_SHIFT 10 |
| 202 | #define IPIPEIF_DF_GAIN_MASK 0x3ff |
| 203 | #define IPIPEIF_DF_GAIN_THR_MASK 0xfff |
| 204 | /* DPCM */ |
| 205 | #define IPIPEIF_DPCM_BITS_SHIFT 2 |
| 206 | #define IPIPEIF_DPCM_PRED_SHIFT 1 |
| 207 | /* CFG2 */ |
| 208 | #define IPIPEIF_CFG2_HDPOL_SHIFT 1 |
| 209 | #define IPIPEIF_CFG2_VDPOL_SHIFT 2 |
| 210 | #define IPIPEIF_CFG2_YUV8_SHIFT 6 |
| 211 | #define IPIPEIF_CFG2_YUV16_SHIFT 3 |
| 212 | #define IPIPEIF_CFG2_YUV8P_SHIFT 7 |
| 213 | |
| 214 | /* INIRSZ */ |
| 215 | #define IPIPEIF_INIRSZ_ALNSYNC_SHIFT 13 |
| 216 | #define IPIPEIF_INIRSZ_MASK 0x1fff |
| 217 | |
| 218 | /* CLKDIV */ |
| 219 | #define IPIPEIF_CLKDIV_M_SHIFT 8 |
| 220 | |
| 221 | void vpfe_ipipeif_enable(struct vpfe_device *vpfe_dev); |
| 222 | void vpfe_ipipeif_ss_buffer_isr(struct vpfe_ipipeif_device *ipipeif); |
| 223 | int vpfe_ipipeif_decimation_enabled(struct vpfe_device *vpfe_dev); |
| 224 | int vpfe_ipipeif_get_rsz(struct vpfe_device *vpfe_dev); |
| 225 | void vpfe_ipipeif_cleanup(struct vpfe_ipipeif_device *ipipeif, |
| 226 | struct platform_device *pdev); |
| 227 | int vpfe_ipipeif_init(struct vpfe_ipipeif_device *ipipeif, |
| 228 | struct platform_device *pdev); |
| 229 | int vpfe_ipipeif_register_entities(struct vpfe_ipipeif_device *ipipeif, |
| 230 | struct v4l2_device *vdev); |
| 231 | void vpfe_ipipeif_unregister_entities(struct vpfe_ipipeif_device *ipipeif); |
| 232 | |
| 233 | #endif /* _DAVINCI_VPFE_DM365_IPIPEIF_H */ |