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Richard Cochrand339b132012-03-16 10:55:32 +00001/*
2 * PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
3 *
4 * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20#include <linux/module.h>
21#include <linux/device.h>
22#include <linux/pci.h>
23
24#include "igb.h"
25
26#define INCVALUE_MASK 0x7fffffff
27#define ISGN 0x80000000
28
29/*
Richard Cochran7ebae812012-03-16 10:55:37 +000030 * The 82580 timesync updates the system timer every 8ns by 8ns,
31 * and this update value cannot be reprogrammed.
32 *
Richard Cochrand339b132012-03-16 10:55:32 +000033 * Neither the 82576 nor the 82580 offer registers wide enough to hold
34 * nanoseconds time values for very long. For the 82580, SYSTIM always
35 * counts nanoseconds, but the upper 24 bits are not availible. The
36 * frequency is adjusted by changing the 32 bit fractional nanoseconds
37 * register, TIMINCA.
38 *
39 * For the 82576, the SYSTIM register time unit is affect by the
40 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
41 * field are needed to provide the nominal 16 nanosecond period,
42 * leaving 19 bits for fractional nanoseconds.
43 *
Richard Cochran7ebae812012-03-16 10:55:37 +000044 * We scale the NIC clock cycle by a large factor so that relatively
45 * small clock corrections can be added or subtracted at each clock
46 * tick. The drawbacks of a large factor are a) that the clock
47 * register overflows more quickly (not such a big deal) and b) that
48 * the increment per tick has to fit into 24 bits. As a result we
49 * need to use a shift of 19 so we can fit a value of 16 into the
50 * TIMINCA register.
51 *
Richard Cochrand339b132012-03-16 10:55:32 +000052 *
53 * SYSTIMH SYSTIML
54 * +--------------+ +---+---+------+
55 * 82576 | 32 | | 8 | 5 | 19 |
56 * +--------------+ +---+---+------+
57 * \________ 45 bits _______/ fract
58 *
59 * +----------+---+ +--------------+
60 * 82580 | 24 | 8 | | 32 |
61 * +----------+---+ +--------------+
62 * reserved \______ 40 bits _____/
63 *
64 *
65 * The 45 bit 82576 SYSTIM overflows every
66 * 2^45 * 10^-9 / 3600 = 9.77 hours.
67 *
68 * The 40 bit 82580 SYSTIM overflows every
69 * 2^40 * 10^-9 / 60 = 18.3 minutes.
70 */
71
72#define IGB_OVERFLOW_PERIOD (HZ * 60 * 9)
73#define INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
74#define INCVALUE_82576_MASK ((1 << E1000_TIMINCA_16NS_SHIFT) - 1)
75#define INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
76#define IGB_NBITS_82580 40
77
78/*
79 * SYSTIM read access for the 82576
80 */
81
82static cycle_t igb_82576_systim_read(const struct cyclecounter *cc)
83{
84 u64 val;
85 u32 lo, hi;
86 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
87 struct e1000_hw *hw = &igb->hw;
88
89 lo = rd32(E1000_SYSTIML);
90 hi = rd32(E1000_SYSTIMH);
91
92 val = ((u64) hi) << 32;
93 val |= lo;
94
95 return val;
96}
97
98/*
99 * SYSTIM read access for the 82580
100 */
101
102static cycle_t igb_82580_systim_read(const struct cyclecounter *cc)
103{
104 u64 val;
105 u32 lo, hi, jk;
106 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
107 struct e1000_hw *hw = &igb->hw;
108
Richard Cochran7ebae812012-03-16 10:55:37 +0000109 /*
110 * The timestamp latches on lowest register read. For the 82580
111 * the lowest register is SYSTIMR instead of SYSTIML. However we only
112 * need to provide nanosecond resolution, so we just ignore it.
113 */
Richard Cochrand339b132012-03-16 10:55:32 +0000114 jk = rd32(E1000_SYSTIMR);
115 lo = rd32(E1000_SYSTIML);
116 hi = rd32(E1000_SYSTIMH);
117
118 val = ((u64) hi) << 32;
119 val |= lo;
120
121 return val;
122}
123
124/*
125 * PTP clock operations
126 */
127
128static int ptp_82576_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
129{
130 u64 rate;
131 u32 incvalue;
132 int neg_adj = 0;
133 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, caps);
134 struct e1000_hw *hw = &igb->hw;
135
136 if (ppb < 0) {
137 neg_adj = 1;
138 ppb = -ppb;
139 }
140 rate = ppb;
141 rate <<= 14;
142 rate = div_u64(rate, 1953125);
143
144 incvalue = 16 << IGB_82576_TSYNC_SHIFT;
145
146 if (neg_adj)
147 incvalue -= rate;
148 else
149 incvalue += rate;
150
151 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
152
153 return 0;
154}
155
156static int ptp_82580_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
157{
158 u64 rate;
159 u32 inca;
160 int neg_adj = 0;
161 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, caps);
162 struct e1000_hw *hw = &igb->hw;
163
164 if (ppb < 0) {
165 neg_adj = 1;
166 ppb = -ppb;
167 }
168 rate = ppb;
169 rate <<= 26;
170 rate = div_u64(rate, 1953125);
171
172 inca = rate & INCVALUE_MASK;
173 if (neg_adj)
174 inca |= ISGN;
175
176 wr32(E1000_TIMINCA, inca);
177
178 return 0;
179}
180
181static int igb_adjtime(struct ptp_clock_info *ptp, s64 delta)
182{
183 s64 now;
184 unsigned long flags;
185 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, caps);
186
187 spin_lock_irqsave(&igb->tmreg_lock, flags);
188
189 now = timecounter_read(&igb->tc);
190 now += delta;
191 timecounter_init(&igb->tc, &igb->cc, now);
192
193 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
194
195 return 0;
196}
197
198static int igb_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
199{
200 u64 ns;
201 u32 remainder;
202 unsigned long flags;
203 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, caps);
204
205 spin_lock_irqsave(&igb->tmreg_lock, flags);
206
207 ns = timecounter_read(&igb->tc);
208
209 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
210
211 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
212 ts->tv_nsec = remainder;
213
214 return 0;
215}
216
217static int igb_settime(struct ptp_clock_info *ptp, const struct timespec *ts)
218{
219 u64 ns;
220 unsigned long flags;
221 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, caps);
222
223 ns = ts->tv_sec * 1000000000ULL;
224 ns += ts->tv_nsec;
225
226 spin_lock_irqsave(&igb->tmreg_lock, flags);
227
228 timecounter_init(&igb->tc, &igb->cc, ns);
229
230 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
231
232 return 0;
233}
234
235static int ptp_82576_enable(struct ptp_clock_info *ptp,
236 struct ptp_clock_request *rq, int on)
237{
238 return -EOPNOTSUPP;
239}
240
241static int ptp_82580_enable(struct ptp_clock_info *ptp,
242 struct ptp_clock_request *rq, int on)
243{
244 return -EOPNOTSUPP;
245}
246
247static void igb_overflow_check(struct work_struct *work)
248{
249 struct timespec ts;
250 struct igb_adapter *igb =
251 container_of(work, struct igb_adapter, overflow_work.work);
252
253 igb_gettime(&igb->caps, &ts);
254
255 pr_debug("igb overflow check at %ld.%09lu\n", ts.tv_sec, ts.tv_nsec);
256
257 schedule_delayed_work(&igb->overflow_work, IGB_OVERFLOW_PERIOD);
258}
259
260void igb_ptp_init(struct igb_adapter *adapter)
261{
262 struct e1000_hw *hw = &adapter->hw;
263
264 switch (hw->mac.type) {
Carolyn Wybornyf96a8a02012-04-06 23:25:19 +0000265 case e1000_i210:
266 case e1000_i211:
Richard Cochrand339b132012-03-16 10:55:32 +0000267 case e1000_i350:
268 case e1000_82580:
269 adapter->caps.owner = THIS_MODULE;
270 strcpy(adapter->caps.name, "igb-82580");
271 adapter->caps.max_adj = 62499999;
272 adapter->caps.n_ext_ts = 0;
273 adapter->caps.pps = 0;
274 adapter->caps.adjfreq = ptp_82580_adjfreq;
275 adapter->caps.adjtime = igb_adjtime;
276 adapter->caps.gettime = igb_gettime;
277 adapter->caps.settime = igb_settime;
278 adapter->caps.enable = ptp_82580_enable;
279 adapter->cc.read = igb_82580_systim_read;
280 adapter->cc.mask = CLOCKSOURCE_MASK(IGB_NBITS_82580);
281 adapter->cc.mult = 1;
282 adapter->cc.shift = 0;
283 /* Enable the timer functions by clearing bit 31. */
284 wr32(E1000_TSAUXC, 0x0);
285 break;
286
287 case e1000_82576:
288 adapter->caps.owner = THIS_MODULE;
289 strcpy(adapter->caps.name, "igb-82576");
290 adapter->caps.max_adj = 1000000000;
291 adapter->caps.n_ext_ts = 0;
292 adapter->caps.pps = 0;
293 adapter->caps.adjfreq = ptp_82576_adjfreq;
294 adapter->caps.adjtime = igb_adjtime;
295 adapter->caps.gettime = igb_gettime;
296 adapter->caps.settime = igb_settime;
297 adapter->caps.enable = ptp_82576_enable;
298 adapter->cc.read = igb_82576_systim_read;
299 adapter->cc.mask = CLOCKSOURCE_MASK(64);
300 adapter->cc.mult = 1;
301 adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
302 /* Dial the nominal frequency. */
303 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
304 break;
305
306 default:
307 adapter->ptp_clock = NULL;
308 return;
309 }
310
311 wrfl();
312
313 timecounter_init(&adapter->tc, &adapter->cc,
314 ktime_to_ns(ktime_get_real()));
315
316 INIT_DELAYED_WORK(&adapter->overflow_work, igb_overflow_check);
317
318 spin_lock_init(&adapter->tmreg_lock);
319
320 schedule_delayed_work(&adapter->overflow_work, IGB_OVERFLOW_PERIOD);
321
322 adapter->ptp_clock = ptp_clock_register(&adapter->caps);
323 if (IS_ERR(adapter->ptp_clock)) {
324 adapter->ptp_clock = NULL;
325 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
326 } else
327 dev_info(&adapter->pdev->dev, "added PHC on %s\n",
328 adapter->netdev->name);
329}
330
331void igb_ptp_remove(struct igb_adapter *adapter)
332{
333 cancel_delayed_work_sync(&adapter->overflow_work);
334
335 if (adapter->ptp_clock) {
336 ptp_clock_unregister(adapter->ptp_clock);
337 dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
338 adapter->netdev->name);
339 }
340}
Richard Cochran7ebae812012-03-16 10:55:37 +0000341
342/**
343 * igb_systim_to_hwtstamp - convert system time value to hw timestamp
344 * @adapter: board private structure
345 * @hwtstamps: timestamp structure to update
346 * @systim: unsigned 64bit system time value.
347 *
348 * We need to convert the system time value stored in the RX/TXSTMP registers
349 * into a hwtstamp which can be used by the upper level timestamping functions.
350 *
351 * The 'tmreg_lock' spinlock is used to protect the consistency of the
352 * system time value. This is needed because reading the 64 bit time
353 * value involves reading two (or three) 32 bit registers. The first
354 * read latches the value. Ditto for writing.
355 *
356 * In addition, here have extended the system time with an overflow
357 * counter in software.
358 **/
359void igb_systim_to_hwtstamp(struct igb_adapter *adapter,
360 struct skb_shared_hwtstamps *hwtstamps,
361 u64 systim)
362{
363 u64 ns;
364 unsigned long flags;
365
366 switch (adapter->hw.mac.type) {
Carolyn Wybornyf96a8a02012-04-06 23:25:19 +0000367 case e1000_i210:
368 case e1000_i211:
Richard Cochran7ebae812012-03-16 10:55:37 +0000369 case e1000_i350:
370 case e1000_82580:
371 case e1000_82576:
372 break;
373 default:
374 return;
375 }
376
377 spin_lock_irqsave(&adapter->tmreg_lock, flags);
378
379 ns = timecounter_cyc2time(&adapter->tc, systim);
380
381 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
382
383 memset(hwtstamps, 0, sizeof(*hwtstamps));
384 hwtstamps->hwtstamp = ns_to_ktime(ns);
385}