blob: 05bb51676e82e5649d3d37b0c1f0ab4735417219 [file] [log] [blame]
Thomas Bogendoerferc066a322006-12-28 18:22:32 +01001/*
2 * PCI Tower specific code
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
9 */
10
11#include <linux/init.h>
12#include <linux/interrupt.h>
David Howellsca4d3e672010-10-07 14:08:54 +010013#include <linux/irq.h>
Thomas Bogendoerferc066a322006-12-28 18:22:32 +010014#include <linux/pci.h>
15#include <linux/serial_8250.h>
16
Thomas Bogendoerferc066a322006-12-28 18:22:32 +010017#include <asm/sni.h>
18#include <asm/time.h>
19#include <asm/irq_cpu.h>
20
21
22#define PORT(_base,_irq) \
23 { \
24 .iobase = _base, \
25 .irq = _irq, \
26 .uartclk = 1843200, \
27 .iotype = UPIO_PORT, \
28 .flags = UPF_BOOT_AUTOCONF, \
29 }
30
31static struct plat_serial8250_port pcit_data[] = {
32 PORT(0x3f8, 0),
33 PORT(0x2f8, 3),
34 { },
35};
36
37static struct platform_device pcit_serial8250_device = {
38 .name = "serial8250",
39 .id = PLAT8250_DEV_PLATFORM,
40 .dev = {
41 .platform_data = pcit_data,
42 },
43};
44
45static struct plat_serial8250_port pcit_cplus_data[] = {
Thomas Bogendoerferbea77172007-04-08 13:34:57 +020046 PORT(0x3f8, 0),
Thomas Bogendoerferc066a322006-12-28 18:22:32 +010047 PORT(0x2f8, 3),
48 PORT(0x3e8, 4),
49 PORT(0x2e8, 3),
50 { },
51};
52
53static struct platform_device pcit_cplus_serial8250_device = {
54 .name = "serial8250",
55 .id = PLAT8250_DEV_PLATFORM,
56 .dev = {
57 .platform_data = pcit_cplus_data,
58 },
59};
60
Thomas Bogendoerfer06cf5582007-06-20 23:36:47 +020061static struct resource pcit_cmos_rsrc[] = {
Ralf Baechle70342282013-01-22 12:59:30 +010062 {
63 .start = 0x70,
64 .end = 0x71,
65 .flags = IORESOURCE_IO
66 },
67 {
68 .start = 8,
69 .end = 8,
70 .flags = IORESOURCE_IRQ
71 }
Thomas Bogendoerfer06cf5582007-06-20 23:36:47 +020072};
73
74static struct platform_device pcit_cmos_device = {
Ralf Baechle70342282013-01-22 12:59:30 +010075 .name = "rtc_cmos",
76 .num_resources = ARRAY_SIZE(pcit_cmos_rsrc),
77 .resource = pcit_cmos_rsrc
Thomas Bogendoerfer06cf5582007-06-20 23:36:47 +020078};
79
Ralf Baechle19388fb2008-01-29 10:14:57 +000080static struct platform_device pcit_pcspeaker_pdev = {
81 .name = "pcspkr",
82 .id = -1,
83};
84
Thomas Bogendoerferc066a322006-12-28 18:22:32 +010085static struct resource sni_io_resource = {
Thomas Bogendoerferbea77172007-04-08 13:34:57 +020086 .start = 0x00000000UL,
Thomas Bogendoerferc066a322006-12-28 18:22:32 +010087 .end = 0x03bfffffUL,
Thomas Bogendoerferbea77172007-04-08 13:34:57 +020088 .name = "PCIT IO",
Thomas Bogendoerferc066a322006-12-28 18:22:32 +010089 .flags = IORESOURCE_IO,
90};
91
92static struct resource pcit_io_resources[] = {
93 {
94 .start = 0x00,
95 .end = 0x1f,
96 .name = "dma1",
97 .flags = IORESOURCE_BUSY
98 }, {
99 .start = 0x40,
100 .end = 0x5f,
101 .name = "timer",
102 .flags = IORESOURCE_BUSY
103 }, {
104 .start = 0x60,
105 .end = 0x6f,
106 .name = "keyboard",
107 .flags = IORESOURCE_BUSY
108 }, {
109 .start = 0x80,
110 .end = 0x8f,
111 .name = "dma page reg",
112 .flags = IORESOURCE_BUSY
113 }, {
114 .start = 0xc0,
115 .end = 0xdf,
116 .name = "dma2",
117 .flags = IORESOURCE_BUSY
118 }, {
Thomas Bogendoerferbea77172007-04-08 13:34:57 +0200119 .start = 0xcf8,
120 .end = 0xcfb,
121 .name = "PCI config addr",
122 .flags = IORESOURCE_BUSY
123 }, {
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100124 .start = 0xcfc,
125 .end = 0xcff,
126 .name = "PCI config data",
127 .flags = IORESOURCE_BUSY
128 }
129};
130
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100131static void __init sni_pcit_resource_init(void)
132{
133 int i;
134
135 /* request I/O space for devices used on all i[345]86 PCs */
136 for (i = 0; i < ARRAY_SIZE(pcit_io_resources); i++)
Thomas Bogendoerferbea77172007-04-08 13:34:57 +0200137 request_resource(&sni_io_resource, pcit_io_resources + i);
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100138}
139
140
141extern struct pci_ops sni_pcit_ops;
142
Ralf Baechle6a720152013-06-25 17:10:28 +0200143#ifdef CONFIG_PCI
144static struct resource sni_mem_resource = {
145 .start = 0x18000000UL,
146 .end = 0x1fbfffffUL,
147 .name = "PCIT PCI MEM",
148 .flags = IORESOURCE_MEM
149};
150
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100151static struct pci_controller sni_pcit_controller = {
152 .pci_ops = &sni_pcit_ops,
153 .mem_resource = &sni_mem_resource,
Thomas Bogendoerferbea77172007-04-08 13:34:57 +0200154 .mem_offset = 0x00000000UL,
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100155 .io_resource = &sni_io_resource,
Thomas Bogendoerferbea77172007-04-08 13:34:57 +0200156 .io_offset = 0x00000000UL,
Ralf Baechle70342282013-01-22 12:59:30 +0100157 .io_map_base = SNI_PORT_BASE
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100158};
Ralf Baechle6a720152013-06-25 17:10:28 +0200159#endif /* CONFIG_PCI */
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100160
Thomas Gleixner0b888c72011-03-23 21:09:15 +0000161static void enable_pcit_irq(struct irq_data *d)
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100162{
Thomas Gleixner0b888c72011-03-23 21:09:15 +0000163 u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24);
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100164
165 *(volatile u32 *)SNI_PCIT_INT_REG |= mask;
166}
167
Thomas Gleixner0b888c72011-03-23 21:09:15 +0000168void disable_pcit_irq(struct irq_data *d)
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100169{
Thomas Gleixner0b888c72011-03-23 21:09:15 +0000170 u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24);
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100171
172 *(volatile u32 *)SNI_PCIT_INT_REG &= ~mask;
173}
174
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100175static struct irq_chip pcit_irq_type = {
Thomas Gleixner8922f792009-11-17 22:51:03 +0000176 .name = "PCIT",
Thomas Gleixner0b888c72011-03-23 21:09:15 +0000177 .irq_mask = disable_pcit_irq,
178 .irq_unmask = enable_pcit_irq,
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100179};
180
181static void pcit_hwint1(void)
182{
183 u32 pending = *(volatile u32 *)SNI_PCIT_INT_REG;
184 int irq;
185
186 clear_c0_status(IE_IRQ1);
187 irq = ffs((pending >> 16) & 0x7f);
188
189 if (likely(irq > 0))
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100190 do_IRQ(irq + SNI_PCIT_INT_START - 1);
191 set_c0_status(IE_IRQ1);
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100192}
193
194static void pcit_hwint0(void)
195{
196 u32 pending = *(volatile u32 *)SNI_PCIT_INT_REG;
197 int irq;
198
199 clear_c0_status(IE_IRQ0);
Thomas Bogendoerferbea77172007-04-08 13:34:57 +0200200 irq = ffs((pending >> 16) & 0x3f);
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100201
202 if (likely(irq > 0))
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100203 do_IRQ(irq + SNI_PCIT_INT_START - 1);
204 set_c0_status(IE_IRQ0);
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100205}
206
207static void sni_pcit_hwint(void)
208{
Thiemo Seufer119537c2007-03-19 00:13:37 +0000209 u32 pending = read_c0_cause() & read_c0_status();
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100210
211 if (pending & C_IRQ1)
212 pcit_hwint1();
213 else if (pending & C_IRQ2)
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100214 do_IRQ(MIPS_CPU_IRQ_BASE + 4);
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100215 else if (pending & C_IRQ3)
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100216 do_IRQ(MIPS_CPU_IRQ_BASE + 5);
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100217 else if (pending & C_IRQ5)
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100218 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100219}
220
221static void sni_pcit_hwint_cplus(void)
222{
Thiemo Seufer119537c2007-03-19 00:13:37 +0000223 u32 pending = read_c0_cause() & read_c0_status();
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100224
225 if (pending & C_IRQ0)
226 pcit_hwint0();
Thomas Bogendoerferbea77172007-04-08 13:34:57 +0200227 else if (pending & C_IRQ1)
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100228 do_IRQ(MIPS_CPU_IRQ_BASE + 3);
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100229 else if (pending & C_IRQ2)
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100230 do_IRQ(MIPS_CPU_IRQ_BASE + 4);
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100231 else if (pending & C_IRQ3)
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100232 do_IRQ(MIPS_CPU_IRQ_BASE + 5);
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100233 else if (pending & C_IRQ5)
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100234 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100235}
236
237void __init sni_pcit_irq_init(void)
238{
239 int i;
240
241 mips_cpu_irq_init();
242 for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
Thomas Gleixnere4ec7982011-03-27 15:19:28 +0200243 irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100244 *(volatile u32 *)SNI_PCIT_INT_REG = 0;
245 sni_hwint = sni_pcit_hwint;
246 change_c0_status(ST0_IM, IE_IRQ1);
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100247 setup_irq(SNI_PCIT_INT_START + 6, &sni_isa_irq);
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100248}
249
250void __init sni_pcit_cplus_irq_init(void)
251{
252 int i;
253
254 mips_cpu_irq_init();
255 for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
Thomas Gleixnere4ec7982011-03-27 15:19:28 +0200256 irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
Thomas Bogendoerferbea77172007-04-08 13:34:57 +0200257 *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000;
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100258 sni_hwint = sni_pcit_hwint_cplus;
259 change_c0_status(ST0_IM, IE_IRQ0);
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100260 setup_irq(MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq);
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100261}
262
Thomas Bogendoerfer06cf5582007-06-20 23:36:47 +0200263void __init sni_pcit_init(void)
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100264{
Thomas Bogendoerferbea77172007-04-08 13:34:57 +0200265 ioport_resource.end = sni_io_resource.end;
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100266#ifdef CONFIG_PCI
Thomas Bogendoerferbea77172007-04-08 13:34:57 +0200267 PCIBIOS_MIN_IO = 0x9000;
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100268 register_pci_controller(&sni_pcit_controller);
269#endif
Thomas Bogendoerferbea77172007-04-08 13:34:57 +0200270 sni_pcit_resource_init();
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100271}
272
273static int __init snirm_pcit_setup_devinit(void)
274{
275 switch (sni_brd_type) {
276 case SNI_BRD_PCI_TOWER:
Ralf Baechle70342282013-01-22 12:59:30 +0100277 platform_device_register(&pcit_serial8250_device);
278 platform_device_register(&pcit_cmos_device);
Ralf Baechle19388fb2008-01-29 10:14:57 +0000279 platform_device_register(&pcit_pcspeaker_pdev);
Ralf Baechle70342282013-01-22 12:59:30 +0100280 break;
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100281
282 case SNI_BRD_PCI_TOWER_CPLUS:
Ralf Baechle70342282013-01-22 12:59:30 +0100283 platform_device_register(&pcit_cplus_serial8250_device);
284 platform_device_register(&pcit_cmos_device);
Ralf Baechle19388fb2008-01-29 10:14:57 +0000285 platform_device_register(&pcit_pcspeaker_pdev);
Ralf Baechle70342282013-01-22 12:59:30 +0100286 break;
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100287 }
288 return 0;
289}
290
291device_initcall(snirm_pcit_setup_devinit);