| James Hogan | 5633004 | 2012-10-09 10:54:32 +0100 | [diff] [blame] | 1 | choice |
| 2 | prompt "SoC Type" |
| 3 | default META21_FPGA |
| 4 | |
| 5 | config META12_FPGA |
| 6 | bool "Meta 1.2 FPGA" |
| 7 | select METAG_META12 |
| 8 | help |
| 9 | This is a Meta 1.2 FPGA bitstream, just a bare CPU. |
| 10 | |
| 11 | config META21_FPGA |
| 12 | bool "Meta 2.1 FPGA" |
| 13 | select METAG_META21 |
| 14 | help |
| 15 | This is a Meta 2.1 FPGA bitstream, just a bare CPU. |
| 16 | |
| James Hogan | c24d297 | 2012-12-05 16:32:10 +0000 | [diff] [blame^] | 17 | config SOC_TZ1090 |
| 18 | bool "Toumaz Xenif TZ1090 SoC (Comet)" |
| 19 | select METAG_LNKGET_AROUND_CACHE |
| 20 | select METAG_META21 |
| 21 | select METAG_SMP_WRITE_REORDERING |
| 22 | help |
| 23 | This is a Toumaz Technology Xenif TZ1090 (A.K.A. Comet) SoC containing |
| 24 | a 2-threaded HTP. |
| 25 | |
| James Hogan | 5633004 | 2012-10-09 10:54:32 +0100 | [diff] [blame] | 26 | endchoice |
| 27 | |
| 28 | menu "SoC configuration" |
| 29 | |
| 30 | if METAG_META21 |
| 31 | |
| 32 | # Meta 2.x specific options |
| 33 | |
| 34 | config METAG_META21_MMU |
| 35 | bool "Meta 2.x MMU mode" |
| 36 | default y |
| 37 | help |
| 38 | Use the Meta 2.x MMU in extended mode. |
| 39 | |
| 40 | config METAG_UNALIGNED |
| 41 | bool "Meta 2.x unaligned access checking" |
| 42 | default y |
| 43 | help |
| 44 | All memory accesses will be checked for alignment and an exception |
| 45 | raised on unaligned accesses. This feature does cost performance |
| 46 | but without it there will be no notification of this type of error. |
| 47 | |
| 48 | config METAG_USER_TCM |
| 49 | bool "Meta on-chip memory support for userland" |
| 50 | select GENERIC_ALLOCATOR |
| 51 | default y |
| 52 | help |
| 53 | Allow the on-chip memories of Meta SoCs to be used by user |
| 54 | applications. |
| 55 | |
| 56 | endif |
| 57 | |
| 58 | config METAG_HALT_ON_PANIC |
| 59 | bool "Halt the core on panic" |
| 60 | help |
| 61 | Halt the core when a panic occurs. This is useful when running |
| 62 | pre-production silicon or in an FPGA environment. |
| 63 | |
| 64 | endmenu |