Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Christian König. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Christian König |
| 25 | */ |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 26 | #include <linux/hdmi.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 27 | #include <drm/drmP.h> |
| 28 | #include <drm/radeon_drm.h> |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 29 | #include "radeon.h" |
Daniel Vetter | 3574dda | 2011-02-18 17:59:19 +0100 | [diff] [blame] | 30 | #include "radeon_asic.h" |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 31 | #include "r600d.h" |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 32 | #include "atom.h" |
| 33 | |
| 34 | /* |
| 35 | * HDMI color format |
| 36 | */ |
| 37 | enum r600_hdmi_color_format { |
| 38 | RGB = 0, |
| 39 | YCC_422 = 1, |
| 40 | YCC_444 = 2 |
| 41 | }; |
| 42 | |
| 43 | /* |
| 44 | * IEC60958 status bits |
| 45 | */ |
| 46 | enum r600_hdmi_iec_status_bits { |
| 47 | AUDIO_STATUS_DIG_ENABLE = 0x01, |
Rafał Miłecki | 3fe373d | 2010-03-06 13:03:38 +0000 | [diff] [blame] | 48 | AUDIO_STATUS_V = 0x02, |
| 49 | AUDIO_STATUS_VCFG = 0x04, |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 50 | AUDIO_STATUS_EMPHASIS = 0x08, |
| 51 | AUDIO_STATUS_COPYRIGHT = 0x10, |
| 52 | AUDIO_STATUS_NONAUDIO = 0x20, |
| 53 | AUDIO_STATUS_PROFESSIONAL = 0x40, |
Rafał Miłecki | 3fe373d | 2010-03-06 13:03:38 +0000 | [diff] [blame] | 54 | AUDIO_STATUS_LEVEL = 0x80 |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 55 | }; |
| 56 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 57 | static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = { |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 58 | /* 32kHz 44.1kHz 48kHz */ |
| 59 | /* Clock N CTS N CTS N CTS */ |
| 60 | { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ |
| 61 | { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ |
| 62 | { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ |
| 63 | { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ |
| 64 | { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ |
| 65 | { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ |
| 66 | { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ |
| 67 | { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ |
| 68 | { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ |
| 69 | { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ |
| 70 | { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */ |
| 71 | }; |
| 72 | |
| 73 | /* |
| 74 | * calculate CTS value if it's not found in the table |
| 75 | */ |
Rafał Miłecki | 1b688d08 | 2012-04-30 15:44:54 +0200 | [diff] [blame] | 76 | static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 77 | { |
| 78 | if (*CTS == 0) |
Rafał Miłecki | 3fe373d | 2010-03-06 13:03:38 +0000 | [diff] [blame] | 79 | *CTS = clock * N / (128 * freq) * 1000; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 80 | DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n", |
| 81 | N, *CTS, freq); |
| 82 | } |
| 83 | |
Rafał Miłecki | 1b688d08 | 2012-04-30 15:44:54 +0200 | [diff] [blame] | 84 | struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock) |
| 85 | { |
| 86 | struct radeon_hdmi_acr res; |
| 87 | u8 i; |
| 88 | |
| 89 | for (i = 0; r600_hdmi_predefined_acr[i].clock != clock && |
| 90 | r600_hdmi_predefined_acr[i].clock != 0; i++) |
| 91 | ; |
| 92 | res = r600_hdmi_predefined_acr[i]; |
| 93 | |
| 94 | /* In case some CTS are missing */ |
| 95 | r600_hdmi_calc_cts(clock, &res.cts_32khz, res.n_32khz, 32000); |
| 96 | r600_hdmi_calc_cts(clock, &res.cts_44_1khz, res.n_44_1khz, 44100); |
| 97 | r600_hdmi_calc_cts(clock, &res.cts_48khz, res.n_48khz, 48000); |
| 98 | |
| 99 | return res; |
| 100 | } |
| 101 | |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 102 | /* |
| 103 | * update the N and CTS parameters for a given pixel clock rate |
| 104 | */ |
| 105 | static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) |
| 106 | { |
| 107 | struct drm_device *dev = encoder->dev; |
| 108 | struct radeon_device *rdev = dev->dev_private; |
Rafał Miłecki | 1b688d08 | 2012-04-30 15:44:54 +0200 | [diff] [blame] | 109 | struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 110 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 111 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 112 | uint32_t offset = dig->afmt->offset; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 113 | |
Rafał Miłecki | 1b688d08 | 2012-04-30 15:44:54 +0200 | [diff] [blame] | 114 | WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz)); |
| 115 | WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 116 | |
Rafał Miłecki | 1b688d08 | 2012-04-30 15:44:54 +0200 | [diff] [blame] | 117 | WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz)); |
| 118 | WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 119 | |
Rafał Miłecki | 1b688d08 | 2012-04-30 15:44:54 +0200 | [diff] [blame] | 120 | WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz)); |
| 121 | WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 122 | } |
| 123 | |
| 124 | /* |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 125 | * build a HDMI Video Info Frame |
| 126 | */ |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 127 | static void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, |
| 128 | void *buffer, size_t size) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 129 | { |
| 130 | struct drm_device *dev = encoder->dev; |
| 131 | struct radeon_device *rdev = dev->dev_private; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 132 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 133 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 134 | uint32_t offset = dig->afmt->offset; |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 135 | uint8_t *frame = buffer + 3; |
Alex Deucher | f100380 | 2013-06-07 10:41:03 -0400 | [diff] [blame] | 136 | uint8_t *header = buffer; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 137 | |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 138 | WREG32(HDMI0_AVI_INFO0 + offset, |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 139 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 140 | WREG32(HDMI0_AVI_INFO1 + offset, |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 141 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 142 | WREG32(HDMI0_AVI_INFO2 + offset, |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 143 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 144 | WREG32(HDMI0_AVI_INFO3 + offset, |
Alex Deucher | f100380 | 2013-06-07 10:41:03 -0400 | [diff] [blame] | 145 | frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 146 | } |
| 147 | |
| 148 | /* |
| 149 | * build a Audio Info Frame |
| 150 | */ |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 151 | static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder, |
| 152 | const void *buffer, size_t size) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 153 | { |
| 154 | struct drm_device *dev = encoder->dev; |
| 155 | struct radeon_device *rdev = dev->dev_private; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 156 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 157 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 158 | uint32_t offset = dig->afmt->offset; |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 159 | const u8 *frame = buffer + 3; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 160 | |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 161 | WREG32(HDMI0_AUDIO_INFO0 + offset, |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 162 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 163 | WREG32(HDMI0_AUDIO_INFO1 + offset, |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 164 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24)); |
| 165 | } |
| 166 | |
| 167 | /* |
| 168 | * test if audio buffer is filled enough to start playing |
| 169 | */ |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 170 | static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 171 | { |
| 172 | struct drm_device *dev = encoder->dev; |
| 173 | struct radeon_device *rdev = dev->dev_private; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 174 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 175 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 176 | uint32_t offset = dig->afmt->offset; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 177 | |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 178 | return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 179 | } |
| 180 | |
| 181 | /* |
| 182 | * have buffer status changed since last call? |
| 183 | */ |
| 184 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder) |
| 185 | { |
| 186 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 187 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 188 | int status, result; |
| 189 | |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 190 | if (!dig->afmt || !dig->afmt->enabled) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 191 | return 0; |
| 192 | |
| 193 | status = r600_hdmi_is_audio_buffer_filled(encoder); |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 194 | result = dig->afmt->last_buffer_filled_status != status; |
| 195 | dig->afmt->last_buffer_filled_status = status; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 196 | |
| 197 | return result; |
| 198 | } |
| 199 | |
| 200 | /* |
| 201 | * write the audio workaround status to the hardware |
| 202 | */ |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 203 | static void r600_hdmi_audio_workaround(struct drm_encoder *encoder) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 204 | { |
| 205 | struct drm_device *dev = encoder->dev; |
| 206 | struct radeon_device *rdev = dev->dev_private; |
| 207 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 208 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 209 | uint32_t offset = dig->afmt->offset; |
| 210 | bool hdmi_audio_workaround = false; /* FIXME */ |
| 211 | u32 value; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 212 | |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 213 | if (!hdmi_audio_workaround || |
| 214 | r600_hdmi_is_audio_buffer_filled(encoder)) |
| 215 | value = 0; /* disable workaround */ |
| 216 | else |
| 217 | value = HDMI0_AUDIO_TEST_EN; /* enable workaround */ |
| 218 | WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, |
| 219 | value, ~HDMI0_AUDIO_TEST_EN); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 220 | } |
| 221 | |
Alex Deucher | b1f6f47 | 2013-04-18 10:50:55 -0400 | [diff] [blame] | 222 | void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock) |
| 223 | { |
| 224 | struct drm_device *dev = encoder->dev; |
| 225 | struct radeon_device *rdev = dev->dev_private; |
| 226 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 227 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Alex Deucher | 731da21 | 2013-05-13 11:35:26 -0400 | [diff] [blame] | 228 | u32 base_rate = 24000; |
Alex Deucher | b1f6f47 | 2013-04-18 10:50:55 -0400 | [diff] [blame] | 229 | |
| 230 | if (!dig || !dig->afmt) |
| 231 | return; |
| 232 | |
| 233 | /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT. |
| 234 | * doesn't matter which one you use. Just use the first one. |
| 235 | */ |
Alex Deucher | b1f6f47 | 2013-04-18 10:50:55 -0400 | [diff] [blame] | 236 | /* XXX two dtos; generally use dto0 for hdmi */ |
| 237 | /* Express [24MHz / target pixel clock] as an exact rational |
| 238 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
| 239 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
| 240 | */ |
Alex Deucher | 1586505 | 2013-04-22 09:42:07 -0400 | [diff] [blame] | 241 | if (ASIC_IS_DCE3(rdev)) { |
| 242 | /* according to the reg specs, this should DCE3.2 only, but in |
| 243 | * practice it seems to cover DCE3.0 as well. |
| 244 | */ |
Alex Deucher | 731da21 | 2013-05-13 11:35:26 -0400 | [diff] [blame] | 245 | WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100); |
Alex Deucher | 1586505 | 2013-04-22 09:42:07 -0400 | [diff] [blame] | 246 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); |
| 247 | WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ |
| 248 | } else { |
| 249 | /* according to the reg specs, this should be DCE2.0 and DCE3.0 */ |
Alex Deucher | 731da21 | 2013-05-13 11:35:26 -0400 | [diff] [blame] | 250 | WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) | |
| 251 | AUDIO_DTO_MODULE(clock / 10)); |
Alex Deucher | 1586505 | 2013-04-22 09:42:07 -0400 | [diff] [blame] | 252 | } |
Alex Deucher | b1f6f47 | 2013-04-18 10:50:55 -0400 | [diff] [blame] | 253 | } |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 254 | |
| 255 | /* |
| 256 | * update the info frames with the data from the current display mode |
| 257 | */ |
| 258 | void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) |
| 259 | { |
| 260 | struct drm_device *dev = encoder->dev; |
| 261 | struct radeon_device *rdev = dev->dev_private; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 262 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 263 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 264 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; |
| 265 | struct hdmi_avi_infoframe frame; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 266 | uint32_t offset; |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 267 | ssize_t err; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 268 | |
Alex Deucher | c2b4cac | 2013-07-08 18:16:56 -0400 | [diff] [blame^] | 269 | if (!dig || !dig->afmt) |
| 270 | return; |
| 271 | |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 272 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
| 273 | if (!dig->afmt->enabled) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 274 | return; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 275 | offset = dig->afmt->offset; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 276 | |
Alex Deucher | b1f6f47 | 2013-04-18 10:50:55 -0400 | [diff] [blame] | 277 | r600_audio_set_dto(encoder, mode->clock); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 278 | |
Rafał Miłecki | 1c3439f | 2012-05-06 17:29:45 +0200 | [diff] [blame] | 279 | WREG32(HDMI0_VBI_PACKET_CONTROL + offset, |
| 280 | HDMI0_NULL_SEND); /* send null packets when required */ |
| 281 | |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 282 | WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); |
Rafał Miłecki | a273a90 | 2012-04-30 15:44:52 +0200 | [diff] [blame] | 283 | |
Rafał Miłecki | 1c3439f | 2012-05-06 17:29:45 +0200 | [diff] [blame] | 284 | if (ASIC_IS_DCE32(rdev)) { |
| 285 | WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, |
| 286 | HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ |
| 287 | HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ |
| 288 | WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, |
| 289 | AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */ |
| 290 | AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ |
| 291 | } else { |
| 292 | WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, |
| 293 | HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ |
| 294 | HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ |
Rafał Miłecki | 1c3439f | 2012-05-06 17:29:45 +0200 | [diff] [blame] | 295 | HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ |
| 296 | HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ |
| 297 | } |
Rafał Miłecki | a273a90 | 2012-04-30 15:44:52 +0200 | [diff] [blame] | 298 | |
Rafał Miłecki | 1c3439f | 2012-05-06 17:29:45 +0200 | [diff] [blame] | 299 | WREG32(HDMI0_ACR_PACKET_CONTROL + offset, |
| 300 | HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ |
| 301 | HDMI0_ACR_SOURCE); /* select SW CTS value */ |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 302 | |
Rafał Miłecki | 1c3439f | 2012-05-06 17:29:45 +0200 | [diff] [blame] | 303 | WREG32(HDMI0_VBI_PACKET_CONTROL + offset, |
| 304 | HDMI0_NULL_SEND | /* send null packets when required */ |
| 305 | HDMI0_GC_SEND | /* send general control packets */ |
| 306 | HDMI0_GC_CONT); /* send general control packets every frame */ |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 307 | |
Rafał Miłecki | 1c3439f | 2012-05-06 17:29:45 +0200 | [diff] [blame] | 308 | /* TODO: HDMI0_AUDIO_INFO_UPDATE */ |
| 309 | WREG32(HDMI0_INFOFRAME_CONTROL0 + offset, |
| 310 | HDMI0_AVI_INFO_SEND | /* enable AVI info frames */ |
| 311 | HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */ |
| 312 | HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
| 313 | HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */ |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 314 | |
Rafał Miłecki | 1c3439f | 2012-05-06 17:29:45 +0200 | [diff] [blame] | 315 | WREG32(HDMI0_INFOFRAME_CONTROL1 + offset, |
| 316 | HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */ |
| 317 | HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */ |
| 318 | |
| 319 | WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */ |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 320 | |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 321 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); |
| 322 | if (err < 0) { |
| 323 | DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); |
| 324 | return; |
| 325 | } |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 326 | |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 327 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); |
| 328 | if (err < 0) { |
| 329 | DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); |
| 330 | return; |
| 331 | } |
| 332 | |
| 333 | r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); |
Rafał Miłecki | 1c3439f | 2012-05-06 17:29:45 +0200 | [diff] [blame] | 334 | r600_hdmi_update_ACR(encoder, mode->clock); |
| 335 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 336 | /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 337 | WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF); |
| 338 | WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF); |
| 339 | WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001); |
| 340 | WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 341 | |
| 342 | r600_hdmi_audio_workaround(encoder); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 343 | } |
| 344 | |
| 345 | /* |
| 346 | * update settings with current parameters from audio engine |
| 347 | */ |
Christian König | 58bd086 | 2010-04-05 22:14:55 +0200 | [diff] [blame] | 348 | void r600_hdmi_update_audio_settings(struct drm_encoder *encoder) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 349 | { |
| 350 | struct drm_device *dev = encoder->dev; |
| 351 | struct radeon_device *rdev = dev->dev_private; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 352 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 353 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 354 | struct r600_audio audio = r600_audio_status(rdev); |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 355 | uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; |
| 356 | struct hdmi_audio_infoframe frame; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 357 | uint32_t offset; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 358 | uint32_t iec; |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 359 | ssize_t err; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 360 | |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 361 | if (!dig->afmt || !dig->afmt->enabled) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 362 | return; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 363 | offset = dig->afmt->offset; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 364 | |
| 365 | DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n", |
| 366 | r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped", |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 367 | audio.channels, audio.rate, audio.bits_per_sample); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 368 | DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n", |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 369 | (int)audio.status_bits, (int)audio.category_code); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 370 | |
| 371 | iec = 0; |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 372 | if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 373 | iec |= 1 << 0; |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 374 | if (audio.status_bits & AUDIO_STATUS_NONAUDIO) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 375 | iec |= 1 << 1; |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 376 | if (audio.status_bits & AUDIO_STATUS_COPYRIGHT) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 377 | iec |= 1 << 2; |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 378 | if (audio.status_bits & AUDIO_STATUS_EMPHASIS) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 379 | iec |= 1 << 3; |
| 380 | |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 381 | iec |= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 382 | |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 383 | switch (audio.rate) { |
Rafał Miłecki | a366e39 | 2012-05-06 17:29:46 +0200 | [diff] [blame] | 384 | case 32000: |
| 385 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3); |
| 386 | break; |
| 387 | case 44100: |
| 388 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0); |
| 389 | break; |
| 390 | case 48000: |
| 391 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2); |
| 392 | break; |
| 393 | case 88200: |
| 394 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8); |
| 395 | break; |
| 396 | case 96000: |
| 397 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa); |
| 398 | break; |
| 399 | case 176400: |
| 400 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc); |
| 401 | break; |
| 402 | case 192000: |
| 403 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe); |
| 404 | break; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 405 | } |
| 406 | |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 407 | WREG32(HDMI0_60958_0 + offset, iec); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 408 | |
| 409 | iec = 0; |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 410 | switch (audio.bits_per_sample) { |
Rafał Miłecki | a366e39 | 2012-05-06 17:29:46 +0200 | [diff] [blame] | 411 | case 16: |
| 412 | iec |= HDMI0_60958_CS_WORD_LENGTH(0x2); |
| 413 | break; |
| 414 | case 20: |
| 415 | iec |= HDMI0_60958_CS_WORD_LENGTH(0x3); |
| 416 | break; |
| 417 | case 24: |
| 418 | iec |= HDMI0_60958_CS_WORD_LENGTH(0xb); |
| 419 | break; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 420 | } |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 421 | if (audio.status_bits & AUDIO_STATUS_V) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 422 | iec |= 0x5 << 16; |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 423 | WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 424 | |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 425 | err = hdmi_audio_infoframe_init(&frame); |
| 426 | if (err < 0) { |
| 427 | DRM_ERROR("failed to setup audio infoframe\n"); |
| 428 | return; |
| 429 | } |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 430 | |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 431 | frame.channels = audio.channels; |
| 432 | |
| 433 | err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); |
| 434 | if (err < 0) { |
| 435 | DRM_ERROR("failed to pack audio infoframe\n"); |
| 436 | return; |
| 437 | } |
| 438 | |
| 439 | r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer)); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 440 | r600_hdmi_audio_workaround(encoder); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 441 | } |
| 442 | |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 443 | /* |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 444 | * enable the HDMI engine |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 445 | */ |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 446 | void r600_hdmi_enable(struct drm_encoder *encoder, bool enable) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 447 | { |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 448 | struct drm_device *dev = encoder->dev; |
| 449 | struct radeon_device *rdev = dev->dev_private; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 450 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 451 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 452 | u32 hdmi = HDMI0_ERROR_ACK; |
Alex Deucher | 16823d1 | 2010-04-16 11:35:30 -0400 | [diff] [blame] | 453 | |
Alex Deucher | c2b4cac | 2013-07-08 18:16:56 -0400 | [diff] [blame^] | 454 | if (!dig || !dig->afmt) |
| 455 | return; |
| 456 | |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 457 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 458 | if (enable && dig->afmt->enabled) |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 459 | return; |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 460 | if (!enable && !dig->afmt->enabled) |
| 461 | return; |
Rafał Miłecki | 64fb4fb | 2012-04-30 15:44:53 +0200 | [diff] [blame] | 462 | |
| 463 | /* Older chipsets require setting HDMI and routing manually */ |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 464 | if (!ASIC_IS_DCE3(rdev)) { |
| 465 | if (enable) |
| 466 | hdmi |= HDMI0_ENABLE; |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 467 | switch (radeon_encoder->encoder_id) { |
| 468 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 469 | if (enable) { |
| 470 | WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN); |
| 471 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA); |
| 472 | } else { |
| 473 | WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN); |
| 474 | } |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 475 | break; |
| 476 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 477 | if (enable) { |
| 478 | WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN); |
| 479 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA); |
| 480 | } else { |
| 481 | WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN); |
| 482 | } |
Rafał Miłecki | 64fb4fb | 2012-04-30 15:44:53 +0200 | [diff] [blame] | 483 | break; |
| 484 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 485 | if (enable) { |
| 486 | WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN); |
| 487 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA); |
| 488 | } else { |
| 489 | WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN); |
| 490 | } |
Rafał Miłecki | 64fb4fb | 2012-04-30 15:44:53 +0200 | [diff] [blame] | 491 | break; |
| 492 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 493 | if (enable) |
| 494 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA); |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 495 | break; |
| 496 | default: |
Rafał Miłecki | 64fb4fb | 2012-04-30 15:44:53 +0200 | [diff] [blame] | 497 | dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n", |
| 498 | radeon_encoder->encoder_id); |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 499 | break; |
| 500 | } |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 501 | WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi); |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 502 | } |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 503 | |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 504 | if (rdev->irq.installed) { |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 505 | /* if irq is available use it */ |
Alex Deucher | 9054ae1 | 2013-04-18 09:42:13 -0400 | [diff] [blame] | 506 | /* XXX: shouldn't need this on any asics. Double check DCE2/3 */ |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 507 | if (enable) |
Alex Deucher | 9054ae1 | 2013-04-18 09:42:13 -0400 | [diff] [blame] | 508 | radeon_irq_kms_enable_afmt(rdev, dig->afmt->id); |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 509 | else |
| 510 | radeon_irq_kms_disable_afmt(rdev, dig->afmt->id); |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 511 | } |
Christian König | 58bd086 | 2010-04-05 22:14:55 +0200 | [diff] [blame] | 512 | |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 513 | dig->afmt->enabled = enable; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 514 | |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 515 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
| 516 | enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 517 | } |
| 518 | |