blob: a2ae7628bbaaf8e0c0d06a9fab16863aac607777 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * include/asm-s390/smp.h
3 *
4 * S390 version
5 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
7 * Martin Schwidefsky (schwidefsky@de.ibm.com)
8 * Heiko Carstens (heiko.carstens@de.ibm.com)
9 */
10#ifndef __ASM_SMP_H
11#define __ASM_SMP_H
12
13#include <linux/config.h>
14#include <linux/threads.h>
15#include <linux/cpumask.h>
16#include <linux/bitops.h>
17
18#if defined(__KERNEL__) && defined(CONFIG_SMP) && !defined(__ASSEMBLY__)
19
20#include <asm/lowcore.h>
21#include <asm/sigp.h>
22
23/*
24 s390 specific smp.c headers
25 */
26typedef struct
27{
28 int intresting;
29 sigp_ccode ccode;
30 __u32 status;
31 __u16 cpu;
32} sigp_info;
33
34extern int smp_call_function_on(void (*func) (void *info), void *info,
35 int nonatomic, int wait, int cpu);
36#define NO_PROC_ID 0xFF /* No processor magic marker */
37
38/*
39 * This magic constant controls our willingness to transfer
40 * a process across CPUs. Such a transfer incurs misses on the L1
41 * cache, and on a P6 or P5 with multiple L2 caches L2 hits. My
42 * gut feeling is this will vary by board in value. For a board
43 * with separate L2 cache it probably depends also on the RSS, and
44 * for a board with shared L2 cache it ought to decay fast as other
45 * processes are run.
46 */
47
48#define PROC_CHANGE_PENALTY 20 /* Schedule penalty */
49
Ingo Molnar39c715b2005-06-21 17:14:34 -070050#define raw_smp_processor_id() (S390_lowcore.cpu_data.cpu_nr)
Linus Torvalds1da177e2005-04-16 15:20:36 -070051
52extern int smp_get_cpu(cpumask_t cpu_map);
53extern void smp_put_cpu(int cpu);
54
Adrian Bunk4448aaf2005-11-08 21:34:42 -080055static inline __u16 hard_smp_processor_id(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070056{
57 __u16 cpu_address;
58
59 __asm__ ("stap %0\n" : "=m" (cpu_address));
60 return cpu_address;
61}
62
63/*
64 * returns 1 if cpu is in stopped/check stopped state or not operational
65 * returns 0 otherwise
66 */
67static inline int
68smp_cpu_not_running(int cpu)
69{
70 __u32 status;
71
72 switch (signal_processor_ps(&status, 0, cpu, sigp_sense)) {
73 case sigp_order_code_accepted:
74 case sigp_status_stored:
75 /* Check for stopped and check stop state */
76 if (status & 0x50)
77 return 1;
78 break;
79 case sigp_not_operational:
80 return 1;
81 default:
82 break;
83 }
84 return 0;
85}
86
87#define cpu_logical_map(cpu) (cpu)
88
89extern int __cpu_disable (void);
90extern void __cpu_die (unsigned int cpu);
91extern void cpu_die (void) __attribute__ ((noreturn));
92extern int __cpu_up (unsigned int cpu);
93
94#endif
95
96#ifndef CONFIG_SMP
97static inline int
98smp_call_function_on(void (*func) (void *info), void *info,
99 int nonatomic, int wait, int cpu)
100{
101 func(info);
102 return 0;
103}
104#define smp_get_cpu(cpu) ({ 0; })
105#define smp_put_cpu(cpu) ({ 0; })
106#endif
107
108#endif