blob: ef7da1e227e61309c990548fa6ed93b259fe0040 [file] [log] [blame]
John Crispin5644da42013-01-22 20:19:33 +01001/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
John Crispinda5b4cf2013-03-21 17:47:07 +01004 compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc";
John Crispin5644da42013-01-22 20:19:33 +01005
6 cpus {
7 cpu@0 {
8 compatible = "mips,mips24KEc";
9 };
10 };
11
Gabor Juhosd3d2b422013-01-31 20:43:30 +010012 cpuintc: cpuintc@0 {
13 #address-cells = <0>;
14 #interrupt-cells = <1>;
15 interrupt-controller;
16 compatible = "mti,cpu-interrupt-controller";
17 };
18
John Crispin5644da42013-01-22 20:19:33 +010019 palmbus@10000000 {
20 compatible = "palmbus";
21 reg = <0x10000000 0x200000>;
John Crispinda5b4cf2013-03-21 17:47:07 +010022 ranges = <0x0 0x10000000 0x1FFFFF>;
John Crispin5644da42013-01-22 20:19:33 +010023
24 #address-cells = <1>;
25 #size-cells = <1>;
26
27 sysc@0 {
28 compatible = "ralink,rt3052-sysc", "ralink,rt3050-sysc";
29 reg = <0x0 0x100>;
30 };
31
John Crispin5644da42013-01-22 20:19:33 +010032 intc: intc@200 {
33 compatible = "ralink,rt3052-intc", "ralink,rt2880-intc";
34 reg = <0x200 0x100>;
35
36 interrupt-controller;
37 #interrupt-cells = <1>;
Gabor Juhosd3d2b422013-01-31 20:43:30 +010038
39 interrupt-parent = <&cpuintc>;
40 interrupts = <2>;
John Crispin5644da42013-01-22 20:19:33 +010041 };
42
43 memc@300 {
44 compatible = "ralink,rt3052-memc", "ralink,rt3050-memc";
45 reg = <0x300 0x100>;
46 };
47
John Crispin5644da42013-01-22 20:19:33 +010048 uartlite@c00 {
49 compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
50 reg = <0xc00 0x100>;
51
52 interrupt-parent = <&intc>;
53 interrupts = <12>;
54
55 reg-shift = <2>;
56 };
57 };
58};