Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 1 | /* |
| 2 | * 8250-core based driver for the OMAP internal UART |
| 3 | * |
| 4 | * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. |
| 5 | * |
| 6 | * Copyright (C) 2014 Sebastian Andrzej Siewior |
| 7 | * |
| 8 | */ |
| 9 | |
| 10 | #include <linux/device.h> |
| 11 | #include <linux/io.h> |
| 12 | #include <linux/module.h> |
| 13 | #include <linux/serial_8250.h> |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 14 | #include <linux/serial_reg.h> |
Sebastian Andrzej Siewior | 7728524 | 2014-09-29 20:06:48 +0200 | [diff] [blame] | 15 | #include <linux/tty_flip.h> |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/slab.h> |
| 18 | #include <linux/of.h> |
| 19 | #include <linux/of_gpio.h> |
| 20 | #include <linux/of_irq.h> |
| 21 | #include <linux/delay.h> |
| 22 | #include <linux/pm_runtime.h> |
| 23 | #include <linux/console.h> |
| 24 | #include <linux/pm_qos.h> |
Sebastian Andrzej Siewior | 31a1713 | 2014-09-29 20:06:43 +0200 | [diff] [blame] | 25 | #include <linux/dma-mapping.h> |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 26 | |
| 27 | #include "8250.h" |
| 28 | |
| 29 | #define DEFAULT_CLK_SPEED 48000000 |
| 30 | |
| 31 | #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) |
| 32 | #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) |
Sebastian Andrzej Siewior | 31a1713 | 2014-09-29 20:06:43 +0200 | [diff] [blame] | 33 | #define OMAP_DMA_TX_KICK (1 << 2) |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 34 | |
| 35 | #define OMAP_UART_FCR_RX_TRIG 6 |
| 36 | #define OMAP_UART_FCR_TX_TRIG 4 |
| 37 | |
| 38 | /* SCR register bitmasks */ |
| 39 | #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) |
| 40 | #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) |
| 41 | #define OMAP_UART_SCR_TX_EMPTY (1 << 3) |
| 42 | #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) |
| 43 | #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) |
| 44 | #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) |
| 45 | |
| 46 | /* MVR register bitmasks */ |
| 47 | #define OMAP_UART_MVR_SCHEME_SHIFT 30 |
| 48 | #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 |
| 49 | #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 |
| 50 | #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f |
| 51 | #define OMAP_UART_MVR_MAJ_MASK 0x700 |
| 52 | #define OMAP_UART_MVR_MAJ_SHIFT 8 |
| 53 | #define OMAP_UART_MVR_MIN_MASK 0x3f |
| 54 | |
| 55 | #define UART_TI752_TLR_TX 0 |
| 56 | #define UART_TI752_TLR_RX 4 |
| 57 | |
| 58 | #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) |
| 59 | #define TRIGGER_FCR_MASK(x) (x & 3) |
| 60 | |
| 61 | /* Enable XON/XOFF flow control on output */ |
| 62 | #define OMAP_UART_SW_TX 0x08 |
| 63 | /* Enable XON/XOFF flow control on input */ |
| 64 | #define OMAP_UART_SW_RX 0x02 |
| 65 | |
| 66 | #define OMAP_UART_WER_MOD_WKUP 0x7f |
| 67 | #define OMAP_UART_TX_WAKEUP_EN (1 << 7) |
| 68 | |
| 69 | #define TX_TRIGGER 1 |
| 70 | #define RX_TRIGGER 48 |
| 71 | |
| 72 | #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) |
| 73 | #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) |
| 74 | |
| 75 | #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) |
| 76 | |
| 77 | #define OMAP_UART_REV_46 0x0406 |
| 78 | #define OMAP_UART_REV_52 0x0502 |
| 79 | #define OMAP_UART_REV_63 0x0603 |
| 80 | |
| 81 | struct omap8250_priv { |
| 82 | int line; |
| 83 | u8 habit; |
| 84 | u8 mdr1; |
| 85 | u8 efr; |
| 86 | u8 scr; |
| 87 | u8 wer; |
| 88 | u8 xon; |
| 89 | u8 xoff; |
Sebastian Andrzej Siewior | 0a0661d | 2014-09-29 20:06:49 +0200 | [diff] [blame] | 90 | u8 delayed_restore; |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 91 | u16 quot; |
| 92 | |
| 93 | bool is_suspending; |
| 94 | int wakeirq; |
| 95 | int wakeups_enabled; |
| 96 | u32 latency; |
| 97 | u32 calc_latency; |
| 98 | struct pm_qos_request pm_qos_request; |
| 99 | struct work_struct qos_work; |
| 100 | struct uart_8250_dma omap8250_dma; |
| 101 | }; |
| 102 | |
| 103 | static u32 uart_read(struct uart_8250_port *up, u32 reg) |
| 104 | { |
| 105 | return readl(up->port.membase + (reg << up->port.regshift)); |
| 106 | } |
| 107 | |
Peter Hurley | 4bf4ea9 | 2014-12-30 20:28:15 -0500 | [diff] [blame] | 108 | static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) |
| 109 | { |
| 110 | struct uart_8250_port *up = up_to_u8250p(port); |
| 111 | struct omap8250_priv *priv = up->port.private_data; |
| 112 | u8 lcr; |
| 113 | |
| 114 | serial8250_do_set_mctrl(port, mctrl); |
| 115 | |
| 116 | /* |
| 117 | * Turn off autoRTS if RTS is lowered and restore autoRTS setting |
| 118 | * if RTS is raised |
| 119 | */ |
| 120 | lcr = serial_in(up, UART_LCR); |
| 121 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
Peter Hurley | 9719acc | 2015-01-25 14:44:52 -0500 | [diff] [blame] | 122 | if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) |
| 123 | priv->efr |= UART_EFR_RTS; |
Peter Hurley | 4bf4ea9 | 2014-12-30 20:28:15 -0500 | [diff] [blame] | 124 | else |
Peter Hurley | 9719acc | 2015-01-25 14:44:52 -0500 | [diff] [blame] | 125 | priv->efr &= ~UART_EFR_RTS; |
| 126 | serial_out(up, UART_EFR, priv->efr); |
Peter Hurley | 4bf4ea9 | 2014-12-30 20:28:15 -0500 | [diff] [blame] | 127 | serial_out(up, UART_LCR, lcr); |
| 128 | } |
| 129 | |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 130 | /* |
| 131 | * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) |
| 132 | * The access to uart register after MDR1 Access |
| 133 | * causes UART to corrupt data. |
| 134 | * |
| 135 | * Need a delay = |
| 136 | * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) |
| 137 | * give 10 times as much |
| 138 | */ |
| 139 | static void omap_8250_mdr1_errataset(struct uart_8250_port *up, |
| 140 | struct omap8250_priv *priv) |
| 141 | { |
| 142 | u8 timeout = 255; |
| 143 | u8 old_mdr1; |
| 144 | |
| 145 | old_mdr1 = serial_in(up, UART_OMAP_MDR1); |
| 146 | if (old_mdr1 == priv->mdr1) |
| 147 | return; |
| 148 | |
| 149 | serial_out(up, UART_OMAP_MDR1, priv->mdr1); |
| 150 | udelay(2); |
| 151 | serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | |
| 152 | UART_FCR_CLEAR_RCVR); |
| 153 | /* |
| 154 | * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and |
| 155 | * TX_FIFO_E bit is 1. |
| 156 | */ |
| 157 | while (UART_LSR_THRE != (serial_in(up, UART_LSR) & |
| 158 | (UART_LSR_THRE | UART_LSR_DR))) { |
| 159 | timeout--; |
| 160 | if (!timeout) { |
| 161 | /* Should *never* happen. we warn and carry on */ |
| 162 | dev_crit(up->port.dev, "Errata i202: timedout %x\n", |
| 163 | serial_in(up, UART_LSR)); |
| 164 | break; |
| 165 | } |
| 166 | udelay(1); |
| 167 | } |
| 168 | } |
| 169 | |
| 170 | static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, |
| 171 | struct omap8250_priv *priv) |
| 172 | { |
| 173 | unsigned int uartclk = port->uartclk; |
| 174 | unsigned int div_13, div_16; |
| 175 | unsigned int abs_d13, abs_d16; |
| 176 | |
| 177 | /* |
| 178 | * Old custom speed handling. |
| 179 | */ |
| 180 | if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { |
| 181 | priv->quot = port->custom_divisor & 0xffff; |
| 182 | /* |
| 183 | * I assume that nobody is using this. But hey, if somebody |
| 184 | * would like to specify the divisor _and_ the mode then the |
| 185 | * driver is ready and waiting for it. |
| 186 | */ |
| 187 | if (port->custom_divisor & (1 << 16)) |
| 188 | priv->mdr1 = UART_OMAP_MDR1_13X_MODE; |
| 189 | else |
| 190 | priv->mdr1 = UART_OMAP_MDR1_16X_MODE; |
| 191 | return; |
| 192 | } |
| 193 | div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); |
| 194 | div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); |
| 195 | |
| 196 | if (!div_13) |
| 197 | div_13 = 1; |
| 198 | if (!div_16) |
| 199 | div_16 = 1; |
| 200 | |
| 201 | abs_d13 = abs(baud - uartclk / 13 / div_13); |
| 202 | abs_d16 = abs(baud - uartclk / 16 / div_16); |
| 203 | |
| 204 | if (abs_d13 >= abs_d16) { |
| 205 | priv->mdr1 = UART_OMAP_MDR1_16X_MODE; |
| 206 | priv->quot = div_16; |
| 207 | } else { |
| 208 | priv->mdr1 = UART_OMAP_MDR1_13X_MODE; |
| 209 | priv->quot = div_13; |
| 210 | } |
| 211 | } |
| 212 | |
| 213 | static void omap8250_update_scr(struct uart_8250_port *up, |
| 214 | struct omap8250_priv *priv) |
| 215 | { |
| 216 | u8 old_scr; |
| 217 | |
| 218 | old_scr = serial_in(up, UART_OMAP_SCR); |
| 219 | if (old_scr == priv->scr) |
| 220 | return; |
| 221 | |
| 222 | /* |
| 223 | * The manual recommends not to enable the DMA mode selector in the SCR |
| 224 | * (instead of the FCR) register _and_ selecting the DMA mode as one |
| 225 | * register write because this may lead to malfunction. |
| 226 | */ |
| 227 | if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) |
| 228 | serial_out(up, UART_OMAP_SCR, |
| 229 | priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); |
| 230 | serial_out(up, UART_OMAP_SCR, priv->scr); |
| 231 | } |
| 232 | |
| 233 | static void omap8250_restore_regs(struct uart_8250_port *up) |
| 234 | { |
| 235 | struct omap8250_priv *priv = up->port.private_data; |
Sebastian Andrzej Siewior | 0a0661d | 2014-09-29 20:06:49 +0200 | [diff] [blame] | 236 | struct uart_8250_dma *dma = up->dma; |
| 237 | |
| 238 | if (dma && dma->tx_running) { |
| 239 | /* |
| 240 | * TCSANOW requests the change to occur immediately however if |
| 241 | * we have a TX-DMA operation in progress then it has been |
| 242 | * observed that it might stall and never complete. Therefore we |
| 243 | * delay DMA completes to prevent this hang from happen. |
| 244 | */ |
| 245 | priv->delayed_restore = 1; |
| 246 | return; |
| 247 | } |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 248 | |
| 249 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
| 250 | serial_out(up, UART_EFR, UART_EFR_ECB); |
| 251 | |
| 252 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
| 253 | serial_out(up, UART_MCR, UART_MCR_TCRTLR); |
| 254 | serial_out(up, UART_FCR, up->fcr); |
| 255 | |
| 256 | omap8250_update_scr(up, priv); |
| 257 | |
| 258 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
| 259 | |
| 260 | serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | |
| 261 | OMAP_UART_TCR_HALT(52)); |
| 262 | serial_out(up, UART_TI752_TLR, |
| 263 | TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX | |
| 264 | TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX); |
| 265 | |
| 266 | serial_out(up, UART_LCR, 0); |
| 267 | |
| 268 | /* drop TCR + TLR access, we setup XON/XOFF later */ |
| 269 | serial_out(up, UART_MCR, up->mcr); |
| 270 | serial_out(up, UART_IER, up->ier); |
| 271 | |
| 272 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
| 273 | serial_dl_write(up, priv->quot); |
| 274 | |
Peter Hurley | 9719acc | 2015-01-25 14:44:52 -0500 | [diff] [blame] | 275 | serial_out(up, UART_EFR, priv->efr); |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 276 | |
| 277 | /* Configure flow control */ |
| 278 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
| 279 | serial_out(up, UART_XON1, priv->xon); |
| 280 | serial_out(up, UART_XOFF1, priv->xoff); |
| 281 | |
| 282 | serial_out(up, UART_LCR, up->lcr); |
| 283 | /* need mode A for FCR */ |
| 284 | if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) |
| 285 | omap_8250_mdr1_errataset(up, priv); |
| 286 | else |
| 287 | serial_out(up, UART_OMAP_MDR1, priv->mdr1); |
| 288 | up->port.ops->set_mctrl(&up->port, up->port.mctrl); |
| 289 | } |
| 290 | |
| 291 | /* |
| 292 | * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have |
| 293 | * some differences in how we want to handle flow control. |
| 294 | */ |
| 295 | static void omap_8250_set_termios(struct uart_port *port, |
| 296 | struct ktermios *termios, |
| 297 | struct ktermios *old) |
| 298 | { |
| 299 | struct uart_8250_port *up = |
| 300 | container_of(port, struct uart_8250_port, port); |
| 301 | struct omap8250_priv *priv = up->port.private_data; |
| 302 | unsigned char cval = 0; |
| 303 | unsigned int baud; |
| 304 | |
| 305 | switch (termios->c_cflag & CSIZE) { |
| 306 | case CS5: |
| 307 | cval = UART_LCR_WLEN5; |
| 308 | break; |
| 309 | case CS6: |
| 310 | cval = UART_LCR_WLEN6; |
| 311 | break; |
| 312 | case CS7: |
| 313 | cval = UART_LCR_WLEN7; |
| 314 | break; |
| 315 | default: |
| 316 | case CS8: |
| 317 | cval = UART_LCR_WLEN8; |
| 318 | break; |
| 319 | } |
| 320 | |
| 321 | if (termios->c_cflag & CSTOPB) |
| 322 | cval |= UART_LCR_STOP; |
| 323 | if (termios->c_cflag & PARENB) |
| 324 | cval |= UART_LCR_PARITY; |
| 325 | if (!(termios->c_cflag & PARODD)) |
| 326 | cval |= UART_LCR_EPAR; |
| 327 | if (termios->c_cflag & CMSPAR) |
| 328 | cval |= UART_LCR_SPAR; |
| 329 | |
| 330 | /* |
| 331 | * Ask the core to calculate the divisor for us. |
| 332 | */ |
| 333 | baud = uart_get_baud_rate(port, termios, old, |
| 334 | port->uartclk / 16 / 0xffff, |
| 335 | port->uartclk / 13); |
| 336 | omap_8250_get_divisor(port, baud, priv); |
| 337 | |
| 338 | /* |
| 339 | * Ok, we're now changing the port state. Do it with |
| 340 | * interrupts disabled. |
| 341 | */ |
| 342 | pm_runtime_get_sync(port->dev); |
| 343 | spin_lock_irq(&port->lock); |
| 344 | |
| 345 | /* |
| 346 | * Update the per-port timeout. |
| 347 | */ |
| 348 | uart_update_timeout(port, termios->c_cflag, baud); |
| 349 | |
| 350 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; |
| 351 | if (termios->c_iflag & INPCK) |
| 352 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; |
| 353 | if (termios->c_iflag & (IGNBRK | PARMRK)) |
| 354 | up->port.read_status_mask |= UART_LSR_BI; |
| 355 | |
| 356 | /* |
| 357 | * Characters to ignore |
| 358 | */ |
| 359 | up->port.ignore_status_mask = 0; |
| 360 | if (termios->c_iflag & IGNPAR) |
| 361 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; |
| 362 | if (termios->c_iflag & IGNBRK) { |
| 363 | up->port.ignore_status_mask |= UART_LSR_BI; |
| 364 | /* |
| 365 | * If we're ignoring parity and break indicators, |
| 366 | * ignore overruns too (for real raw support). |
| 367 | */ |
| 368 | if (termios->c_iflag & IGNPAR) |
| 369 | up->port.ignore_status_mask |= UART_LSR_OE; |
| 370 | } |
| 371 | |
| 372 | /* |
| 373 | * ignore all characters if CREAD is not set |
| 374 | */ |
| 375 | if ((termios->c_cflag & CREAD) == 0) |
| 376 | up->port.ignore_status_mask |= UART_LSR_DR; |
| 377 | |
| 378 | /* |
| 379 | * Modem status interrupts |
| 380 | */ |
| 381 | up->ier &= ~UART_IER_MSI; |
| 382 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) |
| 383 | up->ier |= UART_IER_MSI; |
| 384 | |
| 385 | up->lcr = cval; |
| 386 | /* Up to here it was mostly serial8250_do_set_termios() */ |
| 387 | |
| 388 | /* |
| 389 | * We enable TRIG_GRANU for RX and TX and additionaly we set |
| 390 | * SCR_TX_EMPTY bit. The result is the following: |
| 391 | * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. |
| 392 | * - less than RX_TRIGGER number of bytes will also cause an interrupt |
| 393 | * once the UART decides that there no new bytes arriving. |
| 394 | * - Once THRE is enabled, the interrupt will be fired once the FIFO is |
| 395 | * empty - the trigger level is ignored here. |
| 396 | * |
| 397 | * Once DMA is enabled: |
| 398 | * - UART will assert the TX DMA line once there is room for TX_TRIGGER |
| 399 | * bytes in the TX FIFO. On each assert the DMA engine will move |
| 400 | * TX_TRIGGER bytes into the FIFO. |
| 401 | * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in |
| 402 | * the FIFO and move RX_TRIGGER bytes. |
| 403 | * This is because threshold and trigger values are the same. |
| 404 | */ |
| 405 | up->fcr = UART_FCR_ENABLE_FIFO; |
| 406 | up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG; |
| 407 | up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG; |
| 408 | |
| 409 | priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | |
| 410 | OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; |
| 411 | |
Sebastian Andrzej Siewior | 0a0661d | 2014-09-29 20:06:49 +0200 | [diff] [blame] | 412 | if (up->dma) |
| 413 | priv->scr |= OMAP_UART_SCR_DMAMODE_1 | |
| 414 | OMAP_UART_SCR_DMAMODE_CTL; |
| 415 | |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 416 | priv->xon = termios->c_cc[VSTART]; |
| 417 | priv->xoff = termios->c_cc[VSTOP]; |
| 418 | |
| 419 | priv->efr = 0; |
| 420 | up->mcr &= ~(UART_MCR_RTS | UART_MCR_XONANY); |
Peter Hurley | 391f93f | 2015-01-25 14:44:51 -0500 | [diff] [blame] | 421 | up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); |
| 422 | |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 423 | if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { |
Peter Hurley | 9719acc | 2015-01-25 14:44:52 -0500 | [diff] [blame] | 424 | /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ |
Peter Hurley | 391f93f | 2015-01-25 14:44:51 -0500 | [diff] [blame] | 425 | up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; |
Peter Hurley | 9719acc | 2015-01-25 14:44:52 -0500 | [diff] [blame] | 426 | priv->efr |= UART_EFR_CTS; |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 427 | } else if (up->port.flags & UPF_SOFT_FLOW) { |
| 428 | /* |
| 429 | * IXON Flag: |
| 430 | * Enable XON/XOFF flow control on input. |
| 431 | * Receiver compares XON1, XOFF1. |
| 432 | */ |
| 433 | if (termios->c_iflag & IXON) |
| 434 | priv->efr |= OMAP_UART_SW_RX; |
| 435 | |
| 436 | /* |
| 437 | * IXOFF Flag: |
| 438 | * Enable XON/XOFF flow control on output. |
| 439 | * Transmit XON1, XOFF1 |
| 440 | */ |
Peter Hurley | 391f93f | 2015-01-25 14:44:51 -0500 | [diff] [blame] | 441 | if (termios->c_iflag & IXOFF) { |
| 442 | up->port.status |= UPSTAT_AUTOXOFF; |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 443 | priv->efr |= OMAP_UART_SW_TX; |
Peter Hurley | 391f93f | 2015-01-25 14:44:51 -0500 | [diff] [blame] | 444 | } |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 445 | |
| 446 | /* |
| 447 | * IXANY Flag: |
| 448 | * Enable any character to restart output. |
| 449 | * Operation resumes after receiving any |
| 450 | * character after recognition of the XOFF character |
| 451 | */ |
| 452 | if (termios->c_iflag & IXANY) |
| 453 | up->mcr |= UART_MCR_XONANY; |
| 454 | } |
| 455 | omap8250_restore_regs(up); |
| 456 | |
| 457 | spin_unlock_irq(&up->port.lock); |
| 458 | pm_runtime_mark_last_busy(port->dev); |
| 459 | pm_runtime_put_autosuspend(port->dev); |
| 460 | |
| 461 | /* calculate wakeup latency constraint */ |
| 462 | priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; |
| 463 | priv->latency = priv->calc_latency; |
| 464 | |
| 465 | schedule_work(&priv->qos_work); |
| 466 | |
| 467 | /* Don't rewrite B0 */ |
| 468 | if (tty_termios_baud_rate(termios)) |
| 469 | tty_termios_encode_baud_rate(termios, baud, baud); |
| 470 | } |
| 471 | |
| 472 | /* same as 8250 except that we may have extra flow bits set in EFR */ |
| 473 | static void omap_8250_pm(struct uart_port *port, unsigned int state, |
| 474 | unsigned int oldstate) |
| 475 | { |
Peter Hurley | 3e29af2 | 2014-12-31 16:32:49 -0500 | [diff] [blame] | 476 | struct uart_8250_port *up = up_to_u8250p(port); |
| 477 | u8 efr; |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 478 | |
| 479 | pm_runtime_get_sync(port->dev); |
| 480 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
Peter Hurley | 3e29af2 | 2014-12-31 16:32:49 -0500 | [diff] [blame] | 481 | efr = serial_in(up, UART_EFR); |
| 482 | serial_out(up, UART_EFR, efr | UART_EFR_ECB); |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 483 | serial_out(up, UART_LCR, 0); |
| 484 | |
| 485 | serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); |
| 486 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
Peter Hurley | 3e29af2 | 2014-12-31 16:32:49 -0500 | [diff] [blame] | 487 | serial_out(up, UART_EFR, efr); |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 488 | serial_out(up, UART_LCR, 0); |
| 489 | |
| 490 | pm_runtime_mark_last_busy(port->dev); |
| 491 | pm_runtime_put_autosuspend(port->dev); |
| 492 | } |
| 493 | |
| 494 | static void omap_serial_fill_features_erratas(struct uart_8250_port *up, |
| 495 | struct omap8250_priv *priv) |
| 496 | { |
| 497 | u32 mvr, scheme; |
| 498 | u16 revision, major, minor; |
| 499 | |
| 500 | mvr = uart_read(up, UART_OMAP_MVER); |
| 501 | |
| 502 | /* Check revision register scheme */ |
| 503 | scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; |
| 504 | |
| 505 | switch (scheme) { |
| 506 | case 0: /* Legacy Scheme: OMAP2/3 */ |
| 507 | /* MINOR_REV[0:4], MAJOR_REV[4:7] */ |
| 508 | major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> |
| 509 | OMAP_UART_LEGACY_MVR_MAJ_SHIFT; |
| 510 | minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); |
| 511 | break; |
| 512 | case 1: |
| 513 | /* New Scheme: OMAP4+ */ |
| 514 | /* MINOR_REV[0:5], MAJOR_REV[8:10] */ |
| 515 | major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> |
| 516 | OMAP_UART_MVR_MAJ_SHIFT; |
| 517 | minor = (mvr & OMAP_UART_MVR_MIN_MASK); |
| 518 | break; |
| 519 | default: |
| 520 | dev_warn(up->port.dev, |
| 521 | "Unknown revision, defaulting to highest\n"); |
| 522 | /* highest possible revision */ |
| 523 | major = 0xff; |
| 524 | minor = 0xff; |
| 525 | } |
| 526 | /* normalize revision for the driver */ |
| 527 | revision = UART_BUILD_REVISION(major, minor); |
| 528 | |
| 529 | switch (revision) { |
| 530 | case OMAP_UART_REV_46: |
| 531 | priv->habit = UART_ERRATA_i202_MDR1_ACCESS; |
| 532 | break; |
| 533 | case OMAP_UART_REV_52: |
| 534 | priv->habit = UART_ERRATA_i202_MDR1_ACCESS | |
| 535 | OMAP_UART_WER_HAS_TX_WAKEUP; |
| 536 | break; |
| 537 | case OMAP_UART_REV_63: |
| 538 | priv->habit = UART_ERRATA_i202_MDR1_ACCESS | |
| 539 | OMAP_UART_WER_HAS_TX_WAKEUP; |
| 540 | break; |
| 541 | default: |
| 542 | break; |
| 543 | } |
| 544 | } |
| 545 | |
| 546 | static void omap8250_uart_qos_work(struct work_struct *work) |
| 547 | { |
| 548 | struct omap8250_priv *priv; |
| 549 | |
| 550 | priv = container_of(work, struct omap8250_priv, qos_work); |
| 551 | pm_qos_update_request(&priv->pm_qos_request, priv->latency); |
| 552 | } |
| 553 | |
| 554 | static irqreturn_t omap_wake_irq(int irq, void *dev_id) |
| 555 | { |
| 556 | struct uart_port *port = dev_id; |
| 557 | int ret; |
| 558 | |
| 559 | ret = port->handle_irq(port); |
| 560 | if (ret) |
| 561 | return IRQ_HANDLED; |
| 562 | return IRQ_NONE; |
| 563 | } |
| 564 | |
Sebastian Andrzej Siewior | 9809889 | 2015-05-20 22:07:35 +0200 | [diff] [blame] | 565 | #ifdef CONFIG_SERIAL_8250_DMA |
| 566 | static int omap_8250_dma_handle_irq(struct uart_port *port); |
| 567 | #endif |
| 568 | |
| 569 | static irqreturn_t omap8250_irq(int irq, void *dev_id) |
| 570 | { |
| 571 | struct uart_port *port = dev_id; |
| 572 | struct uart_8250_port *up = up_to_u8250p(port); |
| 573 | unsigned int iir; |
| 574 | int ret; |
| 575 | |
| 576 | #ifdef CONFIG_SERIAL_8250_DMA |
| 577 | if (up->dma) { |
| 578 | ret = omap_8250_dma_handle_irq(port); |
| 579 | return IRQ_RETVAL(ret); |
| 580 | } |
| 581 | #endif |
| 582 | |
| 583 | serial8250_rpm_get(up); |
| 584 | iir = serial_port_in(port, UART_IIR); |
| 585 | ret = serial8250_handle_irq(port, iir); |
| 586 | serial8250_rpm_put(up); |
| 587 | |
| 588 | return IRQ_RETVAL(ret); |
| 589 | } |
| 590 | |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 591 | static int omap_8250_startup(struct uart_port *port) |
| 592 | { |
Sebastian Andrzej Siewior | 9809889 | 2015-05-20 22:07:35 +0200 | [diff] [blame] | 593 | struct uart_8250_port *up = up_to_u8250p(port); |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 594 | struct omap8250_priv *priv = port->private_data; |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 595 | int ret; |
| 596 | |
| 597 | if (priv->wakeirq) { |
| 598 | ret = request_irq(priv->wakeirq, omap_wake_irq, |
| 599 | port->irqflags, "uart wakeup irq", port); |
| 600 | if (ret) |
| 601 | return ret; |
| 602 | disable_irq(priv->wakeirq); |
| 603 | } |
| 604 | |
| 605 | pm_runtime_get_sync(port->dev); |
| 606 | |
Sebastian Andrzej Siewior | 9809889 | 2015-05-20 22:07:35 +0200 | [diff] [blame] | 607 | up->mcr = 0; |
| 608 | serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); |
| 609 | |
| 610 | serial_out(up, UART_LCR, UART_LCR_WLEN8); |
| 611 | |
| 612 | up->lsr_saved_flags = 0; |
| 613 | up->msr_saved_flags = 0; |
| 614 | |
| 615 | if (up->dma) { |
| 616 | ret = serial8250_request_dma(up); |
| 617 | if (ret) { |
| 618 | dev_warn_ratelimited(port->dev, |
| 619 | "failed to request DMA\n"); |
| 620 | up->dma = NULL; |
| 621 | } |
| 622 | } |
| 623 | |
| 624 | ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED, |
| 625 | dev_name(port->dev), port); |
| 626 | if (ret < 0) |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 627 | goto err; |
| 628 | |
Sebastian Andrzej Siewior | 9809889 | 2015-05-20 22:07:35 +0200 | [diff] [blame] | 629 | up->ier = UART_IER_RLSI | UART_IER_RDI; |
| 630 | serial_out(up, UART_IER, up->ier); |
| 631 | |
Rafael J. Wysocki | 71504e5 | 2014-12-19 15:27:58 +0100 | [diff] [blame] | 632 | #ifdef CONFIG_PM |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 633 | up->capabilities |= UART_CAP_RPM; |
| 634 | #endif |
| 635 | |
| 636 | /* Enable module level wake up */ |
| 637 | priv->wer = OMAP_UART_WER_MOD_WKUP; |
| 638 | if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) |
| 639 | priv->wer |= OMAP_UART_TX_WAKEUP_EN; |
| 640 | serial_out(up, UART_OMAP_WER, priv->wer); |
| 641 | |
Sebastian Andrzej Siewior | 0a0661d | 2014-09-29 20:06:49 +0200 | [diff] [blame] | 642 | if (up->dma) |
| 643 | up->dma->rx_dma(up, 0); |
| 644 | |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 645 | pm_runtime_mark_last_busy(port->dev); |
| 646 | pm_runtime_put_autosuspend(port->dev); |
| 647 | return 0; |
| 648 | err: |
| 649 | pm_runtime_mark_last_busy(port->dev); |
| 650 | pm_runtime_put_autosuspend(port->dev); |
| 651 | if (priv->wakeirq) |
| 652 | free_irq(priv->wakeirq, port); |
| 653 | return ret; |
| 654 | } |
| 655 | |
| 656 | static void omap_8250_shutdown(struct uart_port *port) |
| 657 | { |
Sebastian Andrzej Siewior | 9809889 | 2015-05-20 22:07:35 +0200 | [diff] [blame] | 658 | struct uart_8250_port *up = up_to_u8250p(port); |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 659 | struct omap8250_priv *priv = port->private_data; |
| 660 | |
| 661 | flush_work(&priv->qos_work); |
Sebastian Andrzej Siewior | 0a0661d | 2014-09-29 20:06:49 +0200 | [diff] [blame] | 662 | if (up->dma) |
| 663 | up->dma->rx_dma(up, UART_IIR_RX_TIMEOUT); |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 664 | |
| 665 | pm_runtime_get_sync(port->dev); |
| 666 | |
| 667 | serial_out(up, UART_OMAP_WER, 0); |
Sebastian Andrzej Siewior | 9809889 | 2015-05-20 22:07:35 +0200 | [diff] [blame] | 668 | |
| 669 | up->ier = 0; |
| 670 | serial_out(up, UART_IER, 0); |
| 671 | |
| 672 | if (up->dma) |
| 673 | serial8250_release_dma(up); |
| 674 | |
| 675 | /* |
| 676 | * Disable break condition and FIFOs |
| 677 | */ |
| 678 | if (up->lcr & UART_LCR_SBC) |
| 679 | serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); |
| 680 | serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 681 | |
| 682 | pm_runtime_mark_last_busy(port->dev); |
| 683 | pm_runtime_put_autosuspend(port->dev); |
| 684 | |
Sebastian Andrzej Siewior | 9809889 | 2015-05-20 22:07:35 +0200 | [diff] [blame] | 685 | free_irq(port->irq, port); |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 686 | if (priv->wakeirq) |
| 687 | free_irq(priv->wakeirq, port); |
| 688 | } |
| 689 | |
| 690 | static void omap_8250_throttle(struct uart_port *port) |
| 691 | { |
| 692 | unsigned long flags; |
| 693 | struct uart_8250_port *up = |
| 694 | container_of(port, struct uart_8250_port, port); |
| 695 | |
| 696 | pm_runtime_get_sync(port->dev); |
| 697 | |
| 698 | spin_lock_irqsave(&port->lock, flags); |
| 699 | up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); |
| 700 | serial_out(up, UART_IER, up->ier); |
| 701 | spin_unlock_irqrestore(&port->lock, flags); |
| 702 | |
| 703 | pm_runtime_mark_last_busy(port->dev); |
| 704 | pm_runtime_put_autosuspend(port->dev); |
| 705 | } |
| 706 | |
| 707 | static void omap_8250_unthrottle(struct uart_port *port) |
| 708 | { |
| 709 | unsigned long flags; |
| 710 | struct uart_8250_port *up = |
| 711 | container_of(port, struct uart_8250_port, port); |
| 712 | |
| 713 | pm_runtime_get_sync(port->dev); |
| 714 | |
| 715 | spin_lock_irqsave(&port->lock, flags); |
| 716 | up->ier |= UART_IER_RLSI | UART_IER_RDI; |
| 717 | serial_out(up, UART_IER, up->ier); |
| 718 | spin_unlock_irqrestore(&port->lock, flags); |
| 719 | |
| 720 | pm_runtime_mark_last_busy(port->dev); |
| 721 | pm_runtime_put_autosuspend(port->dev); |
| 722 | } |
| 723 | |
Sebastian Andrzej Siewior | 31a1713 | 2014-09-29 20:06:43 +0200 | [diff] [blame] | 724 | #ifdef CONFIG_SERIAL_8250_DMA |
Sebastian Andrzej Siewior | 0e31c8d | 2014-09-29 20:06:44 +0200 | [diff] [blame] | 725 | static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir); |
| 726 | |
| 727 | static void __dma_rx_do_complete(struct uart_8250_port *p, bool error) |
| 728 | { |
| 729 | struct uart_8250_dma *dma = p->dma; |
| 730 | struct tty_port *tty_port = &p->port.state->port; |
| 731 | struct dma_tx_state state; |
| 732 | int count; |
| 733 | |
| 734 | dma_sync_single_for_cpu(dma->rxchan->device->dev, dma->rx_addr, |
| 735 | dma->rx_size, DMA_FROM_DEVICE); |
| 736 | |
| 737 | dma->rx_running = 0; |
| 738 | dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); |
| 739 | dmaengine_terminate_all(dma->rxchan); |
| 740 | |
| 741 | count = dma->rx_size - state.residue; |
| 742 | |
| 743 | tty_insert_flip_string(tty_port, dma->rx_buf, count); |
| 744 | p->port.icount.rx += count; |
| 745 | if (!error) |
| 746 | omap_8250_rx_dma(p, 0); |
| 747 | |
| 748 | tty_flip_buffer_push(tty_port); |
| 749 | } |
| 750 | |
| 751 | static void __dma_rx_complete(void *param) |
| 752 | { |
| 753 | __dma_rx_do_complete(param, false); |
| 754 | } |
| 755 | |
| 756 | static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir) |
| 757 | { |
| 758 | struct uart_8250_dma *dma = p->dma; |
| 759 | struct dma_async_tx_descriptor *desc; |
| 760 | |
| 761 | switch (iir & 0x3f) { |
| 762 | case UART_IIR_RLSI: |
| 763 | /* 8250_core handles errors and break interrupts */ |
| 764 | if (dma->rx_running) { |
| 765 | dmaengine_pause(dma->rxchan); |
| 766 | __dma_rx_do_complete(p, true); |
| 767 | } |
| 768 | return -EIO; |
| 769 | case UART_IIR_RX_TIMEOUT: |
| 770 | /* |
| 771 | * If RCVR FIFO trigger level was not reached, complete the |
| 772 | * transfer and let 8250_core copy the remaining data. |
| 773 | */ |
| 774 | if (dma->rx_running) { |
| 775 | dmaengine_pause(dma->rxchan); |
| 776 | __dma_rx_do_complete(p, true); |
| 777 | } |
| 778 | return -ETIMEDOUT; |
| 779 | case UART_IIR_RDI: |
| 780 | /* |
| 781 | * The OMAP UART is a special BEAST. If we receive RDI we _have_ |
| 782 | * a DMA transfer programmed but it didn't work. One reason is |
| 783 | * that we were too slow and there were too many bytes in the |
| 784 | * FIFO, the UART counted wrong and never kicked the DMA engine |
| 785 | * to do anything. That means once we receive RDI on OMAP then |
| 786 | * the DMA won't do anything soon so we have to cancel the DMA |
| 787 | * transfer and purge the FIFO manually. |
| 788 | */ |
| 789 | if (dma->rx_running) { |
| 790 | dmaengine_pause(dma->rxchan); |
| 791 | __dma_rx_do_complete(p, true); |
| 792 | } |
| 793 | return -ETIMEDOUT; |
| 794 | |
| 795 | default: |
| 796 | break; |
| 797 | } |
| 798 | |
| 799 | if (dma->rx_running) |
| 800 | return 0; |
| 801 | |
| 802 | desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, |
| 803 | dma->rx_size, DMA_DEV_TO_MEM, |
| 804 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 805 | if (!desc) |
| 806 | return -EBUSY; |
| 807 | |
| 808 | dma->rx_running = 1; |
| 809 | desc->callback = __dma_rx_complete; |
| 810 | desc->callback_param = p; |
| 811 | |
| 812 | dma->rx_cookie = dmaengine_submit(desc); |
| 813 | |
| 814 | dma_sync_single_for_device(dma->rxchan->device->dev, dma->rx_addr, |
| 815 | dma->rx_size, DMA_FROM_DEVICE); |
| 816 | |
| 817 | dma_async_issue_pending(dma->rxchan); |
| 818 | return 0; |
| 819 | } |
| 820 | |
Sebastian Andrzej Siewior | 31a1713 | 2014-09-29 20:06:43 +0200 | [diff] [blame] | 821 | static int omap_8250_tx_dma(struct uart_8250_port *p); |
| 822 | |
| 823 | static void omap_8250_dma_tx_complete(void *param) |
| 824 | { |
| 825 | struct uart_8250_port *p = param; |
| 826 | struct uart_8250_dma *dma = p->dma; |
| 827 | struct circ_buf *xmit = &p->port.state->xmit; |
| 828 | unsigned long flags; |
| 829 | bool en_thri = false; |
Sebastian Andrzej Siewior | 0a0661d | 2014-09-29 20:06:49 +0200 | [diff] [blame] | 830 | struct omap8250_priv *priv = p->port.private_data; |
Sebastian Andrzej Siewior | 31a1713 | 2014-09-29 20:06:43 +0200 | [diff] [blame] | 831 | |
| 832 | dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, |
| 833 | UART_XMIT_SIZE, DMA_TO_DEVICE); |
| 834 | |
| 835 | spin_lock_irqsave(&p->port.lock, flags); |
| 836 | |
| 837 | dma->tx_running = 0; |
| 838 | |
| 839 | xmit->tail += dma->tx_size; |
| 840 | xmit->tail &= UART_XMIT_SIZE - 1; |
| 841 | p->port.icount.tx += dma->tx_size; |
| 842 | |
Sebastian Andrzej Siewior | 0a0661d | 2014-09-29 20:06:49 +0200 | [diff] [blame] | 843 | if (priv->delayed_restore) { |
| 844 | priv->delayed_restore = 0; |
| 845 | omap8250_restore_regs(p); |
| 846 | } |
| 847 | |
Sebastian Andrzej Siewior | 31a1713 | 2014-09-29 20:06:43 +0200 | [diff] [blame] | 848 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
| 849 | uart_write_wakeup(&p->port); |
| 850 | |
| 851 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) { |
| 852 | int ret; |
| 853 | |
| 854 | ret = omap_8250_tx_dma(p); |
| 855 | if (ret) |
| 856 | en_thri = true; |
| 857 | |
| 858 | } else if (p->capabilities & UART_CAP_RPM) { |
| 859 | en_thri = true; |
| 860 | } |
| 861 | |
| 862 | if (en_thri) { |
| 863 | dma->tx_err = 1; |
| 864 | p->ier |= UART_IER_THRI; |
| 865 | serial_port_out(&p->port, UART_IER, p->ier); |
| 866 | } |
| 867 | |
| 868 | spin_unlock_irqrestore(&p->port.lock, flags); |
| 869 | } |
| 870 | |
| 871 | static int omap_8250_tx_dma(struct uart_8250_port *p) |
| 872 | { |
| 873 | struct uart_8250_dma *dma = p->dma; |
| 874 | struct omap8250_priv *priv = p->port.private_data; |
| 875 | struct circ_buf *xmit = &p->port.state->xmit; |
| 876 | struct dma_async_tx_descriptor *desc; |
| 877 | unsigned int skip_byte = 0; |
| 878 | int ret; |
| 879 | |
| 880 | if (dma->tx_running) |
| 881 | return 0; |
| 882 | if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) { |
| 883 | |
| 884 | /* |
| 885 | * Even if no data, we need to return an error for the two cases |
| 886 | * below so serial8250_tx_chars() is invoked and properly clears |
| 887 | * THRI and/or runtime suspend. |
| 888 | */ |
| 889 | if (dma->tx_err || p->capabilities & UART_CAP_RPM) { |
| 890 | ret = -EBUSY; |
| 891 | goto err; |
| 892 | } |
| 893 | if (p->ier & UART_IER_THRI) { |
| 894 | p->ier &= ~UART_IER_THRI; |
| 895 | serial_out(p, UART_IER, p->ier); |
| 896 | } |
| 897 | return 0; |
| 898 | } |
| 899 | |
| 900 | dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); |
| 901 | if (priv->habit & OMAP_DMA_TX_KICK) { |
| 902 | u8 tx_lvl; |
| 903 | |
| 904 | /* |
| 905 | * We need to put the first byte into the FIFO in order to start |
| 906 | * the DMA transfer. For transfers smaller than four bytes we |
| 907 | * don't bother doing DMA at all. It seem not matter if there |
| 908 | * are still bytes in the FIFO from the last transfer (in case |
| 909 | * we got here directly from omap_8250_dma_tx_complete()). Bytes |
| 910 | * leaving the FIFO seem not to trigger the DMA transfer. It is |
| 911 | * really the byte that we put into the FIFO. |
| 912 | * If the FIFO is already full then we most likely got here from |
| 913 | * omap_8250_dma_tx_complete(). And this means the DMA engine |
| 914 | * just completed its work. We don't have to wait the complete |
| 915 | * 86us at 115200,8n1 but around 60us (not to mention lower |
| 916 | * baudrates). So in that case we take the interrupt and try |
| 917 | * again with an empty FIFO. |
| 918 | */ |
| 919 | tx_lvl = serial_in(p, UART_OMAP_TX_LVL); |
| 920 | if (tx_lvl == p->tx_loadsz) { |
| 921 | ret = -EBUSY; |
| 922 | goto err; |
| 923 | } |
| 924 | if (dma->tx_size < 4) { |
| 925 | ret = -EINVAL; |
| 926 | goto err; |
| 927 | } |
| 928 | skip_byte = 1; |
| 929 | } |
| 930 | |
| 931 | desc = dmaengine_prep_slave_single(dma->txchan, |
| 932 | dma->tx_addr + xmit->tail + skip_byte, |
| 933 | dma->tx_size - skip_byte, DMA_MEM_TO_DEV, |
| 934 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 935 | if (!desc) { |
| 936 | ret = -EBUSY; |
| 937 | goto err; |
| 938 | } |
| 939 | |
| 940 | dma->tx_running = 1; |
| 941 | |
| 942 | desc->callback = omap_8250_dma_tx_complete; |
| 943 | desc->callback_param = p; |
| 944 | |
| 945 | dma->tx_cookie = dmaengine_submit(desc); |
| 946 | |
| 947 | dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, |
| 948 | UART_XMIT_SIZE, DMA_TO_DEVICE); |
| 949 | |
| 950 | dma_async_issue_pending(dma->txchan); |
| 951 | if (dma->tx_err) |
| 952 | dma->tx_err = 0; |
| 953 | |
| 954 | if (p->ier & UART_IER_THRI) { |
| 955 | p->ier &= ~UART_IER_THRI; |
| 956 | serial_out(p, UART_IER, p->ier); |
| 957 | } |
| 958 | if (skip_byte) |
| 959 | serial_out(p, UART_TX, xmit->buf[xmit->tail]); |
| 960 | return 0; |
| 961 | err: |
| 962 | dma->tx_err = 1; |
| 963 | return ret; |
| 964 | } |
| 965 | |
Sebastian Andrzej Siewior | 7728524 | 2014-09-29 20:06:48 +0200 | [diff] [blame] | 966 | /* |
| 967 | * This is mostly serial8250_handle_irq(). We have a slightly different DMA |
| 968 | * hoook for RX/TX and need different logic for them in the ISR. Therefore we |
| 969 | * use the default routine in the non-DMA case and this one for with DMA. |
| 970 | */ |
| 971 | static int omap_8250_dma_handle_irq(struct uart_port *port) |
| 972 | { |
| 973 | struct uart_8250_port *up = up_to_u8250p(port); |
| 974 | unsigned char status; |
| 975 | unsigned long flags; |
| 976 | u8 iir; |
| 977 | int dma_err = 0; |
| 978 | |
| 979 | serial8250_rpm_get(up); |
| 980 | |
| 981 | iir = serial_port_in(port, UART_IIR); |
| 982 | if (iir & UART_IIR_NO_INT) { |
| 983 | serial8250_rpm_put(up); |
| 984 | return 0; |
| 985 | } |
| 986 | |
| 987 | spin_lock_irqsave(&port->lock, flags); |
| 988 | |
| 989 | status = serial_port_in(port, UART_LSR); |
| 990 | |
| 991 | if (status & (UART_LSR_DR | UART_LSR_BI)) { |
| 992 | |
| 993 | dma_err = omap_8250_rx_dma(up, iir); |
| 994 | if (dma_err) { |
| 995 | status = serial8250_rx_chars(up, status); |
| 996 | omap_8250_rx_dma(up, 0); |
| 997 | } |
| 998 | } |
| 999 | serial8250_modem_status(up); |
| 1000 | if (status & UART_LSR_THRE && up->dma->tx_err) { |
| 1001 | if (uart_tx_stopped(&up->port) || |
| 1002 | uart_circ_empty(&up->port.state->xmit)) { |
| 1003 | up->dma->tx_err = 0; |
| 1004 | serial8250_tx_chars(up); |
| 1005 | } else { |
| 1006 | /* |
| 1007 | * try again due to an earlier failer which |
| 1008 | * might have been resolved by now. |
| 1009 | */ |
| 1010 | dma_err = omap_8250_tx_dma(up); |
| 1011 | if (dma_err) |
| 1012 | serial8250_tx_chars(up); |
| 1013 | } |
| 1014 | } |
| 1015 | |
| 1016 | spin_unlock_irqrestore(&port->lock, flags); |
| 1017 | serial8250_rpm_put(up); |
| 1018 | return 1; |
| 1019 | } |
Sebastian Andrzej Siewior | 0a0661d | 2014-09-29 20:06:49 +0200 | [diff] [blame] | 1020 | |
| 1021 | static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) |
| 1022 | { |
| 1023 | return false; |
| 1024 | } |
| 1025 | |
| 1026 | #else |
| 1027 | |
| 1028 | static inline int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir) |
| 1029 | { |
| 1030 | return -EINVAL; |
| 1031 | } |
Sebastian Andrzej Siewior | 31a1713 | 2014-09-29 20:06:43 +0200 | [diff] [blame] | 1032 | #endif |
| 1033 | |
Sebastian Andrzej Siewior | 9809889 | 2015-05-20 22:07:35 +0200 | [diff] [blame] | 1034 | static int omap8250_no_handle_irq(struct uart_port *port) |
| 1035 | { |
| 1036 | /* IRQ has not been requested but handling irq? */ |
| 1037 | WARN_ONCE(1, "Unexpected irq handling before port startup\n"); |
| 1038 | return 0; |
| 1039 | } |
| 1040 | |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 1041 | static int omap8250_probe(struct platform_device *pdev) |
| 1042 | { |
| 1043 | struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1044 | struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 1045 | struct omap8250_priv *priv; |
| 1046 | struct uart_8250_port up; |
| 1047 | int ret; |
| 1048 | void __iomem *membase; |
| 1049 | |
| 1050 | if (!regs || !irq) { |
| 1051 | dev_err(&pdev->dev, "missing registers or irq\n"); |
| 1052 | return -EINVAL; |
| 1053 | } |
| 1054 | |
| 1055 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
| 1056 | if (!priv) |
| 1057 | return -ENOMEM; |
| 1058 | |
| 1059 | membase = devm_ioremap_nocache(&pdev->dev, regs->start, |
| 1060 | resource_size(regs)); |
| 1061 | if (!membase) |
| 1062 | return -ENODEV; |
| 1063 | |
| 1064 | memset(&up, 0, sizeof(up)); |
| 1065 | up.port.dev = &pdev->dev; |
| 1066 | up.port.mapbase = regs->start; |
| 1067 | up.port.membase = membase; |
| 1068 | up.port.irq = irq->start; |
| 1069 | /* |
| 1070 | * It claims to be 16C750 compatible however it is a little different. |
| 1071 | * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to |
| 1072 | * have) is enabled via EFR instead of MCR. The type is set here 8250 |
| 1073 | * just to get things going. UNKNOWN does not work for a few reasons and |
| 1074 | * we don't need our own type since we don't use 8250's set_termios() |
| 1075 | * or pm callback. |
| 1076 | */ |
| 1077 | up.port.type = PORT_8250; |
| 1078 | up.port.iotype = UPIO_MEM; |
| 1079 | up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | |
| 1080 | UPF_HARD_FLOW; |
| 1081 | up.port.private_data = priv; |
| 1082 | |
| 1083 | up.port.regshift = 2; |
| 1084 | up.port.fifosize = 64; |
| 1085 | up.tx_loadsz = 64; |
| 1086 | up.capabilities = UART_CAP_FIFO; |
Rafael J. Wysocki | 71504e5 | 2014-12-19 15:27:58 +0100 | [diff] [blame] | 1087 | #ifdef CONFIG_PM |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 1088 | /* |
Rafael J. Wysocki | 71504e5 | 2014-12-19 15:27:58 +0100 | [diff] [blame] | 1089 | * Runtime PM is mostly transparent. However to do it right we need to a |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 1090 | * TX empty interrupt before we can put the device to auto idle. So if |
Rafael J. Wysocki | 71504e5 | 2014-12-19 15:27:58 +0100 | [diff] [blame] | 1091 | * PM is not enabled we don't add that flag and can spare that one extra |
| 1092 | * interrupt in the TX path. |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 1093 | */ |
| 1094 | up.capabilities |= UART_CAP_RPM; |
| 1095 | #endif |
| 1096 | up.port.set_termios = omap_8250_set_termios; |
Peter Hurley | 4bf4ea9 | 2014-12-30 20:28:15 -0500 | [diff] [blame] | 1097 | up.port.set_mctrl = omap8250_set_mctrl; |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 1098 | up.port.pm = omap_8250_pm; |
| 1099 | up.port.startup = omap_8250_startup; |
| 1100 | up.port.shutdown = omap_8250_shutdown; |
| 1101 | up.port.throttle = omap_8250_throttle; |
| 1102 | up.port.unthrottle = omap_8250_unthrottle; |
| 1103 | |
| 1104 | if (pdev->dev.of_node) { |
Sebastian Andrzej Siewior | 54178fe | 2014-11-12 10:28:33 +0100 | [diff] [blame] | 1105 | ret = of_alias_get_id(pdev->dev.of_node, "serial"); |
| 1106 | |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 1107 | of_property_read_u32(pdev->dev.of_node, "clock-frequency", |
| 1108 | &up.port.uartclk); |
| 1109 | priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1); |
| 1110 | } else { |
Sebastian Andrzej Siewior | 54178fe | 2014-11-12 10:28:33 +0100 | [diff] [blame] | 1111 | ret = pdev->id; |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 1112 | } |
Sebastian Andrzej Siewior | 54178fe | 2014-11-12 10:28:33 +0100 | [diff] [blame] | 1113 | if (ret < 0) { |
| 1114 | dev_err(&pdev->dev, "failed to get alias/pdev id\n"); |
| 1115 | return ret; |
| 1116 | } |
| 1117 | up.port.line = ret; |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 1118 | |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 1119 | if (!up.port.uartclk) { |
| 1120 | up.port.uartclk = DEFAULT_CLK_SPEED; |
| 1121 | dev_warn(&pdev->dev, |
| 1122 | "No clock speed specified: using default: %d\n", |
| 1123 | DEFAULT_CLK_SPEED); |
| 1124 | } |
| 1125 | |
| 1126 | priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; |
| 1127 | priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; |
| 1128 | pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY, |
| 1129 | priv->latency); |
| 1130 | INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); |
| 1131 | |
| 1132 | device_init_wakeup(&pdev->dev, true); |
| 1133 | pm_runtime_use_autosuspend(&pdev->dev); |
| 1134 | pm_runtime_set_autosuspend_delay(&pdev->dev, -1); |
| 1135 | |
| 1136 | pm_runtime_irq_safe(&pdev->dev); |
| 1137 | pm_runtime_enable(&pdev->dev); |
| 1138 | |
| 1139 | pm_runtime_get_sync(&pdev->dev); |
| 1140 | |
| 1141 | omap_serial_fill_features_erratas(&up, priv); |
Sebastian Andrzej Siewior | 9809889 | 2015-05-20 22:07:35 +0200 | [diff] [blame] | 1142 | up.port.handle_irq = omap8250_no_handle_irq; |
Sebastian Andrzej Siewior | 0a0661d | 2014-09-29 20:06:49 +0200 | [diff] [blame] | 1143 | #ifdef CONFIG_SERIAL_8250_DMA |
| 1144 | if (pdev->dev.of_node) { |
| 1145 | /* |
| 1146 | * Oh DMA support. If there are no DMA properties in the DT then |
| 1147 | * we will fall back to a generic DMA channel which does not |
| 1148 | * really work here. To ensure that we do not get a generic DMA |
| 1149 | * channel assigned, we have the the_no_dma_filter_fn() here. |
| 1150 | * To avoid "failed to request DMA" messages we check for DMA |
| 1151 | * properties in DT. |
| 1152 | */ |
| 1153 | ret = of_property_count_strings(pdev->dev.of_node, "dma-names"); |
| 1154 | if (ret == 2) { |
| 1155 | up.dma = &priv->omap8250_dma; |
Sebastian Andrzej Siewior | 0a0661d | 2014-09-29 20:06:49 +0200 | [diff] [blame] | 1156 | priv->omap8250_dma.fn = the_no_dma_filter_fn; |
| 1157 | priv->omap8250_dma.tx_dma = omap_8250_tx_dma; |
| 1158 | priv->omap8250_dma.rx_dma = omap_8250_rx_dma; |
| 1159 | priv->omap8250_dma.rx_size = RX_TRIGGER; |
| 1160 | priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER; |
| 1161 | priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER; |
| 1162 | |
| 1163 | if (of_machine_is_compatible("ti,am33xx")) |
| 1164 | priv->habit |= OMAP_DMA_TX_KICK; |
| 1165 | } |
| 1166 | } |
| 1167 | #endif |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 1168 | ret = serial8250_register_8250_port(&up); |
| 1169 | if (ret < 0) { |
| 1170 | dev_err(&pdev->dev, "unable to register 8250 port\n"); |
| 1171 | goto err; |
| 1172 | } |
| 1173 | priv->line = ret; |
| 1174 | platform_set_drvdata(pdev, priv); |
| 1175 | pm_runtime_mark_last_busy(&pdev->dev); |
| 1176 | pm_runtime_put_autosuspend(&pdev->dev); |
| 1177 | return 0; |
| 1178 | err: |
| 1179 | pm_runtime_put(&pdev->dev); |
| 1180 | pm_runtime_disable(&pdev->dev); |
| 1181 | return ret; |
| 1182 | } |
| 1183 | |
| 1184 | static int omap8250_remove(struct platform_device *pdev) |
| 1185 | { |
| 1186 | struct omap8250_priv *priv = platform_get_drvdata(pdev); |
| 1187 | |
| 1188 | pm_runtime_put_sync(&pdev->dev); |
| 1189 | pm_runtime_disable(&pdev->dev); |
| 1190 | serial8250_unregister_port(priv->line); |
| 1191 | pm_qos_remove_request(&priv->pm_qos_request); |
| 1192 | device_init_wakeup(&pdev->dev, false); |
| 1193 | return 0; |
| 1194 | } |
| 1195 | |
Rafael J. Wysocki | 71504e5 | 2014-12-19 15:27:58 +0100 | [diff] [blame] | 1196 | #ifdef CONFIG_PM |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 1197 | |
| 1198 | static inline void omap8250_enable_wakeirq(struct omap8250_priv *priv, |
| 1199 | bool enable) |
| 1200 | { |
| 1201 | if (!priv->wakeirq) |
| 1202 | return; |
| 1203 | |
| 1204 | if (enable) |
| 1205 | enable_irq(priv->wakeirq); |
| 1206 | else |
| 1207 | disable_irq_nosync(priv->wakeirq); |
| 1208 | } |
| 1209 | |
| 1210 | static void omap8250_enable_wakeup(struct omap8250_priv *priv, |
| 1211 | bool enable) |
| 1212 | { |
| 1213 | if (enable == priv->wakeups_enabled) |
| 1214 | return; |
| 1215 | |
| 1216 | omap8250_enable_wakeirq(priv, enable); |
| 1217 | priv->wakeups_enabled = enable; |
| 1218 | } |
| 1219 | #endif |
| 1220 | |
| 1221 | #ifdef CONFIG_PM_SLEEP |
| 1222 | static int omap8250_prepare(struct device *dev) |
| 1223 | { |
| 1224 | struct omap8250_priv *priv = dev_get_drvdata(dev); |
| 1225 | |
| 1226 | if (!priv) |
| 1227 | return 0; |
| 1228 | priv->is_suspending = true; |
| 1229 | return 0; |
| 1230 | } |
| 1231 | |
| 1232 | static void omap8250_complete(struct device *dev) |
| 1233 | { |
| 1234 | struct omap8250_priv *priv = dev_get_drvdata(dev); |
| 1235 | |
| 1236 | if (!priv) |
| 1237 | return; |
| 1238 | priv->is_suspending = false; |
| 1239 | } |
| 1240 | |
| 1241 | static int omap8250_suspend(struct device *dev) |
| 1242 | { |
| 1243 | struct omap8250_priv *priv = dev_get_drvdata(dev); |
| 1244 | |
| 1245 | serial8250_suspend_port(priv->line); |
| 1246 | flush_work(&priv->qos_work); |
| 1247 | |
| 1248 | if (device_may_wakeup(dev)) |
| 1249 | omap8250_enable_wakeup(priv, true); |
| 1250 | else |
| 1251 | omap8250_enable_wakeup(priv, false); |
| 1252 | return 0; |
| 1253 | } |
| 1254 | |
| 1255 | static int omap8250_resume(struct device *dev) |
| 1256 | { |
| 1257 | struct omap8250_priv *priv = dev_get_drvdata(dev); |
| 1258 | |
| 1259 | if (device_may_wakeup(dev)) |
| 1260 | omap8250_enable_wakeup(priv, false); |
| 1261 | |
| 1262 | serial8250_resume_port(priv->line); |
| 1263 | return 0; |
| 1264 | } |
| 1265 | #else |
| 1266 | #define omap8250_prepare NULL |
| 1267 | #define omap8250_complete NULL |
| 1268 | #endif |
| 1269 | |
Rafael J. Wysocki | 71504e5 | 2014-12-19 15:27:58 +0100 | [diff] [blame] | 1270 | #ifdef CONFIG_PM |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 1271 | static int omap8250_lost_context(struct uart_8250_port *up) |
| 1272 | { |
| 1273 | u32 val; |
| 1274 | |
| 1275 | val = serial_in(up, UART_OMAP_MDR1); |
| 1276 | /* |
| 1277 | * If we lose context, then MDR1 is set to its reset value which is |
| 1278 | * UART_OMAP_MDR1_DISABLE. After set_termios() we set it either to 13x |
| 1279 | * or 16x but never to disable again. |
| 1280 | */ |
| 1281 | if (val == UART_OMAP_MDR1_DISABLE) |
| 1282 | return 1; |
| 1283 | return 0; |
| 1284 | } |
| 1285 | |
| 1286 | static int omap8250_runtime_suspend(struct device *dev) |
| 1287 | { |
| 1288 | struct omap8250_priv *priv = dev_get_drvdata(dev); |
| 1289 | struct uart_8250_port *up; |
| 1290 | |
| 1291 | up = serial8250_get_port(priv->line); |
| 1292 | /* |
| 1293 | * When using 'no_console_suspend', the console UART must not be |
| 1294 | * suspended. Since driver suspend is managed by runtime suspend, |
| 1295 | * preventing runtime suspend (by returning error) will keep device |
| 1296 | * active during suspend. |
| 1297 | */ |
| 1298 | if (priv->is_suspending && !console_suspend_enabled) { |
| 1299 | if (uart_console(&up->port)) |
| 1300 | return -EBUSY; |
| 1301 | } |
| 1302 | |
| 1303 | omap8250_enable_wakeup(priv, true); |
Sebastian Andrzej Siewior | 0a0661d | 2014-09-29 20:06:49 +0200 | [diff] [blame] | 1304 | if (up->dma) |
| 1305 | omap_8250_rx_dma(up, UART_IIR_RX_TIMEOUT); |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 1306 | |
| 1307 | priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; |
| 1308 | schedule_work(&priv->qos_work); |
| 1309 | |
| 1310 | return 0; |
| 1311 | } |
| 1312 | |
| 1313 | static int omap8250_runtime_resume(struct device *dev) |
| 1314 | { |
| 1315 | struct omap8250_priv *priv = dev_get_drvdata(dev); |
| 1316 | struct uart_8250_port *up; |
| 1317 | int loss_cntx; |
| 1318 | |
| 1319 | /* In case runtime-pm tries this before we are setup */ |
| 1320 | if (!priv) |
| 1321 | return 0; |
| 1322 | |
| 1323 | up = serial8250_get_port(priv->line); |
| 1324 | omap8250_enable_wakeup(priv, false); |
| 1325 | loss_cntx = omap8250_lost_context(up); |
| 1326 | |
| 1327 | if (loss_cntx) |
| 1328 | omap8250_restore_regs(up); |
| 1329 | |
Sebastian Andrzej Siewior | 0a0661d | 2014-09-29 20:06:49 +0200 | [diff] [blame] | 1330 | if (up->dma) |
| 1331 | omap_8250_rx_dma(up, 0); |
| 1332 | |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 1333 | priv->latency = priv->calc_latency; |
| 1334 | schedule_work(&priv->qos_work); |
| 1335 | return 0; |
| 1336 | } |
| 1337 | #endif |
| 1338 | |
Sebastian Andrzej Siewior | 00648d0 | 2014-12-18 18:47:12 +0100 | [diff] [blame] | 1339 | #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP |
| 1340 | static int __init omap8250_console_fixup(void) |
| 1341 | { |
| 1342 | char *omap_str; |
| 1343 | char *options; |
| 1344 | u8 idx; |
| 1345 | |
| 1346 | if (strstr(boot_command_line, "console=ttyS")) |
| 1347 | /* user set a ttyS based name for the console */ |
| 1348 | return 0; |
| 1349 | |
| 1350 | omap_str = strstr(boot_command_line, "console=ttyO"); |
| 1351 | if (!omap_str) |
| 1352 | /* user did not set ttyO based console, so we don't care */ |
| 1353 | return 0; |
| 1354 | |
| 1355 | omap_str += 12; |
| 1356 | if ('0' <= *omap_str && *omap_str <= '9') |
| 1357 | idx = *omap_str - '0'; |
| 1358 | else |
| 1359 | return 0; |
| 1360 | |
| 1361 | omap_str++; |
| 1362 | if (omap_str[0] == ',') { |
| 1363 | omap_str++; |
| 1364 | options = omap_str; |
| 1365 | } else { |
| 1366 | options = NULL; |
| 1367 | } |
| 1368 | |
| 1369 | add_preferred_console("ttyS", idx, options); |
| 1370 | pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", |
| 1371 | idx, idx); |
| 1372 | pr_err("This ensures that you still see kernel messages. Please\n"); |
| 1373 | pr_err("update your kernel commandline.\n"); |
| 1374 | return 0; |
| 1375 | } |
| 1376 | console_initcall(omap8250_console_fixup); |
| 1377 | #endif |
| 1378 | |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 1379 | static const struct dev_pm_ops omap8250_dev_pm_ops = { |
| 1380 | SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) |
| 1381 | SET_RUNTIME_PM_OPS(omap8250_runtime_suspend, |
| 1382 | omap8250_runtime_resume, NULL) |
| 1383 | .prepare = omap8250_prepare, |
| 1384 | .complete = omap8250_complete, |
| 1385 | }; |
| 1386 | |
| 1387 | static const struct of_device_id omap8250_dt_ids[] = { |
| 1388 | { .compatible = "ti,omap2-uart" }, |
| 1389 | { .compatible = "ti,omap3-uart" }, |
| 1390 | { .compatible = "ti,omap4-uart" }, |
| 1391 | {}, |
| 1392 | }; |
| 1393 | MODULE_DEVICE_TABLE(of, omap8250_dt_ids); |
| 1394 | |
| 1395 | static struct platform_driver omap8250_platform_driver = { |
| 1396 | .driver = { |
| 1397 | .name = "omap8250", |
| 1398 | .pm = &omap8250_dev_pm_ops, |
| 1399 | .of_match_table = omap8250_dt_ids, |
Sebastian Andrzej Siewior | 61929cf | 2014-09-29 20:06:39 +0200 | [diff] [blame] | 1400 | }, |
| 1401 | .probe = omap8250_probe, |
| 1402 | .remove = omap8250_remove, |
| 1403 | }; |
| 1404 | module_platform_driver(omap8250_platform_driver); |
| 1405 | |
| 1406 | MODULE_AUTHOR("Sebastian Andrzej Siewior"); |
| 1407 | MODULE_DESCRIPTION("OMAP 8250 Driver"); |
| 1408 | MODULE_LICENSE("GPL v2"); |