Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-kirkwood/include/mach/bridge-regs.h |
| 3 | * |
| 4 | * Mbus-L to Mbus Bridge Registers |
| 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public |
| 7 | * License version 2. This program is licensed "as is" without any |
| 8 | * warranty of any kind, whether express or implied. |
| 9 | */ |
| 10 | |
| 11 | #ifndef __ASM_ARCH_BRIDGE_REGS_H |
| 12 | #define __ASM_ARCH_BRIDGE_REGS_H |
| 13 | |
| 14 | #include <mach/kirkwood.h> |
| 15 | |
Thomas Petazzoni | 40306c8 | 2012-09-11 14:27:15 +0200 | [diff] [blame] | 16 | #define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0100) |
Lennert Buytenhek | 2bf3010 | 2009-11-12 20:31:14 +0100 | [diff] [blame] | 17 | #define CPU_CONFIG_ERROR_PROP 0x00000004 |
| 18 | |
Thomas Petazzoni | 40306c8 | 2012-09-11 14:27:15 +0200 | [diff] [blame] | 19 | #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) |
Andrew Lunn | 0e2ee0c | 2013-01-27 11:07:23 +0100 | [diff] [blame] | 20 | #define CPU_CONTROL_PHYS (BRIDGE_PHYS_BASE + 0x0104) |
Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 21 | #define CPU_RESET 0x00000002 |
| 22 | |
Thomas Petazzoni | 40306c8 | 2012-09-11 14:27:15 +0200 | [diff] [blame] | 23 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) |
Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 24 | #define SOFT_RESET_OUT_EN 0x00000004 |
| 25 | |
Thomas Petazzoni | 40306c8 | 2012-09-11 14:27:15 +0200 | [diff] [blame] | 26 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) |
Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 27 | #define SOFT_RESET 0x00000001 |
| 28 | |
Thomas Petazzoni | 40306c8 | 2012-09-11 14:27:15 +0200 | [diff] [blame] | 29 | #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110) |
Thomas Reitmayr | 054bd3f0 | 2009-06-01 13:38:34 +0200 | [diff] [blame] | 30 | |
Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 31 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) |
| 32 | |
Thomas Petazzoni | 40306c8 | 2012-09-11 14:27:15 +0200 | [diff] [blame] | 33 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) |
Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 34 | #define IRQ_CAUSE_LOW_OFF 0x0000 |
| 35 | #define IRQ_MASK_LOW_OFF 0x0004 |
| 36 | #define IRQ_CAUSE_HIGH_OFF 0x0010 |
| 37 | #define IRQ_MASK_HIGH_OFF 0x0014 |
| 38 | |
Thomas Petazzoni | 40306c8 | 2012-09-11 14:27:15 +0200 | [diff] [blame] | 39 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) |
| 40 | #define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) |
Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 41 | |
Thomas Petazzoni | 40306c8 | 2012-09-11 14:27:15 +0200 | [diff] [blame] | 42 | #define L2_CONFIG_REG (BRIDGE_VIRT_BASE + 0x0128) |
Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 43 | #define L2_WRITETHROUGH 0x00000010 |
| 44 | |
Thomas Petazzoni | 40306c8 | 2012-09-11 14:27:15 +0200 | [diff] [blame] | 45 | #define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE + 0x11c) |
Andrew Lunn | 2f129bf | 2011-12-15 08:15:07 +0100 | [diff] [blame] | 46 | #define CGC_BIT_GE0 (0) |
| 47 | #define CGC_BIT_PEX0 (2) |
| 48 | #define CGC_BIT_USB0 (3) |
| 49 | #define CGC_BIT_SDIO (4) |
| 50 | #define CGC_BIT_TSU (5) |
| 51 | #define CGC_BIT_DUNIT (6) |
| 52 | #define CGC_BIT_RUNIT (7) |
| 53 | #define CGC_BIT_XOR0 (8) |
| 54 | #define CGC_BIT_AUDIO (9) |
| 55 | #define CGC_BIT_SATA0 (14) |
| 56 | #define CGC_BIT_SATA1 (15) |
| 57 | #define CGC_BIT_XOR1 (16) |
| 58 | #define CGC_BIT_CRYPTO (17) |
| 59 | #define CGC_BIT_PEX1 (18) |
| 60 | #define CGC_BIT_GE1 (19) |
| 61 | #define CGC_BIT_TDM (20) |
Rabeeh Khoury | e8b2b7b | 2009-03-22 17:30:32 +0200 | [diff] [blame] | 62 | #define CGC_GE0 (1 << 0) |
| 63 | #define CGC_PEX0 (1 << 2) |
| 64 | #define CGC_USB0 (1 << 3) |
| 65 | #define CGC_SDIO (1 << 4) |
| 66 | #define CGC_TSU (1 << 5) |
| 67 | #define CGC_DUNIT (1 << 6) |
| 68 | #define CGC_RUNIT (1 << 7) |
| 69 | #define CGC_XOR0 (1 << 8) |
| 70 | #define CGC_AUDIO (1 << 9) |
Andrew Lunn | 0e2ee0c | 2013-01-27 11:07:23 +0100 | [diff] [blame] | 71 | #define CGC_POWERSAVE (1 << 11) |
Rabeeh Khoury | e8b2b7b | 2009-03-22 17:30:32 +0200 | [diff] [blame] | 72 | #define CGC_SATA0 (1 << 14) |
| 73 | #define CGC_SATA1 (1 << 15) |
| 74 | #define CGC_XOR1 (1 << 16) |
| 75 | #define CGC_CRYPTO (1 << 17) |
Saeed Bishara | ffd58bd | 2010-06-08 14:21:34 +0300 | [diff] [blame] | 76 | #define CGC_PEX1 (1 << 18) |
Rabeeh Khoury | e8b2b7b | 2009-03-22 17:30:32 +0200 | [diff] [blame] | 77 | #define CGC_GE1 (1 << 19) |
| 78 | #define CGC_TDM (1 << 20) |
Saeed Bishara | ffd58bd | 2010-06-08 14:21:34 +0300 | [diff] [blame] | 79 | #define CGC_RESERVED (0x6 << 21) |
Rabeeh Khoury | e8b2b7b | 2009-03-22 17:30:32 +0200 | [diff] [blame] | 80 | |
Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 81 | #endif |