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Nicolas Pitrefdd8b072009-04-22 20:08:17 +01001/*
2 * arch/arm/mach-kirkwood/include/mach/bridge-regs.h
3 *
4 * Mbus-L to Mbus Bridge Registers
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_BRIDGE_REGS_H
12#define __ASM_ARCH_BRIDGE_REGS_H
13
14#include <mach/kirkwood.h>
15
Thomas Petazzoni40306c82012-09-11 14:27:15 +020016#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0100)
Lennert Buytenhek2bf30102009-11-12 20:31:14 +010017#define CPU_CONFIG_ERROR_PROP 0x00000004
18
Thomas Petazzoni40306c82012-09-11 14:27:15 +020019#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
Andrew Lunn0e2ee0c2013-01-27 11:07:23 +010020#define CPU_CONTROL_PHYS (BRIDGE_PHYS_BASE + 0x0104)
Nicolas Pitrefdd8b072009-04-22 20:08:17 +010021#define CPU_RESET 0x00000002
22
Thomas Petazzoni40306c82012-09-11 14:27:15 +020023#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
Nicolas Pitrefdd8b072009-04-22 20:08:17 +010024#define SOFT_RESET_OUT_EN 0x00000004
25
Thomas Petazzoni40306c82012-09-11 14:27:15 +020026#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
Nicolas Pitrefdd8b072009-04-22 20:08:17 +010027#define SOFT_RESET 0x00000001
28
Thomas Petazzoni40306c82012-09-11 14:27:15 +020029#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110)
Thomas Reitmayr054bd3f02009-06-01 13:38:34 +020030
Nicolas Pitrefdd8b072009-04-22 20:08:17 +010031#define BRIDGE_INT_TIMER1_CLR (~0x0004)
32
Thomas Petazzoni40306c82012-09-11 14:27:15 +020033#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
Nicolas Pitrefdd8b072009-04-22 20:08:17 +010034#define IRQ_CAUSE_LOW_OFF 0x0000
35#define IRQ_MASK_LOW_OFF 0x0004
36#define IRQ_CAUSE_HIGH_OFF 0x0010
37#define IRQ_MASK_HIGH_OFF 0x0014
38
Thomas Petazzoni40306c82012-09-11 14:27:15 +020039#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
40#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
Nicolas Pitrefdd8b072009-04-22 20:08:17 +010041
Thomas Petazzoni40306c82012-09-11 14:27:15 +020042#define L2_CONFIG_REG (BRIDGE_VIRT_BASE + 0x0128)
Nicolas Pitrefdd8b072009-04-22 20:08:17 +010043#define L2_WRITETHROUGH 0x00000010
44
Thomas Petazzoni40306c82012-09-11 14:27:15 +020045#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE + 0x11c)
Andrew Lunn2f129bf2011-12-15 08:15:07 +010046#define CGC_BIT_GE0 (0)
47#define CGC_BIT_PEX0 (2)
48#define CGC_BIT_USB0 (3)
49#define CGC_BIT_SDIO (4)
50#define CGC_BIT_TSU (5)
51#define CGC_BIT_DUNIT (6)
52#define CGC_BIT_RUNIT (7)
53#define CGC_BIT_XOR0 (8)
54#define CGC_BIT_AUDIO (9)
55#define CGC_BIT_SATA0 (14)
56#define CGC_BIT_SATA1 (15)
57#define CGC_BIT_XOR1 (16)
58#define CGC_BIT_CRYPTO (17)
59#define CGC_BIT_PEX1 (18)
60#define CGC_BIT_GE1 (19)
61#define CGC_BIT_TDM (20)
Rabeeh Khourye8b2b7b2009-03-22 17:30:32 +020062#define CGC_GE0 (1 << 0)
63#define CGC_PEX0 (1 << 2)
64#define CGC_USB0 (1 << 3)
65#define CGC_SDIO (1 << 4)
66#define CGC_TSU (1 << 5)
67#define CGC_DUNIT (1 << 6)
68#define CGC_RUNIT (1 << 7)
69#define CGC_XOR0 (1 << 8)
70#define CGC_AUDIO (1 << 9)
Andrew Lunn0e2ee0c2013-01-27 11:07:23 +010071#define CGC_POWERSAVE (1 << 11)
Rabeeh Khourye8b2b7b2009-03-22 17:30:32 +020072#define CGC_SATA0 (1 << 14)
73#define CGC_SATA1 (1 << 15)
74#define CGC_XOR1 (1 << 16)
75#define CGC_CRYPTO (1 << 17)
Saeed Bisharaffd58bd2010-06-08 14:21:34 +030076#define CGC_PEX1 (1 << 18)
Rabeeh Khourye8b2b7b2009-03-22 17:30:32 +020077#define CGC_GE1 (1 << 19)
78#define CGC_TDM (1 << 20)
Saeed Bisharaffd58bd2010-06-08 14:21:34 +030079#define CGC_RESERVED (0x6 << 21)
Rabeeh Khourye8b2b7b2009-03-22 17:30:32 +020080
Nicolas Pitrefdd8b072009-04-22 20:08:17 +010081#endif