blob: a670c006982e5056e418f81aaec1d439a589a7ae [file] [log] [blame]
Daniel Vetter02e792f2009-09-15 22:57:34 +02001/*
2 * Copyright © 2009
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel@ffwll.ch>
25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */
Andrew Mortone1679762010-08-24 16:35:52 -070028
29#include <linux/seq_file.h>
Daniel Vetter02e792f2009-09-15 22:57:34 +020030#include "drmP.h"
31#include "drm.h"
32#include "i915_drm.h"
33#include "i915_drv.h"
34#include "i915_reg.h"
35#include "intel_drv.h"
36
37/* Limits for overlay size. According to intel doc, the real limits are:
38 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
39 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
40 * the mininum of both. */
41#define IMAGE_MAX_WIDTH 2048
42#define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
43/* on 830 and 845 these large limits result in the card hanging */
44#define IMAGE_MAX_WIDTH_LEGACY 1024
45#define IMAGE_MAX_HEIGHT_LEGACY 1088
46
47/* overlay register definitions */
48/* OCMD register */
49#define OCMD_TILED_SURFACE (0x1<<19)
50#define OCMD_MIRROR_MASK (0x3<<17)
51#define OCMD_MIRROR_MODE (0x3<<17)
52#define OCMD_MIRROR_HORIZONTAL (0x1<<17)
53#define OCMD_MIRROR_VERTICAL (0x2<<17)
54#define OCMD_MIRROR_BOTH (0x3<<17)
55#define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
56#define OCMD_UV_SWAP (0x1<<14) /* YVYU */
57#define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
58#define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
59#define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
60#define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
61#define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
62#define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
63#define OCMD_YUV_422_PACKED (0x8<<10)
64#define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
65#define OCMD_YUV_420_PLANAR (0xc<<10)
66#define OCMD_YUV_422_PLANAR (0xd<<10)
67#define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
68#define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
69#define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
Chris Wilsond7961362010-07-13 13:52:17 +010070#define OCMD_BUF_TYPE_MASK (0x1<<5)
Daniel Vetter02e792f2009-09-15 22:57:34 +020071#define OCMD_BUF_TYPE_FRAME (0x0<<5)
72#define OCMD_BUF_TYPE_FIELD (0x1<<5)
73#define OCMD_TEST_MODE (0x1<<4)
74#define OCMD_BUFFER_SELECT (0x3<<2)
75#define OCMD_BUFFER0 (0x0<<2)
76#define OCMD_BUFFER1 (0x1<<2)
77#define OCMD_FIELD_SELECT (0x1<<2)
78#define OCMD_FIELD0 (0x0<<1)
79#define OCMD_FIELD1 (0x1<<1)
80#define OCMD_ENABLE (0x1<<0)
81
82/* OCONFIG register */
83#define OCONF_PIPE_MASK (0x1<<18)
84#define OCONF_PIPE_A (0x0<<18)
85#define OCONF_PIPE_B (0x1<<18)
86#define OCONF_GAMMA2_ENABLE (0x1<<16)
87#define OCONF_CSC_MODE_BT601 (0x0<<5)
88#define OCONF_CSC_MODE_BT709 (0x1<<5)
89#define OCONF_CSC_BYPASS (0x1<<4)
90#define OCONF_CC_OUT_8BIT (0x1<<3)
91#define OCONF_TEST_MODE (0x1<<2)
92#define OCONF_THREE_LINE_BUFFER (0x1<<0)
93#define OCONF_TWO_LINE_BUFFER (0x0<<0)
94
95/* DCLRKM (dst-key) register */
96#define DST_KEY_ENABLE (0x1<<31)
97#define CLK_RGB24_MASK 0x0
98#define CLK_RGB16_MASK 0x070307
99#define CLK_RGB15_MASK 0x070707
100#define CLK_RGB8I_MASK 0xffffff
101
102#define RGB16_TO_COLORKEY(c) \
103 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
104#define RGB15_TO_COLORKEY(c) \
105 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
106
107/* overlay flip addr flag */
108#define OFC_UPDATE 0x1
109
110/* polyphase filter coefficients */
111#define N_HORIZ_Y_TAPS 5
112#define N_VERT_Y_TAPS 3
113#define N_HORIZ_UV_TAPS 3
114#define N_VERT_UV_TAPS 3
115#define N_PHASES 17
116#define MAX_TAPS 5
117
118/* memory bufferd overlay registers */
119struct overlay_registers {
120 u32 OBUF_0Y;
121 u32 OBUF_1Y;
122 u32 OBUF_0U;
123 u32 OBUF_0V;
124 u32 OBUF_1U;
125 u32 OBUF_1V;
126 u32 OSTRIDE;
127 u32 YRGB_VPH;
128 u32 UV_VPH;
129 u32 HORZ_PH;
130 u32 INIT_PHS;
131 u32 DWINPOS;
132 u32 DWINSZ;
133 u32 SWIDTH;
134 u32 SWIDTHSW;
135 u32 SHEIGHT;
136 u32 YRGBSCALE;
137 u32 UVSCALE;
138 u32 OCLRC0;
139 u32 OCLRC1;
140 u32 DCLRKV;
141 u32 DCLRKM;
142 u32 SCLRKVH;
143 u32 SCLRKVL;
144 u32 SCLRKEN;
145 u32 OCONFIG;
146 u32 OCMD;
147 u32 RESERVED1; /* 0x6C */
148 u32 OSTART_0Y;
149 u32 OSTART_1Y;
150 u32 OSTART_0U;
151 u32 OSTART_0V;
152 u32 OSTART_1U;
153 u32 OSTART_1V;
154 u32 OTILEOFF_0Y;
155 u32 OTILEOFF_1Y;
156 u32 OTILEOFF_0U;
157 u32 OTILEOFF_0V;
158 u32 OTILEOFF_1U;
159 u32 OTILEOFF_1V;
160 u32 FASTHSCALE; /* 0xA0 */
161 u32 UVSCALEV; /* 0xA4 */
162 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
163 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
164 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
165 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
166 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
167 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
168 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
169 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
170 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
171};
172
Chris Wilson23f09ce2010-08-12 13:53:37 +0100173struct intel_overlay {
174 struct drm_device *dev;
175 struct intel_crtc *crtc;
176 struct drm_i915_gem_object *vid_bo;
177 struct drm_i915_gem_object *old_vid_bo;
178 int active;
179 int pfit_active;
180 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
181 u32 color_key;
182 u32 brightness, contrast, saturation;
183 u32 old_xscale, old_yscale;
184 /* register access */
185 u32 flip_addr;
186 struct drm_i915_gem_object *reg_bo;
187 /* flip handling */
188 uint32_t last_flip_req;
Chris Wilsonb303cf92010-08-12 14:03:48 +0100189 void (*flip_tail)(struct intel_overlay *);
Chris Wilson23f09ce2010-08-12 13:53:37 +0100190};
Daniel Vetter02e792f2009-09-15 22:57:34 +0200191
Chris Wilson8d74f652010-08-12 10:35:26 +0100192static struct overlay_registers *
Chris Wilson8d74f652010-08-12 10:35:26 +0100193intel_overlay_map_regs(struct intel_overlay *overlay)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200194{
195 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
196 struct overlay_registers *regs;
197
Chris Wilson9bb2ff72010-08-12 12:02:11 +0100198 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
Daniel Vetter02e792f2009-09-15 22:57:34 +0200199 regs = overlay->reg_bo->phys_obj->handle->vaddr;
Chris Wilson9bb2ff72010-08-12 12:02:11 +0100200 else
Chris Wilson8d74f652010-08-12 10:35:26 +0100201 regs = io_mapping_map_wc(dev_priv->mm.gtt_mapping,
202 overlay->reg_bo->gtt_offset);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200203
Chris Wilson9bb2ff72010-08-12 12:02:11 +0100204 return regs;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200205}
206
Chris Wilson9bb2ff72010-08-12 12:02:11 +0100207static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
208 struct overlay_registers *regs)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200209{
Chris Wilson8d74f652010-08-12 10:35:26 +0100210 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
Chris Wilson9bb2ff72010-08-12 12:02:11 +0100211 io_mapping_unmap(regs);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200212}
Daniel Vetter02e792f2009-09-15 22:57:34 +0200213
Chris Wilsonb6c028e2010-08-12 11:55:08 +0100214static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
Chris Wilson8dc5d142010-08-12 12:36:12 +0100215 struct drm_i915_gem_request *request,
Chris Wilsonb303cf92010-08-12 14:03:48 +0100216 void (*tail)(struct intel_overlay *))
Chris Wilsonb6c028e2010-08-12 11:55:08 +0100217{
218 struct drm_device *dev = overlay->dev;
219 drm_i915_private_t *dev_priv = dev->dev_private;
220 int ret;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200221
Chris Wilsonb303cf92010-08-12 14:03:48 +0100222 BUG_ON(overlay->last_flip_req);
Chris Wilsondb53a302011-02-03 11:57:46 +0000223 ret = i915_add_request(LP_RING(dev_priv), NULL, request);
Chris Wilson3cce4692010-10-27 16:11:02 +0100224 if (ret) {
225 kfree(request);
226 return ret;
227 }
228 overlay->last_flip_req = request->seqno;
Chris Wilsonb303cf92010-08-12 14:03:48 +0100229 overlay->flip_tail = tail;
Chris Wilsonce453d82011-02-21 14:43:56 +0000230 ret = i915_wait_request(LP_RING(dev_priv), overlay->last_flip_req);
Chris Wilsonb6c028e2010-08-12 11:55:08 +0100231 if (ret)
232 return ret;
233
Chris Wilsonb6c028e2010-08-12 11:55:08 +0100234 overlay->last_flip_req = 0;
235 return 0;
236}
237
Chris Wilson106dada2010-07-16 17:13:01 +0100238/* Workaround for i830 bug where pipe a must be enable to change control regs */
239static int
240i830_activate_pipe_a(struct drm_device *dev)
241{
242 drm_i915_private_t *dev_priv = dev->dev_private;
243 struct intel_crtc *crtc;
244 struct drm_crtc_helper_funcs *crtc_funcs;
245 struct drm_display_mode vesa_640x480 = {
246 DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
247 752, 800, 0, 480, 489, 492, 525, 0,
248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)
249 }, *mode;
250
251 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[0]);
252 if (crtc->dpms_mode == DRM_MODE_DPMS_ON)
253 return 0;
254
255 /* most i8xx have pipe a forced on, so don't trust dpms mode */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800256 if (I915_READ(_PIPEACONF) & PIPECONF_ENABLE)
Chris Wilson106dada2010-07-16 17:13:01 +0100257 return 0;
258
259 crtc_funcs = crtc->base.helper_private;
260 if (crtc_funcs->dpms == NULL)
261 return 0;
262
263 DRM_DEBUG_DRIVER("Enabling pipe A in order to enable overlay\n");
264
265 mode = drm_mode_duplicate(dev, &vesa_640x480);
266 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
267 if(!drm_crtc_helper_set_mode(&crtc->base, mode,
268 crtc->base.x, crtc->base.y,
269 crtc->base.fb))
270 return 0;
271
272 crtc_funcs->dpms(&crtc->base, DRM_MODE_DPMS_ON);
273 return 1;
274}
275
276static void
277i830_deactivate_pipe_a(struct drm_device *dev)
278{
279 drm_i915_private_t *dev_priv = dev->dev_private;
280 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[0];
281 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
282
283 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200284}
285
286/* overlay needs to be disable in OCMD reg */
287static int intel_overlay_on(struct intel_overlay *overlay)
288{
289 struct drm_device *dev = overlay->dev;
Chris Wilsone1f99ce2010-10-27 12:45:26 +0100290 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson8dc5d142010-08-12 12:36:12 +0100291 struct drm_i915_gem_request *request;
Chris Wilson106dada2010-07-16 17:13:01 +0100292 int pipe_a_quirk = 0;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200293 int ret;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200294
295 BUG_ON(overlay->active);
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200296 overlay->active = 1;
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200297
Chris Wilson106dada2010-07-16 17:13:01 +0100298 if (IS_I830(dev)) {
299 pipe_a_quirk = i830_activate_pipe_a(dev);
300 if (pipe_a_quirk < 0)
301 return pipe_a_quirk;
302 }
303
Chris Wilson8dc5d142010-08-12 12:36:12 +0100304 request = kzalloc(sizeof(*request), GFP_KERNEL);
Chris Wilson106dada2010-07-16 17:13:01 +0100305 if (request == NULL) {
306 ret = -ENOMEM;
307 goto out;
308 }
Daniel Vetter02e792f2009-09-15 22:57:34 +0200309
Chris Wilsone1f99ce2010-10-27 12:45:26 +0100310 ret = BEGIN_LP_RING(4);
311 if (ret) {
312 kfree(request);
313 goto out;
314 }
315
Daniel Vetter02e792f2009-09-15 22:57:34 +0200316 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
317 OUT_RING(overlay->flip_addr | OFC_UPDATE);
318 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
319 OUT_RING(MI_NOOP);
320 ADVANCE_LP_RING();
321
Chris Wilsonce453d82011-02-21 14:43:56 +0000322 ret = intel_overlay_do_wait_request(overlay, request, NULL);
Chris Wilson106dada2010-07-16 17:13:01 +0100323out:
324 if (pipe_a_quirk)
325 i830_deactivate_pipe_a(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200326
Chris Wilson106dada2010-07-16 17:13:01 +0100327 return ret;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200328}
329
330/* overlay needs to be enabled in OCMD reg */
Chris Wilson8dc5d142010-08-12 12:36:12 +0100331static int intel_overlay_continue(struct intel_overlay *overlay,
332 bool load_polyphase_filter)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200333{
334 struct drm_device *dev = overlay->dev;
335 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilson8dc5d142010-08-12 12:36:12 +0100336 struct drm_i915_gem_request *request;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200337 u32 flip_addr = overlay->flip_addr;
338 u32 tmp;
Chris Wilsone1f99ce2010-10-27 12:45:26 +0100339 int ret;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200340
341 BUG_ON(!overlay->active);
342
Chris Wilson8dc5d142010-08-12 12:36:12 +0100343 request = kzalloc(sizeof(*request), GFP_KERNEL);
344 if (request == NULL)
345 return -ENOMEM;
346
Daniel Vetter02e792f2009-09-15 22:57:34 +0200347 if (load_polyphase_filter)
348 flip_addr |= OFC_UPDATE;
349
350 /* check for underruns */
351 tmp = I915_READ(DOVSTA);
352 if (tmp & (1 << 17))
353 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
354
Chris Wilsone1f99ce2010-10-27 12:45:26 +0100355 ret = BEGIN_LP_RING(2);
356 if (ret) {
357 kfree(request);
358 return ret;
359 }
Daniel Vetter02e792f2009-09-15 22:57:34 +0200360 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
361 OUT_RING(flip_addr);
Daniel Vetter5a5a0c62009-09-15 22:57:36 +0200362 ADVANCE_LP_RING();
363
Chris Wilsondb53a302011-02-03 11:57:46 +0000364 ret = i915_add_request(LP_RING(dev_priv), NULL, request);
Chris Wilson3cce4692010-10-27 16:11:02 +0100365 if (ret) {
366 kfree(request);
367 return ret;
368 }
369
370 overlay->last_flip_req = request->seqno;
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200371 return 0;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200372}
373
Chris Wilsonb303cf92010-08-12 14:03:48 +0100374static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200375{
Chris Wilson05394f32010-11-08 19:18:58 +0000376 struct drm_i915_gem_object *obj = overlay->old_vid_bo;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200377
Chris Wilsonb303cf92010-08-12 14:03:48 +0100378 i915_gem_object_unpin(obj);
Chris Wilson05394f32010-11-08 19:18:58 +0000379 drm_gem_object_unreference(&obj->base);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200380
Chris Wilsonb303cf92010-08-12 14:03:48 +0100381 overlay->old_vid_bo = NULL;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200382}
383
Daniel Vetter12ca45f2037-04-25 10:08:26 +0200384static void intel_overlay_off_tail(struct intel_overlay *overlay)
385{
Chris Wilson05394f32010-11-08 19:18:58 +0000386 struct drm_i915_gem_object *obj = overlay->vid_bo;
Daniel Vetter12ca45f2037-04-25 10:08:26 +0200387
388 /* never have the overlay hw on without showing a frame */
389 BUG_ON(!overlay->vid_bo);
Daniel Vetter12ca45f2037-04-25 10:08:26 +0200390
391 i915_gem_object_unpin(obj);
Chris Wilson05394f32010-11-08 19:18:58 +0000392 drm_gem_object_unreference(&obj->base);
Daniel Vetter12ca45f2037-04-25 10:08:26 +0200393 overlay->vid_bo = NULL;
394
395 overlay->crtc->overlay = NULL;
396 overlay->crtc = NULL;
397 overlay->active = 0;
398}
399
Daniel Vetter02e792f2009-09-15 22:57:34 +0200400/* overlay needs to be disabled in OCMD reg */
Chris Wilsonce453d82011-02-21 14:43:56 +0000401static int intel_overlay_off(struct intel_overlay *overlay)
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200402{
403 struct drm_device *dev = overlay->dev;
Chris Wilsone1f99ce2010-10-27 12:45:26 +0100404 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson8dc5d142010-08-12 12:36:12 +0100405 u32 flip_addr = overlay->flip_addr;
406 struct drm_i915_gem_request *request;
Chris Wilsone1f99ce2010-10-27 12:45:26 +0100407 int ret;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200408
409 BUG_ON(!overlay->active);
410
Chris Wilson8dc5d142010-08-12 12:36:12 +0100411 request = kzalloc(sizeof(*request), GFP_KERNEL);
412 if (request == NULL)
413 return -ENOMEM;
414
Daniel Vetter02e792f2009-09-15 22:57:34 +0200415 /* According to intel docs the overlay hw may hang (when switching
416 * off) without loading the filter coeffs. It is however unclear whether
417 * this applies to the disabling of the overlay or to the switching off
418 * of the hw. Do it in both cases */
419 flip_addr |= OFC_UPDATE;
420
Chris Wilsone1f99ce2010-10-27 12:45:26 +0100421 ret = BEGIN_LP_RING(6);
422 if (ret) {
423 kfree(request);
424 return ret;
425 }
Daniel Vetter02e792f2009-09-15 22:57:34 +0200426 /* wait for overlay to go idle */
Daniel Vetter02e792f2009-09-15 22:57:34 +0200427 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
428 OUT_RING(flip_addr);
Chris Wilson722506f2010-08-12 09:28:50 +0100429 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
Chris Wilson722506f2010-08-12 09:28:50 +0100430 /* turn overlay off */
Chris Wilson722506f2010-08-12 09:28:50 +0100431 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
432 OUT_RING(flip_addr);
433 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
Chris Wilson722506f2010-08-12 09:28:50 +0100434 ADVANCE_LP_RING();
435
Chris Wilsonce453d82011-02-21 14:43:56 +0000436 return intel_overlay_do_wait_request(overlay, request,
Chris Wilsonb303cf92010-08-12 14:03:48 +0100437 intel_overlay_off_tail);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200438}
439
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200440/* recover from an interruption due to a signal
441 * We have to be careful not to repeat work forever an make forward progess. */
Chris Wilsonce453d82011-02-21 14:43:56 +0000442static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200443{
444 struct drm_device *dev = overlay->dev;
Zou Nan hai852835f2010-05-21 09:08:56 +0800445 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200446 int ret;
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200447
Chris Wilsonb303cf92010-08-12 14:03:48 +0100448 if (overlay->last_flip_req == 0)
449 return 0;
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200450
Chris Wilsonce453d82011-02-21 14:43:56 +0000451 ret = i915_wait_request(LP_RING(dev_priv), overlay->last_flip_req);
Chris Wilsonb6c028e2010-08-12 11:55:08 +0100452 if (ret)
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200453 return ret;
454
Chris Wilsonb303cf92010-08-12 14:03:48 +0100455 if (overlay->flip_tail)
456 overlay->flip_tail(overlay);
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200457
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200458 overlay->last_flip_req = 0;
459 return 0;
460}
461
Daniel Vetter5a5a0c62009-09-15 22:57:36 +0200462/* Wait for pending overlay flip and release old frame.
463 * Needs to be called before the overlay register are changed
Chris Wilson8d74f652010-08-12 10:35:26 +0100464 * via intel_overlay_(un)map_regs
465 */
Daniel Vetter02e792f2009-09-15 22:57:34 +0200466static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
467{
Chris Wilson5cd68c92010-08-12 12:21:54 +0100468 struct drm_device *dev = overlay->dev;
469 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200470 int ret;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200471
Chris Wilson5cd68c92010-08-12 12:21:54 +0100472 /* Only wait if there is actually an old frame to release to
473 * guarantee forward progress.
474 */
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200475 if (!overlay->old_vid_bo)
476 return 0;
477
Chris Wilson5cd68c92010-08-12 12:21:54 +0100478 if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
Chris Wilson8dc5d142010-08-12 12:36:12 +0100479 struct drm_i915_gem_request *request;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200480
Chris Wilson5cd68c92010-08-12 12:21:54 +0100481 /* synchronous slowpath */
Chris Wilson8dc5d142010-08-12 12:36:12 +0100482 request = kzalloc(sizeof(*request), GFP_KERNEL);
483 if (request == NULL)
484 return -ENOMEM;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200485
Chris Wilsone1f99ce2010-10-27 12:45:26 +0100486 ret = BEGIN_LP_RING(2);
487 if (ret) {
488 kfree(request);
489 return ret;
490 }
491
Chris Wilson5cd68c92010-08-12 12:21:54 +0100492 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
493 OUT_RING(MI_NOOP);
494 ADVANCE_LP_RING();
Daniel Vetter02e792f2009-09-15 22:57:34 +0200495
Chris Wilsonce453d82011-02-21 14:43:56 +0000496 ret = intel_overlay_do_wait_request(overlay, request,
Chris Wilsonb303cf92010-08-12 14:03:48 +0100497 intel_overlay_release_old_vid_tail);
Chris Wilson5cd68c92010-08-12 12:21:54 +0100498 if (ret)
499 return ret;
500 }
Daniel Vetter02e792f2009-09-15 22:57:34 +0200501
Chris Wilson5cd68c92010-08-12 12:21:54 +0100502 intel_overlay_release_old_vid_tail(overlay);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200503 return 0;
504}
505
506struct put_image_params {
507 int format;
508 short dst_x;
509 short dst_y;
510 short dst_w;
511 short dst_h;
512 short src_w;
513 short src_scan_h;
514 short src_scan_w;
515 short src_h;
516 short stride_Y;
517 short stride_UV;
518 int offset_Y;
519 int offset_U;
520 int offset_V;
521};
522
523static int packed_depth_bytes(u32 format)
524{
525 switch (format & I915_OVERLAY_DEPTH_MASK) {
Chris Wilson722506f2010-08-12 09:28:50 +0100526 case I915_OVERLAY_YUV422:
527 return 4;
528 case I915_OVERLAY_YUV411:
529 /* return 6; not implemented */
530 default:
531 return -EINVAL;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200532 }
533}
534
535static int packed_width_bytes(u32 format, short width)
536{
537 switch (format & I915_OVERLAY_DEPTH_MASK) {
Chris Wilson722506f2010-08-12 09:28:50 +0100538 case I915_OVERLAY_YUV422:
539 return width << 1;
540 default:
541 return -EINVAL;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200542 }
543}
544
545static int uv_hsubsampling(u32 format)
546{
547 switch (format & I915_OVERLAY_DEPTH_MASK) {
Chris Wilson722506f2010-08-12 09:28:50 +0100548 case I915_OVERLAY_YUV422:
549 case I915_OVERLAY_YUV420:
550 return 2;
551 case I915_OVERLAY_YUV411:
552 case I915_OVERLAY_YUV410:
553 return 4;
554 default:
555 return -EINVAL;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200556 }
557}
558
559static int uv_vsubsampling(u32 format)
560{
561 switch (format & I915_OVERLAY_DEPTH_MASK) {
Chris Wilson722506f2010-08-12 09:28:50 +0100562 case I915_OVERLAY_YUV420:
563 case I915_OVERLAY_YUV410:
564 return 2;
565 case I915_OVERLAY_YUV422:
566 case I915_OVERLAY_YUV411:
567 return 1;
568 default:
569 return -EINVAL;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200570 }
571}
572
573static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
574{
575 u32 mask, shift, ret;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100576 if (IS_GEN2(dev)) {
Daniel Vetter02e792f2009-09-15 22:57:34 +0200577 mask = 0x1f;
578 shift = 5;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100579 } else {
580 mask = 0x3f;
581 shift = 6;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200582 }
583 ret = ((offset + width + mask) >> shift) - (offset >> shift);
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100584 if (!IS_GEN2(dev))
Daniel Vetter02e792f2009-09-15 22:57:34 +0200585 ret <<= 1;
586 ret -=1;
587 return ret << 2;
588}
589
590static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
591 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
592 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
593 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
594 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
595 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
596 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
597 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
598 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
599 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
600 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
601 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
602 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
603 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
604 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
605 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
606 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
Chris Wilson722506f2010-08-12 09:28:50 +0100607 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
608};
609
Daniel Vetter02e792f2009-09-15 22:57:34 +0200610static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
611 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
612 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
613 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
614 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
615 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
616 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
617 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
618 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
Chris Wilson722506f2010-08-12 09:28:50 +0100619 0x3000, 0x0800, 0x3000
620};
Daniel Vetter02e792f2009-09-15 22:57:34 +0200621
622static void update_polyphase_filter(struct overlay_registers *regs)
623{
624 memcpy(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
625 memcpy(regs->UV_HCOEFS, uv_static_hcoeffs, sizeof(uv_static_hcoeffs));
626}
627
628static bool update_scaling_factors(struct intel_overlay *overlay,
629 struct overlay_registers *regs,
630 struct put_image_params *params)
631{
632 /* fixed point with a 12 bit shift */
633 u32 xscale, yscale, xscale_UV, yscale_UV;
634#define FP_SHIFT 12
635#define FRACT_MASK 0xfff
636 bool scale_changed = false;
637 int uv_hscale = uv_hsubsampling(params->format);
638 int uv_vscale = uv_vsubsampling(params->format);
639
640 if (params->dst_w > 1)
641 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
642 /(params->dst_w);
643 else
644 xscale = 1 << FP_SHIFT;
645
646 if (params->dst_h > 1)
647 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
648 /(params->dst_h);
649 else
650 yscale = 1 << FP_SHIFT;
651
652 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
Chris Wilson722506f2010-08-12 09:28:50 +0100653 xscale_UV = xscale/uv_hscale;
654 yscale_UV = yscale/uv_vscale;
655 /* make the Y scale to UV scale ratio an exact multiply */
656 xscale = xscale_UV * uv_hscale;
657 yscale = yscale_UV * uv_vscale;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200658 /*} else {
Chris Wilson722506f2010-08-12 09:28:50 +0100659 xscale_UV = 0;
660 yscale_UV = 0;
661 }*/
Daniel Vetter02e792f2009-09-15 22:57:34 +0200662
663 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
664 scale_changed = true;
665 overlay->old_xscale = xscale;
666 overlay->old_yscale = yscale;
667
Chris Wilson722506f2010-08-12 09:28:50 +0100668 regs->YRGBSCALE = (((yscale & FRACT_MASK) << 20) |
669 ((xscale >> FP_SHIFT) << 16) |
670 ((xscale & FRACT_MASK) << 3));
671
672 regs->UVSCALE = (((yscale_UV & FRACT_MASK) << 20) |
673 ((xscale_UV >> FP_SHIFT) << 16) |
674 ((xscale_UV & FRACT_MASK) << 3));
675
676 regs->UVSCALEV = ((((yscale >> FP_SHIFT) << 16) |
677 ((yscale_UV >> FP_SHIFT) << 0)));
Daniel Vetter02e792f2009-09-15 22:57:34 +0200678
679 if (scale_changed)
680 update_polyphase_filter(regs);
681
682 return scale_changed;
683}
684
685static void update_colorkey(struct intel_overlay *overlay,
686 struct overlay_registers *regs)
687{
688 u32 key = overlay->color_key;
Chris Wilson6ba3ddd2010-08-12 09:30:58 +0100689
Daniel Vetter02e792f2009-09-15 22:57:34 +0200690 switch (overlay->crtc->base.fb->bits_per_pixel) {
Chris Wilson722506f2010-08-12 09:28:50 +0100691 case 8:
692 regs->DCLRKV = 0;
693 regs->DCLRKM = CLK_RGB8I_MASK | DST_KEY_ENABLE;
Chris Wilson6ba3ddd2010-08-12 09:30:58 +0100694 break;
695
Chris Wilson722506f2010-08-12 09:28:50 +0100696 case 16:
697 if (overlay->crtc->base.fb->depth == 15) {
698 regs->DCLRKV = RGB15_TO_COLORKEY(key);
699 regs->DCLRKM = CLK_RGB15_MASK | DST_KEY_ENABLE;
700 } else {
701 regs->DCLRKV = RGB16_TO_COLORKEY(key);
702 regs->DCLRKM = CLK_RGB16_MASK | DST_KEY_ENABLE;
703 }
Chris Wilson6ba3ddd2010-08-12 09:30:58 +0100704 break;
705
Chris Wilson722506f2010-08-12 09:28:50 +0100706 case 24:
707 case 32:
708 regs->DCLRKV = key;
709 regs->DCLRKM = CLK_RGB24_MASK | DST_KEY_ENABLE;
Chris Wilson6ba3ddd2010-08-12 09:30:58 +0100710 break;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200711 }
712}
713
714static u32 overlay_cmd_reg(struct put_image_params *params)
715{
716 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
717
718 if (params->format & I915_OVERLAY_YUV_PLANAR) {
719 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
Chris Wilson722506f2010-08-12 09:28:50 +0100720 case I915_OVERLAY_YUV422:
721 cmd |= OCMD_YUV_422_PLANAR;
722 break;
723 case I915_OVERLAY_YUV420:
724 cmd |= OCMD_YUV_420_PLANAR;
725 break;
726 case I915_OVERLAY_YUV411:
727 case I915_OVERLAY_YUV410:
728 cmd |= OCMD_YUV_410_PLANAR;
729 break;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200730 }
731 } else { /* YUV packed */
732 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
Chris Wilson722506f2010-08-12 09:28:50 +0100733 case I915_OVERLAY_YUV422:
734 cmd |= OCMD_YUV_422_PACKED;
735 break;
736 case I915_OVERLAY_YUV411:
737 cmd |= OCMD_YUV_411_PACKED;
738 break;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200739 }
740
741 switch (params->format & I915_OVERLAY_SWAP_MASK) {
Chris Wilson722506f2010-08-12 09:28:50 +0100742 case I915_OVERLAY_NO_SWAP:
743 break;
744 case I915_OVERLAY_UV_SWAP:
745 cmd |= OCMD_UV_SWAP;
746 break;
747 case I915_OVERLAY_Y_SWAP:
748 cmd |= OCMD_Y_SWAP;
749 break;
750 case I915_OVERLAY_Y_AND_UV_SWAP:
751 cmd |= OCMD_Y_AND_UV_SWAP;
752 break;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200753 }
754 }
755
756 return cmd;
757}
758
Chris Wilson5fe82c52010-08-12 12:38:21 +0100759static int intel_overlay_do_put_image(struct intel_overlay *overlay,
Chris Wilson05394f32010-11-08 19:18:58 +0000760 struct drm_i915_gem_object *new_bo,
Chris Wilson5fe82c52010-08-12 12:38:21 +0100761 struct put_image_params *params)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200762{
763 int ret, tmp_width;
764 struct overlay_registers *regs;
765 bool scale_changed = false;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200766 struct drm_device *dev = overlay->dev;
767
768 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
769 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
770 BUG_ON(!overlay);
771
Daniel Vetter02e792f2009-09-15 22:57:34 +0200772 ret = intel_overlay_release_old_vid(overlay);
773 if (ret != 0)
774 return ret;
775
Daniel Vetter75e9e912010-11-04 17:11:09 +0100776 ret = i915_gem_object_pin(new_bo, PAGE_SIZE, true);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200777 if (ret != 0)
778 return ret;
779
780 ret = i915_gem_object_set_to_gtt_domain(new_bo, 0);
781 if (ret != 0)
782 goto out_unpin;
783
Chris Wilsond9e86c02010-11-10 16:40:20 +0000784 ret = i915_gem_object_put_fence(new_bo);
785 if (ret)
786 goto out_unpin;
787
Daniel Vetter02e792f2009-09-15 22:57:34 +0200788 if (!overlay->active) {
Chris Wilson8d74f652010-08-12 10:35:26 +0100789 regs = intel_overlay_map_regs(overlay);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200790 if (!regs) {
791 ret = -ENOMEM;
792 goto out_unpin;
793 }
794 regs->OCONFIG = OCONF_CC_OUT_8BIT;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100795 if (IS_GEN4(overlay->dev))
Daniel Vetter02e792f2009-09-15 22:57:34 +0200796 regs->OCONFIG |= OCONF_CSC_MODE_BT709;
797 regs->OCONFIG |= overlay->crtc->pipe == 0 ?
798 OCONF_PIPE_A : OCONF_PIPE_B;
Chris Wilson9bb2ff72010-08-12 12:02:11 +0100799 intel_overlay_unmap_regs(overlay, regs);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200800
801 ret = intel_overlay_on(overlay);
802 if (ret != 0)
803 goto out_unpin;
804 }
805
Chris Wilson8d74f652010-08-12 10:35:26 +0100806 regs = intel_overlay_map_regs(overlay);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200807 if (!regs) {
808 ret = -ENOMEM;
809 goto out_unpin;
810 }
811
812 regs->DWINPOS = (params->dst_y << 16) | params->dst_x;
813 regs->DWINSZ = (params->dst_h << 16) | params->dst_w;
814
815 if (params->format & I915_OVERLAY_YUV_PACKED)
816 tmp_width = packed_width_bytes(params->format, params->src_w);
817 else
818 tmp_width = params->src_w;
819
820 regs->SWIDTH = params->src_w;
821 regs->SWIDTHSW = calc_swidthsw(overlay->dev,
Chris Wilson722506f2010-08-12 09:28:50 +0100822 params->offset_Y, tmp_width);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200823 regs->SHEIGHT = params->src_h;
Chris Wilson05394f32010-11-08 19:18:58 +0000824 regs->OBUF_0Y = new_bo->gtt_offset + params-> offset_Y;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200825 regs->OSTRIDE = params->stride_Y;
826
827 if (params->format & I915_OVERLAY_YUV_PLANAR) {
828 int uv_hscale = uv_hsubsampling(params->format);
829 int uv_vscale = uv_vsubsampling(params->format);
830 u32 tmp_U, tmp_V;
831 regs->SWIDTH |= (params->src_w/uv_hscale) << 16;
832 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
Chris Wilson722506f2010-08-12 09:28:50 +0100833 params->src_w/uv_hscale);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200834 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
Chris Wilson722506f2010-08-12 09:28:50 +0100835 params->src_w/uv_hscale);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200836 regs->SWIDTHSW |= max_t(u32, tmp_U, tmp_V) << 16;
837 regs->SHEIGHT |= (params->src_h/uv_vscale) << 16;
Chris Wilson05394f32010-11-08 19:18:58 +0000838 regs->OBUF_0U = new_bo->gtt_offset + params->offset_U;
839 regs->OBUF_0V = new_bo->gtt_offset + params->offset_V;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200840 regs->OSTRIDE |= params->stride_UV << 16;
841 }
842
843 scale_changed = update_scaling_factors(overlay, regs, params);
844
845 update_colorkey(overlay, regs);
846
847 regs->OCMD = overlay_cmd_reg(params);
848
Chris Wilson9bb2ff72010-08-12 12:02:11 +0100849 intel_overlay_unmap_regs(overlay, regs);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200850
Chris Wilson8dc5d142010-08-12 12:36:12 +0100851 ret = intel_overlay_continue(overlay, scale_changed);
852 if (ret)
853 goto out_unpin;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200854
855 overlay->old_vid_bo = overlay->vid_bo;
Chris Wilson05394f32010-11-08 19:18:58 +0000856 overlay->vid_bo = new_bo;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200857
858 return 0;
859
860out_unpin:
861 i915_gem_object_unpin(new_bo);
862 return ret;
863}
864
Chris Wilsonce453d82011-02-21 14:43:56 +0000865int intel_overlay_switch_off(struct intel_overlay *overlay)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200866{
Daniel Vetter02e792f2009-09-15 22:57:34 +0200867 struct overlay_registers *regs;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200868 struct drm_device *dev = overlay->dev;
Chris Wilson5dcdbcb2010-08-12 13:50:28 +0100869 int ret;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200870
871 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
872 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
873
Chris Wilsonce453d82011-02-21 14:43:56 +0000874 ret = intel_overlay_recover_from_interrupt(overlay);
Chris Wilsonb303cf92010-08-12 14:03:48 +0100875 if (ret != 0)
876 return ret;
Daniel Vetter9bedb972009-11-30 15:55:49 +0100877
Daniel Vetter02e792f2009-09-15 22:57:34 +0200878 if (!overlay->active)
879 return 0;
880
Daniel Vetter02e792f2009-09-15 22:57:34 +0200881 ret = intel_overlay_release_old_vid(overlay);
882 if (ret != 0)
883 return ret;
884
Chris Wilson8d74f652010-08-12 10:35:26 +0100885 regs = intel_overlay_map_regs(overlay);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200886 regs->OCMD = 0;
Chris Wilson9bb2ff72010-08-12 12:02:11 +0100887 intel_overlay_unmap_regs(overlay, regs);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200888
Chris Wilsonce453d82011-02-21 14:43:56 +0000889 ret = intel_overlay_off(overlay);
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200890 if (ret != 0)
891 return ret;
892
Daniel Vetter12ca45f2037-04-25 10:08:26 +0200893 intel_overlay_off_tail(overlay);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200894 return 0;
895}
896
897static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
898 struct intel_crtc *crtc)
899{
Chris Wilson722506f2010-08-12 09:28:50 +0100900 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200901
Chris Wilsonf7abfe82010-09-13 14:19:16 +0100902 if (!crtc->active)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200903 return -EINVAL;
904
Daniel Vetter02e792f2009-09-15 22:57:34 +0200905 /* can't use the overlay with double wide pipe */
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100906 if (INTEL_INFO(overlay->dev)->gen < 4 &&
Chris Wilsonf7abfe82010-09-13 14:19:16 +0100907 (I915_READ(PIPECONF(crtc->pipe)) & (PIPECONF_DOUBLE_WIDE | PIPECONF_ENABLE)) != PIPECONF_ENABLE)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200908 return -EINVAL;
909
910 return 0;
911}
912
913static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
914{
915 struct drm_device *dev = overlay->dev;
Chris Wilson722506f2010-08-12 09:28:50 +0100916 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200917 u32 pfit_control = I915_READ(PFIT_CONTROL);
Chris Wilson446d2182010-08-12 11:15:58 +0100918 u32 ratio;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200919
920 /* XXX: This is not the same logic as in the xorg driver, but more in
Chris Wilson446d2182010-08-12 11:15:58 +0100921 * line with the intel documentation for the i965
922 */
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100923 if (INTEL_INFO(dev)->gen >= 4) {
924 /* on i965 use the PGM reg to read out the autoscaler values */
925 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
926 } else {
Chris Wilson446d2182010-08-12 11:15:58 +0100927 if (pfit_control & VERT_AUTO_SCALE)
928 ratio = I915_READ(PFIT_AUTO_RATIOS);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200929 else
Chris Wilson446d2182010-08-12 11:15:58 +0100930 ratio = I915_READ(PFIT_PGM_RATIOS);
931 ratio >>= PFIT_VERT_SCALE_SHIFT;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200932 }
933
934 overlay->pfit_vscale_ratio = ratio;
935}
936
937static int check_overlay_dst(struct intel_overlay *overlay,
938 struct drm_intel_overlay_put_image *rec)
939{
940 struct drm_display_mode *mode = &overlay->crtc->base.mode;
941
Chris Wilson722506f2010-08-12 09:28:50 +0100942 if (rec->dst_x < mode->crtc_hdisplay &&
943 rec->dst_x + rec->dst_width <= mode->crtc_hdisplay &&
944 rec->dst_y < mode->crtc_vdisplay &&
945 rec->dst_y + rec->dst_height <= mode->crtc_vdisplay)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200946 return 0;
947 else
948 return -EINVAL;
949}
950
951static int check_overlay_scaling(struct put_image_params *rec)
952{
953 u32 tmp;
954
955 /* downscaling limit is 8.0 */
956 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
957 if (tmp > 7)
958 return -EINVAL;
959 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
960 if (tmp > 7)
961 return -EINVAL;
962
963 return 0;
964}
965
966static int check_overlay_src(struct drm_device *dev,
967 struct drm_intel_overlay_put_image *rec,
Chris Wilson05394f32010-11-08 19:18:58 +0000968 struct drm_i915_gem_object *new_bo)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200969{
Daniel Vetter02e792f2009-09-15 22:57:34 +0200970 int uv_hscale = uv_hsubsampling(rec->flags);
971 int uv_vscale = uv_vsubsampling(rec->flags);
Dan Carpenter8f28f542010-10-27 23:17:25 +0200972 u32 stride_mask;
973 int depth;
974 u32 tmp;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200975
976 /* check src dimensions */
977 if (IS_845G(dev) || IS_I830(dev)) {
Chris Wilson722506f2010-08-12 09:28:50 +0100978 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
Chris Wilson9f7c3f42010-08-12 11:29:34 +0100979 rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200980 return -EINVAL;
981 } else {
Chris Wilson722506f2010-08-12 09:28:50 +0100982 if (rec->src_height > IMAGE_MAX_HEIGHT ||
Chris Wilson9f7c3f42010-08-12 11:29:34 +0100983 rec->src_width > IMAGE_MAX_WIDTH)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200984 return -EINVAL;
985 }
Chris Wilson9f7c3f42010-08-12 11:29:34 +0100986
Daniel Vetter02e792f2009-09-15 22:57:34 +0200987 /* better safe than sorry, use 4 as the maximal subsampling ratio */
Chris Wilson722506f2010-08-12 09:28:50 +0100988 if (rec->src_height < N_VERT_Y_TAPS*4 ||
Chris Wilson9f7c3f42010-08-12 11:29:34 +0100989 rec->src_width < N_HORIZ_Y_TAPS*4)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200990 return -EINVAL;
991
Chris Wilsona1efd142010-07-12 19:35:38 +0100992 /* check alignment constraints */
Daniel Vetter02e792f2009-09-15 22:57:34 +0200993 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
Chris Wilson722506f2010-08-12 09:28:50 +0100994 case I915_OVERLAY_RGB:
995 /* not implemented */
996 return -EINVAL;
Chris Wilson9f7c3f42010-08-12 11:29:34 +0100997
Chris Wilson722506f2010-08-12 09:28:50 +0100998 case I915_OVERLAY_YUV_PACKED:
Chris Wilson722506f2010-08-12 09:28:50 +0100999 if (uv_vscale != 1)
Daniel Vetter02e792f2009-09-15 22:57:34 +02001000 return -EINVAL;
Chris Wilson9f7c3f42010-08-12 11:29:34 +01001001
1002 depth = packed_depth_bytes(rec->flags);
Chris Wilson722506f2010-08-12 09:28:50 +01001003 if (depth < 0)
1004 return depth;
Chris Wilson9f7c3f42010-08-12 11:29:34 +01001005
Chris Wilson722506f2010-08-12 09:28:50 +01001006 /* ignore UV planes */
1007 rec->stride_UV = 0;
1008 rec->offset_U = 0;
1009 rec->offset_V = 0;
1010 /* check pixel alignment */
1011 if (rec->offset_Y % depth)
Daniel Vetter02e792f2009-09-15 22:57:34 +02001012 return -EINVAL;
Chris Wilson722506f2010-08-12 09:28:50 +01001013 break;
Chris Wilson9f7c3f42010-08-12 11:29:34 +01001014
Chris Wilson722506f2010-08-12 09:28:50 +01001015 case I915_OVERLAY_YUV_PLANAR:
1016 if (uv_vscale < 0 || uv_hscale < 0)
1017 return -EINVAL;
1018 /* no offset restrictions for planar formats */
1019 break;
Chris Wilson9f7c3f42010-08-12 11:29:34 +01001020
Chris Wilson722506f2010-08-12 09:28:50 +01001021 default:
1022 return -EINVAL;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001023 }
1024
1025 if (rec->src_width % uv_hscale)
1026 return -EINVAL;
1027
1028 /* stride checking */
Chris Wilsona1efd142010-07-12 19:35:38 +01001029 if (IS_I830(dev) || IS_845G(dev))
1030 stride_mask = 255;
1031 else
1032 stride_mask = 63;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001033
1034 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1035 return -EINVAL;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001036 if (IS_GEN4(dev) && rec->stride_Y < 512)
Daniel Vetter02e792f2009-09-15 22:57:34 +02001037 return -EINVAL;
1038
1039 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
Chris Wilson9f7c3f42010-08-12 11:29:34 +01001040 4096 : 8192;
1041 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
Daniel Vetter02e792f2009-09-15 22:57:34 +02001042 return -EINVAL;
1043
1044 /* check buffer dimensions */
1045 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
Chris Wilson722506f2010-08-12 09:28:50 +01001046 case I915_OVERLAY_RGB:
1047 case I915_OVERLAY_YUV_PACKED:
1048 /* always 4 Y values per depth pixels */
1049 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1050 return -EINVAL;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001051
Chris Wilson722506f2010-08-12 09:28:50 +01001052 tmp = rec->stride_Y*rec->src_height;
Chris Wilson05394f32010-11-08 19:18:58 +00001053 if (rec->offset_Y + tmp > new_bo->base.size)
Chris Wilson722506f2010-08-12 09:28:50 +01001054 return -EINVAL;
1055 break;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001056
Chris Wilson722506f2010-08-12 09:28:50 +01001057 case I915_OVERLAY_YUV_PLANAR:
1058 if (rec->src_width > rec->stride_Y)
1059 return -EINVAL;
1060 if (rec->src_width/uv_hscale > rec->stride_UV)
1061 return -EINVAL;
1062
Chris Wilson9f7c3f42010-08-12 11:29:34 +01001063 tmp = rec->stride_Y * rec->src_height;
Chris Wilson05394f32010-11-08 19:18:58 +00001064 if (rec->offset_Y + tmp > new_bo->base.size)
Chris Wilson722506f2010-08-12 09:28:50 +01001065 return -EINVAL;
Chris Wilson9f7c3f42010-08-12 11:29:34 +01001066
1067 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
Chris Wilson05394f32010-11-08 19:18:58 +00001068 if (rec->offset_U + tmp > new_bo->base.size ||
1069 rec->offset_V + tmp > new_bo->base.size)
Chris Wilson722506f2010-08-12 09:28:50 +01001070 return -EINVAL;
1071 break;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001072 }
1073
1074 return 0;
1075}
1076
Chris Wilsone9e331a2010-09-13 01:16:10 +01001077/**
1078 * Return the pipe currently connected to the panel fitter,
1079 * or -1 if the panel fitter is not present or not in use
1080 */
1081static int intel_panel_fitter_pipe(struct drm_device *dev)
1082{
1083 struct drm_i915_private *dev_priv = dev->dev_private;
1084 u32 pfit_control;
1085
1086 /* i830 doesn't have a panel fitter */
1087 if (IS_I830(dev))
1088 return -1;
1089
1090 pfit_control = I915_READ(PFIT_CONTROL);
1091
1092 /* See if the panel fitter is in use */
1093 if ((pfit_control & PFIT_ENABLE) == 0)
1094 return -1;
1095
1096 /* 965 can place panel fitter on either pipe */
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001097 if (IS_GEN4(dev))
Chris Wilsone9e331a2010-09-13 01:16:10 +01001098 return (pfit_control >> 29) & 0x3;
1099
1100 /* older chips can only use pipe 1 */
1101 return 1;
1102}
1103
Daniel Vetter02e792f2009-09-15 22:57:34 +02001104int intel_overlay_put_image(struct drm_device *dev, void *data,
1105 struct drm_file *file_priv)
1106{
1107 struct drm_intel_overlay_put_image *put_image_rec = data;
1108 drm_i915_private_t *dev_priv = dev->dev_private;
1109 struct intel_overlay *overlay;
1110 struct drm_mode_object *drmmode_obj;
1111 struct intel_crtc *crtc;
Chris Wilson05394f32010-11-08 19:18:58 +00001112 struct drm_i915_gem_object *new_bo;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001113 struct put_image_params *params;
1114 int ret;
1115
1116 if (!dev_priv) {
1117 DRM_ERROR("called with no initialization\n");
1118 return -EINVAL;
1119 }
1120
1121 overlay = dev_priv->overlay;
1122 if (!overlay) {
1123 DRM_DEBUG("userspace bug: no overlay\n");
1124 return -ENODEV;
1125 }
1126
1127 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1128 mutex_lock(&dev->mode_config.mutex);
1129 mutex_lock(&dev->struct_mutex);
1130
Chris Wilsonce453d82011-02-21 14:43:56 +00001131 ret = intel_overlay_switch_off(overlay);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001132
1133 mutex_unlock(&dev->struct_mutex);
1134 mutex_unlock(&dev->mode_config.mutex);
1135
1136 return ret;
1137 }
1138
1139 params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
1140 if (!params)
1141 return -ENOMEM;
1142
1143 drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
Chris Wilson722506f2010-08-12 09:28:50 +01001144 DRM_MODE_OBJECT_CRTC);
Dan Carpenter915a4282010-03-06 14:05:39 +03001145 if (!drmmode_obj) {
1146 ret = -ENOENT;
1147 goto out_free;
1148 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02001149 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
1150
Chris Wilson05394f32010-11-08 19:18:58 +00001151 new_bo = to_intel_bo(drm_gem_object_lookup(dev, file_priv,
1152 put_image_rec->bo_handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00001153 if (&new_bo->base == NULL) {
Dan Carpenter915a4282010-03-06 14:05:39 +03001154 ret = -ENOENT;
1155 goto out_free;
1156 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02001157
1158 mutex_lock(&dev->mode_config.mutex);
1159 mutex_lock(&dev->struct_mutex);
1160
Chris Wilsond9e86c02010-11-10 16:40:20 +00001161 if (new_bo->tiling_mode) {
1162 DRM_ERROR("buffer used for overlay image can not be tiled\n");
1163 ret = -EINVAL;
1164 goto out_unlock;
1165 }
1166
Chris Wilsonce453d82011-02-21 14:43:56 +00001167 ret = intel_overlay_recover_from_interrupt(overlay);
Chris Wilsonb303cf92010-08-12 14:03:48 +01001168 if (ret != 0)
1169 goto out_unlock;
Daniel Vetter03f77ea2009-09-15 22:57:37 +02001170
Daniel Vetter02e792f2009-09-15 22:57:34 +02001171 if (overlay->crtc != crtc) {
1172 struct drm_display_mode *mode = &crtc->base.mode;
Chris Wilsonce453d82011-02-21 14:43:56 +00001173 ret = intel_overlay_switch_off(overlay);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001174 if (ret != 0)
1175 goto out_unlock;
1176
1177 ret = check_overlay_possible_on_crtc(overlay, crtc);
1178 if (ret != 0)
1179 goto out_unlock;
1180
1181 overlay->crtc = crtc;
1182 crtc->overlay = overlay;
1183
Chris Wilsone9e331a2010-09-13 01:16:10 +01001184 /* line too wide, i.e. one-line-mode */
1185 if (mode->hdisplay > 1024 &&
1186 intel_panel_fitter_pipe(dev) == crtc->pipe) {
Daniel Vetter02e792f2009-09-15 22:57:34 +02001187 overlay->pfit_active = 1;
1188 update_pfit_vscale_ratio(overlay);
1189 } else
1190 overlay->pfit_active = 0;
1191 }
1192
1193 ret = check_overlay_dst(overlay, put_image_rec);
1194 if (ret != 0)
1195 goto out_unlock;
1196
1197 if (overlay->pfit_active) {
1198 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
Chris Wilson722506f2010-08-12 09:28:50 +01001199 overlay->pfit_vscale_ratio);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001200 /* shifting right rounds downwards, so add 1 */
1201 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
Chris Wilson722506f2010-08-12 09:28:50 +01001202 overlay->pfit_vscale_ratio) + 1;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001203 } else {
1204 params->dst_y = put_image_rec->dst_y;
1205 params->dst_h = put_image_rec->dst_height;
1206 }
1207 params->dst_x = put_image_rec->dst_x;
1208 params->dst_w = put_image_rec->dst_width;
1209
1210 params->src_w = put_image_rec->src_width;
1211 params->src_h = put_image_rec->src_height;
1212 params->src_scan_w = put_image_rec->src_scan_width;
1213 params->src_scan_h = put_image_rec->src_scan_height;
Chris Wilson722506f2010-08-12 09:28:50 +01001214 if (params->src_scan_h > params->src_h ||
1215 params->src_scan_w > params->src_w) {
Daniel Vetter02e792f2009-09-15 22:57:34 +02001216 ret = -EINVAL;
1217 goto out_unlock;
1218 }
1219
1220 ret = check_overlay_src(dev, put_image_rec, new_bo);
1221 if (ret != 0)
1222 goto out_unlock;
1223 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1224 params->stride_Y = put_image_rec->stride_Y;
1225 params->stride_UV = put_image_rec->stride_UV;
1226 params->offset_Y = put_image_rec->offset_Y;
1227 params->offset_U = put_image_rec->offset_U;
1228 params->offset_V = put_image_rec->offset_V;
1229
1230 /* Check scaling after src size to prevent a divide-by-zero. */
1231 ret = check_overlay_scaling(params);
1232 if (ret != 0)
1233 goto out_unlock;
1234
1235 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1236 if (ret != 0)
1237 goto out_unlock;
1238
1239 mutex_unlock(&dev->struct_mutex);
1240 mutex_unlock(&dev->mode_config.mutex);
1241
1242 kfree(params);
1243
1244 return 0;
1245
1246out_unlock:
1247 mutex_unlock(&dev->struct_mutex);
1248 mutex_unlock(&dev->mode_config.mutex);
Chris Wilson05394f32010-11-08 19:18:58 +00001249 drm_gem_object_unreference_unlocked(&new_bo->base);
Dan Carpenter915a4282010-03-06 14:05:39 +03001250out_free:
Daniel Vetter02e792f2009-09-15 22:57:34 +02001251 kfree(params);
1252
1253 return ret;
1254}
1255
1256static void update_reg_attrs(struct intel_overlay *overlay,
1257 struct overlay_registers *regs)
1258{
1259 regs->OCLRC0 = (overlay->contrast << 18) | (overlay->brightness & 0xff);
1260 regs->OCLRC1 = overlay->saturation;
1261}
1262
1263static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1264{
1265 int i;
1266
1267 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1268 return false;
1269
1270 for (i = 0; i < 3; i++) {
Chris Wilson722506f2010-08-12 09:28:50 +01001271 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
Daniel Vetter02e792f2009-09-15 22:57:34 +02001272 return false;
1273 }
1274
1275 return true;
1276}
1277
1278static bool check_gamma5_errata(u32 gamma5)
1279{
1280 int i;
1281
1282 for (i = 0; i < 3; i++) {
1283 if (((gamma5 >> i*8) & 0xff) == 0x80)
1284 return false;
1285 }
1286
1287 return true;
1288}
1289
1290static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1291{
Chris Wilson722506f2010-08-12 09:28:50 +01001292 if (!check_gamma_bounds(0, attrs->gamma0) ||
1293 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1294 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1295 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1296 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1297 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1298 !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
Daniel Vetter02e792f2009-09-15 22:57:34 +02001299 return -EINVAL;
Chris Wilson722506f2010-08-12 09:28:50 +01001300
Daniel Vetter02e792f2009-09-15 22:57:34 +02001301 if (!check_gamma5_errata(attrs->gamma5))
1302 return -EINVAL;
Chris Wilson722506f2010-08-12 09:28:50 +01001303
Daniel Vetter02e792f2009-09-15 22:57:34 +02001304 return 0;
1305}
1306
1307int intel_overlay_attrs(struct drm_device *dev, void *data,
1308 struct drm_file *file_priv)
1309{
1310 struct drm_intel_overlay_attrs *attrs = data;
1311 drm_i915_private_t *dev_priv = dev->dev_private;
1312 struct intel_overlay *overlay;
1313 struct overlay_registers *regs;
1314 int ret;
1315
1316 if (!dev_priv) {
1317 DRM_ERROR("called with no initialization\n");
1318 return -EINVAL;
1319 }
1320
1321 overlay = dev_priv->overlay;
1322 if (!overlay) {
1323 DRM_DEBUG("userspace bug: no overlay\n");
1324 return -ENODEV;
1325 }
1326
1327 mutex_lock(&dev->mode_config.mutex);
1328 mutex_lock(&dev->struct_mutex);
1329
Chris Wilson60fc3322010-08-12 10:44:45 +01001330 ret = -EINVAL;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001331 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
Chris Wilson60fc3322010-08-12 10:44:45 +01001332 attrs->color_key = overlay->color_key;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001333 attrs->brightness = overlay->brightness;
Chris Wilson60fc3322010-08-12 10:44:45 +01001334 attrs->contrast = overlay->contrast;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001335 attrs->saturation = overlay->saturation;
1336
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001337 if (!IS_GEN2(dev)) {
Daniel Vetter02e792f2009-09-15 22:57:34 +02001338 attrs->gamma0 = I915_READ(OGAMC0);
1339 attrs->gamma1 = I915_READ(OGAMC1);
1340 attrs->gamma2 = I915_READ(OGAMC2);
1341 attrs->gamma3 = I915_READ(OGAMC3);
1342 attrs->gamma4 = I915_READ(OGAMC4);
1343 attrs->gamma5 = I915_READ(OGAMC5);
1344 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02001345 } else {
Chris Wilson60fc3322010-08-12 10:44:45 +01001346 if (attrs->brightness < -128 || attrs->brightness > 127)
Daniel Vetter02e792f2009-09-15 22:57:34 +02001347 goto out_unlock;
Chris Wilson60fc3322010-08-12 10:44:45 +01001348 if (attrs->contrast > 255)
Daniel Vetter02e792f2009-09-15 22:57:34 +02001349 goto out_unlock;
Chris Wilson60fc3322010-08-12 10:44:45 +01001350 if (attrs->saturation > 1023)
Daniel Vetter02e792f2009-09-15 22:57:34 +02001351 goto out_unlock;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001352
Chris Wilson60fc3322010-08-12 10:44:45 +01001353 overlay->color_key = attrs->color_key;
1354 overlay->brightness = attrs->brightness;
1355 overlay->contrast = attrs->contrast;
1356 overlay->saturation = attrs->saturation;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001357
Chris Wilson8d74f652010-08-12 10:35:26 +01001358 regs = intel_overlay_map_regs(overlay);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001359 if (!regs) {
1360 ret = -ENOMEM;
1361 goto out_unlock;
1362 }
1363
1364 update_reg_attrs(overlay, regs);
1365
Chris Wilson9bb2ff72010-08-12 12:02:11 +01001366 intel_overlay_unmap_regs(overlay, regs);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001367
1368 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001369 if (IS_GEN2(dev))
Daniel Vetter02e792f2009-09-15 22:57:34 +02001370 goto out_unlock;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001371
1372 if (overlay->active) {
1373 ret = -EBUSY;
1374 goto out_unlock;
1375 }
1376
1377 ret = check_gamma(attrs);
Chris Wilson60fc3322010-08-12 10:44:45 +01001378 if (ret)
Daniel Vetter02e792f2009-09-15 22:57:34 +02001379 goto out_unlock;
1380
1381 I915_WRITE(OGAMC0, attrs->gamma0);
1382 I915_WRITE(OGAMC1, attrs->gamma1);
1383 I915_WRITE(OGAMC2, attrs->gamma2);
1384 I915_WRITE(OGAMC3, attrs->gamma3);
1385 I915_WRITE(OGAMC4, attrs->gamma4);
1386 I915_WRITE(OGAMC5, attrs->gamma5);
1387 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02001388 }
1389
Chris Wilson60fc3322010-08-12 10:44:45 +01001390 ret = 0;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001391out_unlock:
1392 mutex_unlock(&dev->struct_mutex);
1393 mutex_unlock(&dev->mode_config.mutex);
1394
1395 return ret;
1396}
1397
1398void intel_setup_overlay(struct drm_device *dev)
1399{
1400 drm_i915_private_t *dev_priv = dev->dev_private;
1401 struct intel_overlay *overlay;
Chris Wilson05394f32010-11-08 19:18:58 +00001402 struct drm_i915_gem_object *reg_bo;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001403 struct overlay_registers *regs;
1404 int ret;
1405
Chris Wilson315781482010-08-12 09:42:51 +01001406 if (!HAS_OVERLAY(dev))
Daniel Vetter02e792f2009-09-15 22:57:34 +02001407 return;
1408
1409 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1410 if (!overlay)
1411 return;
1412 overlay->dev = dev;
1413
Daniel Vetterac52bc52010-04-09 19:05:06 +00001414 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001415 if (!reg_bo)
1416 goto out_free;
Chris Wilson05394f32010-11-08 19:18:58 +00001417 overlay->reg_bo = reg_bo;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001418
Chris Wilson315781482010-08-12 09:42:51 +01001419 if (OVERLAY_NEEDS_PHYSICAL(dev)) {
1420 ret = i915_gem_attach_phys_object(dev, reg_bo,
1421 I915_GEM_PHYS_OVERLAY_REGS,
Chris Wilsona2930122010-08-12 10:47:56 +01001422 PAGE_SIZE);
Chris Wilson315781482010-08-12 09:42:51 +01001423 if (ret) {
1424 DRM_ERROR("failed to attach phys overlay regs\n");
1425 goto out_free_bo;
1426 }
Chris Wilson05394f32010-11-08 19:18:58 +00001427 overlay->flip_addr = reg_bo->phys_obj->handle->busaddr;
Chris Wilson315781482010-08-12 09:42:51 +01001428 } else {
Daniel Vetter75e9e912010-11-04 17:11:09 +01001429 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE, true);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001430 if (ret) {
1431 DRM_ERROR("failed to pin overlay register bo\n");
1432 goto out_free_bo;
1433 }
Chris Wilson05394f32010-11-08 19:18:58 +00001434 overlay->flip_addr = reg_bo->gtt_offset;
Chris Wilson0ddc1282010-08-12 09:35:00 +01001435
1436 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1437 if (ret) {
1438 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1439 goto out_unpin_bo;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001440 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02001441 }
1442
1443 /* init all values */
1444 overlay->color_key = 0x0101fe;
1445 overlay->brightness = -19;
1446 overlay->contrast = 75;
1447 overlay->saturation = 146;
1448
Chris Wilson8d74f652010-08-12 10:35:26 +01001449 regs = intel_overlay_map_regs(overlay);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001450 if (!regs)
1451 goto out_free_bo;
1452
1453 memset(regs, 0, sizeof(struct overlay_registers));
1454 update_polyphase_filter(regs);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001455 update_reg_attrs(overlay, regs);
1456
Chris Wilson9bb2ff72010-08-12 12:02:11 +01001457 intel_overlay_unmap_regs(overlay, regs);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001458
1459 dev_priv->overlay = overlay;
1460 DRM_INFO("initialized overlay support\n");
1461 return;
1462
Chris Wilson0ddc1282010-08-12 09:35:00 +01001463out_unpin_bo:
1464 i915_gem_object_unpin(reg_bo);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001465out_free_bo:
Chris Wilson05394f32010-11-08 19:18:58 +00001466 drm_gem_object_unreference(&reg_bo->base);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001467out_free:
1468 kfree(overlay);
1469 return;
1470}
1471
1472void intel_cleanup_overlay(struct drm_device *dev)
1473{
Chris Wilson722506f2010-08-12 09:28:50 +01001474 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001475
Chris Wilson62cf4e62010-08-12 10:50:36 +01001476 if (!dev_priv->overlay)
1477 return;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001478
Chris Wilson62cf4e62010-08-12 10:50:36 +01001479 /* The bo's should be free'd by the generic code already.
1480 * Furthermore modesetting teardown happens beforehand so the
1481 * hardware should be off already */
1482 BUG_ON(dev_priv->overlay->active);
1483
1484 drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
1485 kfree(dev_priv->overlay);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001486}
Chris Wilson6ef3d422010-08-04 20:26:07 +01001487
Chris Wilson3bd3c932010-08-19 08:19:30 +01001488#ifdef CONFIG_DEBUG_FS
1489#include <linux/seq_file.h>
1490
Chris Wilson6ef3d422010-08-04 20:26:07 +01001491struct intel_overlay_error_state {
1492 struct overlay_registers regs;
1493 unsigned long base;
1494 u32 dovsta;
1495 u32 isr;
1496};
1497
Chris Wilson3bd3c932010-08-19 08:19:30 +01001498static struct overlay_registers *
Linus Torvaldsc48c43e2010-10-26 18:57:59 -07001499intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
Chris Wilson3bd3c932010-08-19 08:19:30 +01001500{
Linus Torvaldsc48c43e2010-10-26 18:57:59 -07001501 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
Chris Wilson3bd3c932010-08-19 08:19:30 +01001502 struct overlay_registers *regs;
1503
1504 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1505 regs = overlay->reg_bo->phys_obj->handle->vaddr;
1506 else
1507 regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
Linus Torvaldsc48c43e2010-10-26 18:57:59 -07001508 overlay->reg_bo->gtt_offset);
Chris Wilson3bd3c932010-08-19 08:19:30 +01001509
1510 return regs;
1511}
1512
1513static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
Chris Wilson3bd3c932010-08-19 08:19:30 +01001514 struct overlay_registers *regs)
1515{
1516 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
Linus Torvaldsc48c43e2010-10-26 18:57:59 -07001517 io_mapping_unmap_atomic(regs);
Chris Wilson3bd3c932010-08-19 08:19:30 +01001518}
1519
1520
Chris Wilson6ef3d422010-08-04 20:26:07 +01001521struct intel_overlay_error_state *
1522intel_overlay_capture_error_state(struct drm_device *dev)
1523{
1524 drm_i915_private_t *dev_priv = dev->dev_private;
1525 struct intel_overlay *overlay = dev_priv->overlay;
1526 struct intel_overlay_error_state *error;
1527 struct overlay_registers __iomem *regs;
1528
1529 if (!overlay || !overlay->active)
1530 return NULL;
1531
1532 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1533 if (error == NULL)
1534 return NULL;
1535
1536 error->dovsta = I915_READ(DOVSTA);
1537 error->isr = I915_READ(ISR);
Chris Wilson315781482010-08-12 09:42:51 +01001538 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
Chris Wilson6ef3d422010-08-04 20:26:07 +01001539 error->base = (long) overlay->reg_bo->phys_obj->handle->vaddr;
Chris Wilson315781482010-08-12 09:42:51 +01001540 else
1541 error->base = (long) overlay->reg_bo->gtt_offset;
Chris Wilson6ef3d422010-08-04 20:26:07 +01001542
1543 regs = intel_overlay_map_regs_atomic(overlay);
1544 if (!regs)
1545 goto err;
1546
1547 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
Linus Torvaldsc48c43e2010-10-26 18:57:59 -07001548 intel_overlay_unmap_regs_atomic(overlay, regs);
Chris Wilson6ef3d422010-08-04 20:26:07 +01001549
1550 return error;
1551
1552err:
1553 kfree(error);
1554 return NULL;
1555}
1556
1557void
1558intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error)
1559{
1560 seq_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1561 error->dovsta, error->isr);
1562 seq_printf(m, " Register file at 0x%08lx:\n",
1563 error->base);
1564
1565#define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)
1566 P(OBUF_0Y);
1567 P(OBUF_1Y);
1568 P(OBUF_0U);
1569 P(OBUF_0V);
1570 P(OBUF_1U);
1571 P(OBUF_1V);
1572 P(OSTRIDE);
1573 P(YRGB_VPH);
1574 P(UV_VPH);
1575 P(HORZ_PH);
1576 P(INIT_PHS);
1577 P(DWINPOS);
1578 P(DWINSZ);
1579 P(SWIDTH);
1580 P(SWIDTHSW);
1581 P(SHEIGHT);
1582 P(YRGBSCALE);
1583 P(UVSCALE);
1584 P(OCLRC0);
1585 P(OCLRC1);
1586 P(DCLRKV);
1587 P(DCLRKM);
1588 P(SCLRKVH);
1589 P(SCLRKVL);
1590 P(SCLRKEN);
1591 P(OCONFIG);
1592 P(OCMD);
1593 P(OSTART_0Y);
1594 P(OSTART_1Y);
1595 P(OSTART_0U);
1596 P(OSTART_0V);
1597 P(OSTART_1U);
1598 P(OSTART_1V);
1599 P(OTILEOFF_0Y);
1600 P(OTILEOFF_1Y);
1601 P(OTILEOFF_0U);
1602 P(OTILEOFF_0V);
1603 P(OTILEOFF_1U);
1604 P(OTILEOFF_1V);
1605 P(FASTHSCALE);
1606 P(UVSCALEV);
1607#undef P
1608}
Chris Wilson3bd3c932010-08-19 08:19:30 +01001609#endif