Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2010 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
| 25 | #include "drmP.h" |
| 26 | |
| 27 | #include "nouveau_drv.h" |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 28 | #include "nouveau_mm.h" |
| 29 | |
| 30 | static void nvc0_fifo_isr(struct drm_device *); |
| 31 | |
| 32 | struct nvc0_fifo_priv { |
| 33 | struct nouveau_gpuobj *playlist[2]; |
| 34 | int cur_playlist; |
| 35 | struct nouveau_vma user_vma; |
Ben Skeggs | ec9c088 | 2010-12-31 12:10:49 +1000 | [diff] [blame] | 36 | int spoon_nr; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 37 | }; |
| 38 | |
| 39 | struct nvc0_fifo_chan { |
Ben Skeggs | 1233bd8 | 2011-04-13 13:55:17 +1000 | [diff] [blame] | 40 | struct nouveau_gpuobj *user; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 41 | struct nouveau_gpuobj *ramfc; |
| 42 | }; |
| 43 | |
| 44 | static void |
| 45 | nvc0_fifo_playlist_update(struct drm_device *dev) |
| 46 | { |
| 47 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 48 | struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem; |
| 49 | struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; |
| 50 | struct nvc0_fifo_priv *priv = pfifo->priv; |
| 51 | struct nouveau_gpuobj *cur; |
| 52 | int i, p; |
| 53 | |
| 54 | cur = priv->playlist[priv->cur_playlist]; |
| 55 | priv->cur_playlist = !priv->cur_playlist; |
| 56 | |
| 57 | for (i = 0, p = 0; i < 128; i++) { |
| 58 | if (!(nv_rd32(dev, 0x3004 + (i * 8)) & 1)) |
| 59 | continue; |
| 60 | nv_wo32(cur, p + 0, i); |
| 61 | nv_wo32(cur, p + 4, 0x00000004); |
| 62 | p += 8; |
| 63 | } |
| 64 | pinstmem->flush(dev); |
| 65 | |
| 66 | nv_wr32(dev, 0x002270, cur->vinst >> 12); |
| 67 | nv_wr32(dev, 0x002274, 0x01f00000 | (p >> 3)); |
| 68 | if (!nv_wait(dev, 0x00227c, 0x00100000, 0x00000000)) |
| 69 | NV_ERROR(dev, "PFIFO - playlist update failed\n"); |
| 70 | } |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 71 | |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 72 | int |
| 73 | nvc0_fifo_create_context(struct nouveau_channel *chan) |
| 74 | { |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 75 | struct drm_device *dev = chan->dev; |
| 76 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 77 | struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem; |
| 78 | struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; |
| 79 | struct nvc0_fifo_priv *priv = pfifo->priv; |
| 80 | struct nvc0_fifo_chan *fifoch; |
Ben Skeggs | 1233bd8 | 2011-04-13 13:55:17 +1000 | [diff] [blame] | 81 | u64 ib_virt = chan->pushbuf_base + chan->dma.ib_base * 4; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 82 | int ret; |
| 83 | |
| 84 | chan->fifo_priv = kzalloc(sizeof(*fifoch), GFP_KERNEL); |
| 85 | if (!chan->fifo_priv) |
| 86 | return -ENOMEM; |
| 87 | fifoch = chan->fifo_priv; |
| 88 | |
| 89 | /* allocate vram for control regs, map into polling area */ |
Ben Skeggs | 1233bd8 | 2011-04-13 13:55:17 +1000 | [diff] [blame] | 90 | ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0x1000, |
| 91 | NVOBJ_FLAG_ZERO_ALLOC, &fifoch->user); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 92 | if (ret) |
| 93 | goto error; |
| 94 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 95 | nouveau_vm_map_at(&priv->user_vma, chan->id * 0x1000, |
Ben Skeggs | 1233bd8 | 2011-04-13 13:55:17 +1000 | [diff] [blame] | 96 | *(struct nouveau_mem **)fifoch->user->node); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 97 | |
| 98 | chan->user = ioremap_wc(pci_resource_start(dev->pdev, 1) + |
| 99 | priv->user_vma.offset + (chan->id * 0x1000), |
| 100 | PAGE_SIZE); |
| 101 | if (!chan->user) { |
| 102 | ret = -ENOMEM; |
| 103 | goto error; |
| 104 | } |
| 105 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 106 | /* ramfc */ |
| 107 | ret = nouveau_gpuobj_new_fake(dev, chan->ramin->pinst, |
| 108 | chan->ramin->vinst, 0x100, |
| 109 | NVOBJ_FLAG_ZERO_ALLOC, &fifoch->ramfc); |
| 110 | if (ret) |
| 111 | goto error; |
| 112 | |
Ben Skeggs | 1233bd8 | 2011-04-13 13:55:17 +1000 | [diff] [blame] | 113 | nv_wo32(fifoch->ramfc, 0x08, lower_32_bits(fifoch->user->vinst)); |
| 114 | nv_wo32(fifoch->ramfc, 0x0c, upper_32_bits(fifoch->user->vinst)); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 115 | nv_wo32(fifoch->ramfc, 0x10, 0x0000face); |
| 116 | nv_wo32(fifoch->ramfc, 0x30, 0xfffff902); |
| 117 | nv_wo32(fifoch->ramfc, 0x48, lower_32_bits(ib_virt)); |
| 118 | nv_wo32(fifoch->ramfc, 0x4c, drm_order(chan->dma.ib_max + 1) << 16 | |
| 119 | upper_32_bits(ib_virt)); |
| 120 | nv_wo32(fifoch->ramfc, 0x54, 0x00000002); |
| 121 | nv_wo32(fifoch->ramfc, 0x84, 0x20400000); |
| 122 | nv_wo32(fifoch->ramfc, 0x94, 0x30000001); |
| 123 | nv_wo32(fifoch->ramfc, 0x9c, 0x00000100); |
| 124 | nv_wo32(fifoch->ramfc, 0xa4, 0x1f1f1f1f); |
| 125 | nv_wo32(fifoch->ramfc, 0xa8, 0x1f1f1f1f); |
| 126 | nv_wo32(fifoch->ramfc, 0xac, 0x0000001f); |
| 127 | nv_wo32(fifoch->ramfc, 0xb8, 0xf8000000); |
| 128 | nv_wo32(fifoch->ramfc, 0xf8, 0x10003080); /* 0x002310 */ |
| 129 | nv_wo32(fifoch->ramfc, 0xfc, 0x10000010); /* 0x002350 */ |
| 130 | pinstmem->flush(dev); |
| 131 | |
| 132 | nv_wr32(dev, 0x003000 + (chan->id * 8), 0xc0000000 | |
| 133 | (chan->ramin->vinst >> 12)); |
| 134 | nv_wr32(dev, 0x003004 + (chan->id * 8), 0x001f0001); |
| 135 | nvc0_fifo_playlist_update(dev); |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 136 | return 0; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 137 | |
| 138 | error: |
| 139 | pfifo->destroy_context(chan); |
| 140 | return ret; |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 141 | } |
| 142 | |
| 143 | void |
| 144 | nvc0_fifo_destroy_context(struct nouveau_channel *chan) |
| 145 | { |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 146 | struct drm_device *dev = chan->dev; |
| 147 | struct nvc0_fifo_chan *fifoch; |
| 148 | |
| 149 | nv_mask(dev, 0x003004 + (chan->id * 8), 0x00000001, 0x00000000); |
| 150 | nv_wr32(dev, 0x002634, chan->id); |
| 151 | if (!nv_wait(dev, 0x0002634, 0xffffffff, chan->id)) |
| 152 | NV_WARN(dev, "0x2634 != chid: 0x%08x\n", nv_rd32(dev, 0x2634)); |
| 153 | |
| 154 | nvc0_fifo_playlist_update(dev); |
| 155 | |
| 156 | nv_wr32(dev, 0x003000 + (chan->id * 8), 0x00000000); |
| 157 | |
| 158 | if (chan->user) { |
| 159 | iounmap(chan->user); |
| 160 | chan->user = NULL; |
| 161 | } |
| 162 | |
| 163 | fifoch = chan->fifo_priv; |
| 164 | chan->fifo_priv = NULL; |
| 165 | if (!fifoch) |
| 166 | return; |
| 167 | |
| 168 | nouveau_gpuobj_ref(NULL, &fifoch->ramfc); |
Ben Skeggs | 1233bd8 | 2011-04-13 13:55:17 +1000 | [diff] [blame] | 169 | nouveau_gpuobj_ref(NULL, &fifoch->user); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 170 | kfree(fifoch); |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 171 | } |
| 172 | |
| 173 | int |
| 174 | nvc0_fifo_load_context(struct nouveau_channel *chan) |
| 175 | { |
| 176 | return 0; |
| 177 | } |
| 178 | |
| 179 | int |
| 180 | nvc0_fifo_unload_context(struct drm_device *dev) |
| 181 | { |
Ben Skeggs | 7a5c23d | 2011-04-12 18:51:39 +1000 | [diff] [blame] | 182 | int i; |
| 183 | |
| 184 | for (i = 0; i < 128; i++) { |
Ben Skeggs | 068da16 | 2011-05-24 11:54:42 +1000 | [diff] [blame] | 185 | if (!(nv_rd32(dev, 0x003004 + (i * 8)) & 1)) |
Ben Skeggs | 7a5c23d | 2011-04-12 18:51:39 +1000 | [diff] [blame] | 186 | continue; |
| 187 | |
Ben Skeggs | 068da16 | 2011-05-24 11:54:42 +1000 | [diff] [blame] | 188 | nv_mask(dev, 0x003004 + (i * 8), 0x00000001, 0x00000000); |
Ben Skeggs | 7a5c23d | 2011-04-12 18:51:39 +1000 | [diff] [blame] | 189 | nv_wr32(dev, 0x002634, i); |
| 190 | if (!nv_wait(dev, 0x002634, 0xffffffff, i)) { |
| 191 | NV_INFO(dev, "PFIFO: kick ch %d failed: 0x%08x\n", |
| 192 | i, nv_rd32(dev, 0x002634)); |
| 193 | return -EBUSY; |
| 194 | } |
| 195 | } |
| 196 | |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 197 | return 0; |
| 198 | } |
| 199 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 200 | static void |
| 201 | nvc0_fifo_destroy(struct drm_device *dev) |
| 202 | { |
| 203 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 204 | struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; |
| 205 | struct nvc0_fifo_priv *priv; |
| 206 | |
| 207 | priv = pfifo->priv; |
| 208 | if (!priv) |
| 209 | return; |
| 210 | |
| 211 | nouveau_vm_put(&priv->user_vma); |
| 212 | nouveau_gpuobj_ref(NULL, &priv->playlist[1]); |
| 213 | nouveau_gpuobj_ref(NULL, &priv->playlist[0]); |
| 214 | kfree(priv); |
| 215 | } |
| 216 | |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 217 | void |
| 218 | nvc0_fifo_takedown(struct drm_device *dev) |
| 219 | { |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 220 | nv_wr32(dev, 0x002140, 0x00000000); |
| 221 | nvc0_fifo_destroy(dev); |
| 222 | } |
| 223 | |
| 224 | static int |
| 225 | nvc0_fifo_create(struct drm_device *dev) |
| 226 | { |
| 227 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 228 | struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; |
| 229 | struct nvc0_fifo_priv *priv; |
| 230 | int ret; |
| 231 | |
| 232 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
| 233 | if (!priv) |
| 234 | return -ENOMEM; |
| 235 | pfifo->priv = priv; |
| 236 | |
| 237 | ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0x1000, 0, |
| 238 | &priv->playlist[0]); |
| 239 | if (ret) |
| 240 | goto error; |
| 241 | |
| 242 | ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0x1000, 0, |
| 243 | &priv->playlist[1]); |
| 244 | if (ret) |
| 245 | goto error; |
| 246 | |
| 247 | ret = nouveau_vm_get(dev_priv->bar1_vm, pfifo->channels * 0x1000, |
| 248 | 12, NV_MEM_ACCESS_RW, &priv->user_vma); |
| 249 | if (ret) |
| 250 | goto error; |
| 251 | |
| 252 | nouveau_irq_register(dev, 8, nvc0_fifo_isr); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 253 | return 0; |
| 254 | |
| 255 | error: |
| 256 | nvc0_fifo_destroy(dev); |
| 257 | return ret; |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 258 | } |
| 259 | |
| 260 | int |
| 261 | nvc0_fifo_init(struct drm_device *dev) |
| 262 | { |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 263 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 264 | struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; |
Ben Skeggs | 0638df4 | 2011-04-12 19:38:06 +1000 | [diff] [blame] | 265 | struct nouveau_channel *chan; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 266 | struct nvc0_fifo_priv *priv; |
| 267 | int ret, i; |
| 268 | |
| 269 | if (!pfifo->priv) { |
| 270 | ret = nvc0_fifo_create(dev); |
| 271 | if (ret) |
| 272 | return ret; |
| 273 | } |
| 274 | priv = pfifo->priv; |
| 275 | |
| 276 | /* reset PFIFO, enable all available PSUBFIFO areas */ |
| 277 | nv_mask(dev, 0x000200, 0x00000100, 0x00000000); |
| 278 | nv_mask(dev, 0x000200, 0x00000100, 0x00000100); |
| 279 | nv_wr32(dev, 0x000204, 0xffffffff); |
| 280 | nv_wr32(dev, 0x002204, 0xffffffff); |
| 281 | |
Ben Skeggs | ec9c088 | 2010-12-31 12:10:49 +1000 | [diff] [blame] | 282 | priv->spoon_nr = hweight32(nv_rd32(dev, 0x002204)); |
| 283 | NV_DEBUG(dev, "PFIFO: %d subfifo(s)\n", priv->spoon_nr); |
| 284 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 285 | /* assign engines to subfifos */ |
Ben Skeggs | ec9c088 | 2010-12-31 12:10:49 +1000 | [diff] [blame] | 286 | if (priv->spoon_nr >= 3) { |
| 287 | nv_wr32(dev, 0x002208, ~(1 << 0)); /* PGRAPH */ |
| 288 | nv_wr32(dev, 0x00220c, ~(1 << 1)); /* PVP */ |
| 289 | nv_wr32(dev, 0x002210, ~(1 << 1)); /* PPP */ |
| 290 | nv_wr32(dev, 0x002214, ~(1 << 1)); /* PBSP */ |
| 291 | nv_wr32(dev, 0x002218, ~(1 << 2)); /* PCE0 */ |
| 292 | nv_wr32(dev, 0x00221c, ~(1 << 1)); /* PCE1 */ |
| 293 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 294 | |
| 295 | /* PSUBFIFO[n] */ |
Ben Skeggs | 3dcbb02 | 2011-08-25 15:53:57 +1000 | [diff] [blame] | 296 | for (i = 0; i < priv->spoon_nr; i++) { |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 297 | nv_mask(dev, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); |
| 298 | nv_wr32(dev, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */ |
| 299 | nv_wr32(dev, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTR_EN */ |
| 300 | } |
| 301 | |
| 302 | nv_mask(dev, 0x002200, 0x00000001, 0x00000001); |
| 303 | nv_wr32(dev, 0x002254, 0x10000000 | priv->user_vma.offset >> 12); |
| 304 | |
| 305 | nv_wr32(dev, 0x002a00, 0xffffffff); /* clears PFIFO.INTR bit 30 */ |
| 306 | nv_wr32(dev, 0x002100, 0xffffffff); |
| 307 | nv_wr32(dev, 0x002140, 0xbfffffff); |
Ben Skeggs | 0638df4 | 2011-04-12 19:38:06 +1000 | [diff] [blame] | 308 | |
| 309 | /* restore PFIFO context table */ |
| 310 | for (i = 0; i < 128; i++) { |
| 311 | chan = dev_priv->channels.ptr[i]; |
| 312 | if (!chan || !chan->fifo_priv) |
| 313 | continue; |
| 314 | |
| 315 | nv_wr32(dev, 0x003000 + (i * 8), 0xc0000000 | |
| 316 | (chan->ramin->vinst >> 12)); |
| 317 | nv_wr32(dev, 0x003004 + (i * 8), 0x001f0001); |
| 318 | } |
| 319 | nvc0_fifo_playlist_update(dev); |
| 320 | |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 321 | return 0; |
| 322 | } |
| 323 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 324 | struct nouveau_enum nvc0_fifo_fault_unit[] = { |
Ben Skeggs | 7a31347 | 2011-03-29 00:52:59 +1000 | [diff] [blame] | 325 | { 0x00, "PGRAPH" }, |
| 326 | { 0x03, "PEEPHOLE" }, |
| 327 | { 0x04, "BAR1" }, |
| 328 | { 0x05, "BAR3" }, |
| 329 | { 0x07, "PFIFO" }, |
| 330 | { 0x10, "PBSP" }, |
| 331 | { 0x11, "PPPP" }, |
| 332 | { 0x13, "PCOUNTER" }, |
| 333 | { 0x14, "PVP" }, |
| 334 | { 0x15, "PCOPY0" }, |
| 335 | { 0x16, "PCOPY1" }, |
| 336 | { 0x17, "PDAEMON" }, |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 337 | {} |
| 338 | }; |
| 339 | |
| 340 | struct nouveau_enum nvc0_fifo_fault_reason[] = { |
Ben Skeggs | e296663 | 2011-03-29 08:57:34 +1000 | [diff] [blame] | 341 | { 0x00, "PT_NOT_PRESENT" }, |
| 342 | { 0x01, "PT_TOO_SHORT" }, |
| 343 | { 0x02, "PAGE_NOT_PRESENT" }, |
| 344 | { 0x03, "VM_LIMIT_EXCEEDED" }, |
| 345 | { 0x04, "NO_CHANNEL" }, |
| 346 | { 0x05, "PAGE_SYSTEM_ONLY" }, |
| 347 | { 0x06, "PAGE_READ_ONLY" }, |
| 348 | { 0x0a, "COMPRESSED_SYSRAM" }, |
| 349 | { 0x0c, "INVALID_STORAGE_TYPE" }, |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 350 | {} |
| 351 | }; |
| 352 | |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 353 | struct nouveau_enum nvc0_fifo_fault_hubclient[] = { |
| 354 | { 0x01, "PCOPY0" }, |
| 355 | { 0x02, "PCOPY1" }, |
| 356 | { 0x04, "DISPATCH" }, |
| 357 | { 0x05, "CTXCTL" }, |
| 358 | { 0x06, "PFIFO" }, |
| 359 | { 0x07, "BAR_READ" }, |
| 360 | { 0x08, "BAR_WRITE" }, |
| 361 | { 0x0b, "PVP" }, |
| 362 | { 0x0c, "PPPP" }, |
| 363 | { 0x0d, "PBSP" }, |
| 364 | { 0x11, "PCOUNTER" }, |
| 365 | { 0x12, "PDAEMON" }, |
| 366 | { 0x14, "CCACHE" }, |
| 367 | { 0x15, "CCACHE_POST" }, |
| 368 | {} |
| 369 | }; |
| 370 | |
| 371 | struct nouveau_enum nvc0_fifo_fault_gpcclient[] = { |
| 372 | { 0x01, "TEX" }, |
| 373 | { 0x0c, "ESETUP" }, |
| 374 | { 0x0e, "CTXCTL" }, |
| 375 | { 0x0f, "PROP" }, |
| 376 | {} |
| 377 | }; |
| 378 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 379 | struct nouveau_bitfield nvc0_fifo_subfifo_intr[] = { |
| 380 | /* { 0x00008000, "" } seen with null ib push */ |
| 381 | { 0x00200000, "ILLEGAL_MTHD" }, |
| 382 | { 0x00800000, "EMPTY_SUBC" }, |
| 383 | {} |
| 384 | }; |
| 385 | |
| 386 | static void |
| 387 | nvc0_fifo_isr_vm_fault(struct drm_device *dev, int unit) |
| 388 | { |
| 389 | u32 inst = nv_rd32(dev, 0x2800 + (unit * 0x10)); |
| 390 | u32 valo = nv_rd32(dev, 0x2804 + (unit * 0x10)); |
| 391 | u32 vahi = nv_rd32(dev, 0x2808 + (unit * 0x10)); |
| 392 | u32 stat = nv_rd32(dev, 0x280c + (unit * 0x10)); |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 393 | u32 client = (stat & 0x00001f00) >> 8; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 394 | |
| 395 | NV_INFO(dev, "PFIFO: %s fault at 0x%010llx [", |
| 396 | (stat & 0x00000080) ? "write" : "read", (u64)vahi << 32 | valo); |
| 397 | nouveau_enum_print(nvc0_fifo_fault_reason, stat & 0x0000000f); |
| 398 | printk("] from "); |
| 399 | nouveau_enum_print(nvc0_fifo_fault_unit, unit); |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 400 | if (stat & 0x00000040) { |
| 401 | printk("/"); |
| 402 | nouveau_enum_print(nvc0_fifo_fault_hubclient, client); |
| 403 | } else { |
| 404 | printk("/GPC%d/", (stat & 0x1f000000) >> 24); |
| 405 | nouveau_enum_print(nvc0_fifo_fault_gpcclient, client); |
| 406 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 407 | printk(" on channel 0x%010llx\n", (u64)inst << 12); |
| 408 | } |
| 409 | |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 410 | static int |
| 411 | nvc0_fifo_page_flip(struct drm_device *dev, u32 chid) |
| 412 | { |
| 413 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 414 | struct nouveau_channel *chan = NULL; |
| 415 | unsigned long flags; |
| 416 | int ret = -EINVAL; |
| 417 | |
| 418 | spin_lock_irqsave(&dev_priv->channels.lock, flags); |
| 419 | if (likely(chid >= 0 && chid < dev_priv->engine.fifo.channels)) { |
| 420 | chan = dev_priv->channels.ptr[chid]; |
| 421 | if (likely(chan)) |
| 422 | ret = nouveau_finish_page_flip(chan, NULL); |
| 423 | } |
| 424 | spin_unlock_irqrestore(&dev_priv->channels.lock, flags); |
| 425 | return ret; |
| 426 | } |
| 427 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 428 | static void |
| 429 | nvc0_fifo_isr_subfifo_intr(struct drm_device *dev, int unit) |
| 430 | { |
| 431 | u32 stat = nv_rd32(dev, 0x040108 + (unit * 0x2000)); |
| 432 | u32 addr = nv_rd32(dev, 0x0400c0 + (unit * 0x2000)); |
| 433 | u32 data = nv_rd32(dev, 0x0400c4 + (unit * 0x2000)); |
| 434 | u32 chid = nv_rd32(dev, 0x040120 + (unit * 0x2000)) & 0x7f; |
| 435 | u32 subc = (addr & 0x00070000); |
| 436 | u32 mthd = (addr & 0x00003ffc); |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 437 | u32 show = stat; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 438 | |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 439 | if (stat & 0x00200000) { |
| 440 | if (mthd == 0x0054) { |
| 441 | if (!nvc0_fifo_page_flip(dev, chid)) |
| 442 | show &= ~0x00200000; |
| 443 | } |
| 444 | } |
| 445 | |
| 446 | if (show) { |
| 447 | NV_INFO(dev, "PFIFO%d:", unit); |
| 448 | nouveau_bitfield_print(nvc0_fifo_subfifo_intr, show); |
| 449 | NV_INFO(dev, "PFIFO%d: ch %d subc %d mthd 0x%04x data 0x%08x\n", |
| 450 | unit, chid, subc, mthd, data); |
| 451 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 452 | |
| 453 | nv_wr32(dev, 0x0400c0 + (unit * 0x2000), 0x80600008); |
| 454 | nv_wr32(dev, 0x040108 + (unit * 0x2000), stat); |
| 455 | } |
| 456 | |
| 457 | static void |
| 458 | nvc0_fifo_isr(struct drm_device *dev) |
| 459 | { |
| 460 | u32 stat = nv_rd32(dev, 0x002100); |
| 461 | |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 462 | if (stat & 0x00000100) { |
| 463 | NV_INFO(dev, "PFIFO: unknown status 0x00000100\n"); |
| 464 | nv_wr32(dev, 0x002100, 0x00000100); |
| 465 | stat &= ~0x00000100; |
| 466 | } |
| 467 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 468 | if (stat & 0x10000000) { |
| 469 | u32 units = nv_rd32(dev, 0x00259c); |
| 470 | u32 u = units; |
| 471 | |
| 472 | while (u) { |
| 473 | int i = ffs(u) - 1; |
| 474 | nvc0_fifo_isr_vm_fault(dev, i); |
| 475 | u &= ~(1 << i); |
| 476 | } |
| 477 | |
| 478 | nv_wr32(dev, 0x00259c, units); |
| 479 | stat &= ~0x10000000; |
| 480 | } |
| 481 | |
| 482 | if (stat & 0x20000000) { |
| 483 | u32 units = nv_rd32(dev, 0x0025a0); |
| 484 | u32 u = units; |
| 485 | |
| 486 | while (u) { |
| 487 | int i = ffs(u) - 1; |
| 488 | nvc0_fifo_isr_subfifo_intr(dev, i); |
| 489 | u &= ~(1 << i); |
| 490 | } |
| 491 | |
| 492 | nv_wr32(dev, 0x0025a0, units); |
| 493 | stat &= ~0x20000000; |
| 494 | } |
| 495 | |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 496 | if (stat & 0x40000000) { |
| 497 | NV_INFO(dev, "PFIFO: unknown status 0x40000000\n"); |
| 498 | nv_mask(dev, 0x002a00, 0x00000000, 0x00000000); |
| 499 | stat &= ~0x40000000; |
| 500 | } |
| 501 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 502 | if (stat) { |
| 503 | NV_INFO(dev, "PFIFO: unhandled status 0x%08x\n", stat); |
| 504 | nv_wr32(dev, 0x002100, stat); |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 505 | nv_wr32(dev, 0x002140, 0); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 506 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 507 | } |