Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (C) 2012 Ben Skeggs. |
| 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining |
| 6 | * a copy of this software and associated documentation files (the |
| 7 | * "Software"), to deal in the Software without restriction, including |
| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
| 9 | * distribute, sublicense, and/or sell copies of the Software, and to |
| 10 | * permit persons to whom the Software is furnished to do so, subject to |
| 11 | * the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the |
| 14 | * next paragraph) shall be included in all copies or substantial |
| 15 | * portions of the Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 18 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 20 | * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
| 21 | * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
| 22 | * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
| 23 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 24 | * |
| 25 | */ |
| 26 | |
| 27 | #include "drmP.h" |
| 28 | #include "drm.h" |
| 29 | #include "nouveau_drv.h" |
| 30 | #include "nouveau_fifo.h" |
| 31 | #include "nouveau_ramht.h" |
| 32 | #include "nouveau_vm.h" |
| 33 | |
| 34 | struct nv84_fifo_priv { |
| 35 | struct nouveau_fifo_priv base; |
| 36 | struct nouveau_gpuobj *playlist[2]; |
| 37 | int cur_playlist; |
| 38 | }; |
| 39 | |
| 40 | struct nv84_fifo_chan { |
| 41 | struct nouveau_fifo_chan base; |
| 42 | struct nouveau_gpuobj *ramfc; |
| 43 | struct nouveau_gpuobj *cache; |
| 44 | }; |
| 45 | |
| 46 | static int |
| 47 | nv84_fifo_context_new(struct nouveau_channel *chan, int engine) |
| 48 | { |
| 49 | struct nv84_fifo_priv *priv = nv_engine(chan->dev, engine); |
| 50 | struct nv84_fifo_chan *fctx; |
| 51 | struct drm_device *dev = chan->dev; |
| 52 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 53 | u64 ib_offset = chan->pushbuf_base + chan->dma.ib_base * 4; |
| 54 | u64 instance; |
| 55 | unsigned long flags; |
| 56 | int ret; |
| 57 | |
| 58 | fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL); |
| 59 | if (!fctx) |
| 60 | return -ENOMEM; |
| 61 | atomic_inc(&chan->vm->engref[engine]); |
| 62 | |
| 63 | chan->user = ioremap(pci_resource_start(dev->pdev, 0) + |
| 64 | NV50_USER(chan->id), PAGE_SIZE); |
| 65 | if (!chan->user) { |
| 66 | ret = -ENOMEM; |
| 67 | goto error; |
| 68 | } |
| 69 | |
| 70 | ret = nouveau_gpuobj_new(dev, chan, 256, 256, NVOBJ_FLAG_ZERO_ALLOC | |
| 71 | NVOBJ_FLAG_ZERO_FREE, &fctx->ramfc); |
| 72 | if (ret) |
| 73 | goto error; |
| 74 | |
| 75 | instance = fctx->ramfc->vinst >> 8; |
| 76 | |
| 77 | ret = nouveau_gpuobj_new(dev, chan, 4096, 1024, 0, &fctx->cache); |
| 78 | if (ret) |
| 79 | goto error; |
| 80 | |
| 81 | nv_wo32(fctx->ramfc, 0x3c, 0x403f6078); |
| 82 | nv_wo32(fctx->ramfc, 0x40, 0x00000000); |
| 83 | nv_wo32(fctx->ramfc, 0x44, 0x01003fff); |
| 84 | nv_wo32(fctx->ramfc, 0x48, chan->pushbuf->cinst >> 4); |
| 85 | nv_wo32(fctx->ramfc, 0x50, lower_32_bits(ib_offset)); |
| 86 | nv_wo32(fctx->ramfc, 0x54, upper_32_bits(ib_offset) | |
| 87 | drm_order(chan->dma.ib_max + 1) << 16); |
| 88 | nv_wo32(fctx->ramfc, 0x60, 0x7fffffff); |
| 89 | nv_wo32(fctx->ramfc, 0x78, 0x00000000); |
| 90 | nv_wo32(fctx->ramfc, 0x7c, 0x30000001); |
| 91 | nv_wo32(fctx->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | |
| 92 | (4 << 24) /* SEARCH_FULL */ | |
| 93 | (chan->ramht->gpuobj->cinst >> 4)); |
| 94 | nv_wo32(fctx->ramfc, 0x88, fctx->cache->vinst >> 10); |
| 95 | nv_wo32(fctx->ramfc, 0x98, chan->ramin->vinst >> 12); |
| 96 | |
| 97 | nv_wo32(chan->ramin, 0x00, chan->id); |
| 98 | nv_wo32(chan->ramin, 0x04, fctx->ramfc->vinst >> 8); |
| 99 | |
| 100 | dev_priv->engine.instmem.flush(dev); |
| 101 | |
| 102 | spin_lock_irqsave(&dev_priv->context_switch_lock, flags); |
| 103 | nv_wr32(dev, 0x002600 + (chan->id * 4), 0x80000000 | instance); |
| 104 | nv50_fifo_playlist_update(dev); |
| 105 | spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); |
| 106 | |
| 107 | error: |
| 108 | if (ret) |
| 109 | priv->base.base.context_del(chan, engine); |
| 110 | return ret; |
| 111 | } |
| 112 | |
| 113 | static void |
| 114 | nv84_fifo_context_del(struct nouveau_channel *chan, int engine) |
| 115 | { |
| 116 | struct nv84_fifo_chan *fctx = chan->engctx[engine]; |
| 117 | struct drm_device *dev = chan->dev; |
| 118 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 119 | unsigned long flags; |
| 120 | |
| 121 | /* remove channel from playlist, will context switch if active */ |
| 122 | spin_lock_irqsave(&dev_priv->context_switch_lock, flags); |
| 123 | nv_mask(dev, 0x002600 + (chan->id * 4), 0x80000000, 0x00000000); |
| 124 | nv50_fifo_playlist_update(dev); |
| 125 | |
| 126 | /* tell any engines on this channel to unload their contexts */ |
| 127 | nv_wr32(dev, 0x0032fc, chan->ramin->vinst >> 12); |
| 128 | if (!nv_wait_ne(dev, 0x0032fc, 0xffffffff, 0xffffffff)) |
| 129 | NV_INFO(dev, "PFIFO: channel %d unload timeout\n", chan->id); |
| 130 | |
| 131 | nv_wr32(dev, 0x002600 + (chan->id * 4), 0x00000000); |
| 132 | spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); |
| 133 | |
| 134 | /* clean up */ |
| 135 | if (chan->user) { |
| 136 | iounmap(chan->user); |
| 137 | chan->user = NULL; |
| 138 | } |
| 139 | |
| 140 | nouveau_gpuobj_ref(NULL, &fctx->ramfc); |
| 141 | nouveau_gpuobj_ref(NULL, &fctx->cache); |
| 142 | |
| 143 | atomic_dec(&chan->vm->engref[engine]); |
| 144 | chan->engctx[engine] = NULL; |
| 145 | kfree(fctx); |
| 146 | } |
| 147 | |
| 148 | static int |
| 149 | nv84_fifo_init(struct drm_device *dev, int engine) |
| 150 | { |
| 151 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 152 | struct nv84_fifo_chan *fctx; |
| 153 | u32 instance; |
| 154 | int i; |
| 155 | |
| 156 | nv_mask(dev, 0x000200, 0x00000100, 0x00000000); |
| 157 | nv_mask(dev, 0x000200, 0x00000100, 0x00000100); |
| 158 | nv_wr32(dev, 0x00250c, 0x6f3cfc34); |
| 159 | nv_wr32(dev, 0x002044, 0x01003fff); |
| 160 | |
| 161 | nv_wr32(dev, 0x002100, 0xffffffff); |
| 162 | nv_wr32(dev, 0x002140, 0xffffffff); |
| 163 | |
| 164 | for (i = 0; i < 128; i++) { |
| 165 | struct nouveau_channel *chan = dev_priv->channels.ptr[i]; |
| 166 | if (chan && (fctx = chan->engctx[engine])) |
| 167 | instance = 0x80000000 | fctx->ramfc->vinst >> 8; |
| 168 | else |
| 169 | instance = 0x00000000; |
| 170 | nv_wr32(dev, 0x002600 + (i * 4), instance); |
| 171 | } |
| 172 | |
| 173 | nv50_fifo_playlist_update(dev); |
| 174 | |
| 175 | nv_wr32(dev, 0x003200, 1); |
| 176 | nv_wr32(dev, 0x003250, 1); |
| 177 | nv_wr32(dev, 0x002500, 1); |
| 178 | return 0; |
| 179 | } |
| 180 | |
| 181 | static int |
| 182 | nv84_fifo_fini(struct drm_device *dev, int engine, bool suspend) |
| 183 | { |
| 184 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 185 | struct nv84_fifo_priv *priv = nv_engine(dev, engine); |
| 186 | int i; |
| 187 | |
| 188 | /* set playlist length to zero, fifo will unload context */ |
| 189 | nv_wr32(dev, 0x0032ec, 0); |
| 190 | |
| 191 | /* tell all connected engines to unload their contexts */ |
| 192 | for (i = 0; i < priv->base.channels; i++) { |
| 193 | struct nouveau_channel *chan = dev_priv->channels.ptr[i]; |
| 194 | if (chan) |
| 195 | nv_wr32(dev, 0x0032fc, chan->ramin->vinst >> 12); |
| 196 | if (!nv_wait_ne(dev, 0x0032fc, 0xffffffff, 0xffffffff)) { |
| 197 | NV_INFO(dev, "PFIFO: channel %d unload timeout\n", i); |
| 198 | return -EBUSY; |
| 199 | } |
| 200 | } |
| 201 | |
| 202 | nv_wr32(dev, 0x002140, 0); |
| 203 | return 0; |
| 204 | } |
| 205 | |
| 206 | int |
| 207 | nv84_fifo_create(struct drm_device *dev) |
| 208 | { |
| 209 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 210 | struct nv84_fifo_priv *priv; |
| 211 | int ret; |
| 212 | |
| 213 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
| 214 | if (!priv) |
| 215 | return -ENOMEM; |
| 216 | |
| 217 | priv->base.base.destroy = nv50_fifo_destroy; |
| 218 | priv->base.base.init = nv84_fifo_init; |
| 219 | priv->base.base.fini = nv84_fifo_fini; |
| 220 | priv->base.base.context_new = nv84_fifo_context_new; |
| 221 | priv->base.base.context_del = nv84_fifo_context_del; |
| 222 | priv->base.base.tlb_flush = nv50_fifo_tlb_flush; |
| 223 | priv->base.channels = 127; |
| 224 | dev_priv->eng[NVOBJ_ENGINE_FIFO] = &priv->base.base; |
| 225 | |
| 226 | ret = nouveau_gpuobj_new(dev, NULL, priv->base.channels * 4, 0x1000, |
| 227 | NVOBJ_FLAG_ZERO_ALLOC, &priv->playlist[0]); |
| 228 | if (ret) |
| 229 | goto error; |
| 230 | |
| 231 | ret = nouveau_gpuobj_new(dev, NULL, priv->base.channels * 4, 0x1000, |
| 232 | NVOBJ_FLAG_ZERO_ALLOC, &priv->playlist[1]); |
| 233 | if (ret) |
| 234 | goto error; |
| 235 | |
| 236 | nouveau_irq_register(dev, 8, nv04_fifo_isr); |
| 237 | error: |
| 238 | if (ret) |
| 239 | priv->base.base.destroy(dev, NVOBJ_ENGINE_FIFO); |
| 240 | return ret; |
| 241 | } |