Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * arch/arm/mach-u300/core.c |
| 4 | * |
| 5 | * |
Linus Walleij | ec8f125 | 2010-08-13 11:31:59 +0200 | [diff] [blame] | 6 | * Copyright (C) 2007-2010 ST-Ericsson SA |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 7 | * License terms: GNU General Public License (GPL) version 2 |
| 8 | * Core platform support, IRQ handling and device definitions. |
| 9 | * Author: Linus Walleij <linus.walleij@stericsson.com> |
| 10 | */ |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/spinlock.h> |
| 14 | #include <linux/interrupt.h> |
| 15 | #include <linux/bitops.h> |
| 16 | #include <linux/device.h> |
| 17 | #include <linux/mm.h> |
| 18 | #include <linux/termios.h> |
Linus Walleij | ec8f125 | 2010-08-13 11:31:59 +0200 | [diff] [blame] | 19 | #include <linux/dmaengine.h> |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 20 | #include <linux/amba/bus.h> |
Linus Walleij | ec8f125 | 2010-08-13 11:31:59 +0200 | [diff] [blame] | 21 | #include <linux/amba/serial.h> |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/gpio.h> |
Linus Walleij | b7276b2 | 2010-08-05 07:58:58 +0100 | [diff] [blame] | 24 | #include <linux/clk.h> |
| 25 | #include <linux/err.h> |
Linus Walleij | 93ac5a5 | 2010-09-13 00:35:37 +0200 | [diff] [blame] | 26 | #include <linux/mtd/nand.h> |
| 27 | #include <linux/mtd/fsmc.h> |
Linus Walleij | 98da352 | 2011-05-02 20:54:38 +0200 | [diff] [blame] | 28 | #include <linux/pinctrl/machine.h> |
| 29 | #include <linux/pinctrl/pinmux.h> |
Jon Medhurst | d70a596 | 2011-08-04 15:41:42 +0100 | [diff] [blame] | 30 | #include <linux/dma-mapping.h> |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 31 | |
| 32 | #include <asm/types.h> |
| 33 | #include <asm/setup.h> |
| 34 | #include <asm/memory.h> |
| 35 | #include <asm/hardware/vic.h> |
| 36 | #include <asm/mach/map.h> |
| 37 | #include <asm/mach/irq.h> |
| 38 | |
Linus Walleij | 93ac5a5 | 2010-09-13 00:35:37 +0200 | [diff] [blame] | 39 | #include <mach/coh901318.h> |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 40 | #include <mach/hardware.h> |
| 41 | #include <mach/syscon.h> |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 42 | #include <mach/dma_channels.h> |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 43 | #include <mach/gpio-u300.h> |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 44 | |
| 45 | #include "clock.h" |
| 46 | #include "mmc.h" |
Linus Walleij | c7c8c78 | 2009-08-14 10:59:05 +0100 | [diff] [blame] | 47 | #include "spi.h" |
Linus Walleij | 6be2a0c | 2009-08-13 21:42:01 +0100 | [diff] [blame] | 48 | #include "i2c.h" |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 49 | |
| 50 | /* |
| 51 | * Static I/O mappings that are needed for booting the U300 platforms. The |
| 52 | * only things we need are the areas where we find the timer, syscon and |
| 53 | * intcon, since the remaining device drivers will map their own memory |
| 54 | * physical to virtual as the need arise. |
| 55 | */ |
| 56 | static struct map_desc u300_io_desc[] __initdata = { |
| 57 | { |
| 58 | .virtual = U300_SLOW_PER_VIRT_BASE, |
| 59 | .pfn = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE), |
| 60 | .length = SZ_64K, |
| 61 | .type = MT_DEVICE, |
| 62 | }, |
| 63 | { |
| 64 | .virtual = U300_AHB_PER_VIRT_BASE, |
| 65 | .pfn = __phys_to_pfn(U300_AHB_PER_PHYS_BASE), |
| 66 | .length = SZ_32K, |
| 67 | .type = MT_DEVICE, |
| 68 | }, |
| 69 | { |
| 70 | .virtual = U300_FAST_PER_VIRT_BASE, |
| 71 | .pfn = __phys_to_pfn(U300_FAST_PER_PHYS_BASE), |
| 72 | .length = SZ_32K, |
| 73 | .type = MT_DEVICE, |
| 74 | }, |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 75 | }; |
| 76 | |
| 77 | void __init u300_map_io(void) |
| 78 | { |
| 79 | iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc)); |
Jon Medhurst | d70a596 | 2011-08-04 15:41:42 +0100 | [diff] [blame] | 80 | /* We enable a real big DMA buffer if need be. */ |
| 81 | init_consistent_dma_size(SZ_4M); |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 82 | } |
| 83 | |
| 84 | /* |
| 85 | * Declaration of devices found on the U300 board and |
| 86 | * their respective memory locations. |
| 87 | */ |
Linus Walleij | ec8f125 | 2010-08-13 11:31:59 +0200 | [diff] [blame] | 88 | |
| 89 | static struct amba_pl011_data uart0_plat_data = { |
| 90 | #ifdef CONFIG_COH901318 |
| 91 | .dma_filter = coh901318_filter_id, |
| 92 | .dma_rx_param = (void *) U300_DMA_UART0_RX, |
| 93 | .dma_tx_param = (void *) U300_DMA_UART0_TX, |
| 94 | #endif |
| 95 | }; |
| 96 | |
Russell King | 6db2a45 | 2011-12-18 15:26:38 +0000 | [diff] [blame] | 97 | /* Slow device at 0x3000 offset */ |
| 98 | static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE, |
| 99 | { IRQ_U300_UART0 }, &uart0_plat_data); |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 100 | |
| 101 | /* The U335 have an additional UART1 on the APP CPU */ |
| 102 | #ifdef CONFIG_MACH_U300_BS335 |
Linus Walleij | ec8f125 | 2010-08-13 11:31:59 +0200 | [diff] [blame] | 103 | static struct amba_pl011_data uart1_plat_data = { |
| 104 | #ifdef CONFIG_COH901318 |
| 105 | .dma_filter = coh901318_filter_id, |
| 106 | .dma_rx_param = (void *) U300_DMA_UART1_RX, |
| 107 | .dma_tx_param = (void *) U300_DMA_UART1_TX, |
| 108 | #endif |
| 109 | }; |
| 110 | |
Russell King | 6db2a45 | 2011-12-18 15:26:38 +0000 | [diff] [blame] | 111 | /* Fast device at 0x7000 offset */ |
| 112 | static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE, |
| 113 | { IRQ_U300_UART1 }, &uart1_plat_data); |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 114 | #endif |
| 115 | |
Russell King | 6db2a45 | 2011-12-18 15:26:38 +0000 | [diff] [blame] | 116 | /* AHB device at 0x4000 offset */ |
| 117 | static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL); |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 118 | |
| 119 | |
| 120 | /* |
| 121 | * Everything within this next ifdef deals with external devices connected to |
| 122 | * the APP SPI bus. |
| 123 | */ |
Russell King | 6db2a45 | 2011-12-18 15:26:38 +0000 | [diff] [blame] | 124 | /* Fast device at 0x6000 offset */ |
| 125 | static AMBA_APB_DEVICE(pl022, "pl022", 0, U300_SPI_BASE, |
| 126 | { IRQ_U300_SPI }, NULL); |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 127 | |
Russell King | 6db2a45 | 2011-12-18 15:26:38 +0000 | [diff] [blame] | 128 | /* Fast device at 0x1000 offset */ |
| 129 | #define U300_MMCSD_IRQS { IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 } |
| 130 | |
| 131 | static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE, |
| 132 | U300_MMCSD_IRQS, NULL); |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 133 | |
| 134 | /* |
| 135 | * The order of device declaration may be important, since some devices |
| 136 | * have dependencies on other devices being initialized first. |
| 137 | */ |
| 138 | static struct amba_device *amba_devs[] __initdata = { |
| 139 | &uart0_device, |
| 140 | #ifdef CONFIG_MACH_U300_BS335 |
| 141 | &uart1_device, |
| 142 | #endif |
| 143 | &pl022_device, |
| 144 | &pl172_device, |
| 145 | &mmcsd_device, |
| 146 | }; |
| 147 | |
| 148 | /* Here follows a list of all hw resources that the platform devices |
| 149 | * allocate. Note, clock dependencies are not included |
| 150 | */ |
| 151 | |
| 152 | static struct resource gpio_resources[] = { |
| 153 | { |
| 154 | .start = U300_GPIO_BASE, |
| 155 | .end = (U300_GPIO_BASE + SZ_4K - 1), |
| 156 | .flags = IORESOURCE_MEM, |
| 157 | }, |
| 158 | { |
| 159 | .name = "gpio0", |
| 160 | .start = IRQ_U300_GPIO_PORT0, |
| 161 | .end = IRQ_U300_GPIO_PORT0, |
| 162 | .flags = IORESOURCE_IRQ, |
| 163 | }, |
| 164 | { |
| 165 | .name = "gpio1", |
| 166 | .start = IRQ_U300_GPIO_PORT1, |
| 167 | .end = IRQ_U300_GPIO_PORT1, |
| 168 | .flags = IORESOURCE_IRQ, |
| 169 | }, |
| 170 | { |
| 171 | .name = "gpio2", |
| 172 | .start = IRQ_U300_GPIO_PORT2, |
| 173 | .end = IRQ_U300_GPIO_PORT2, |
| 174 | .flags = IORESOURCE_IRQ, |
| 175 | }, |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 176 | #if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335) |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 177 | { |
| 178 | .name = "gpio3", |
| 179 | .start = IRQ_U300_GPIO_PORT3, |
| 180 | .end = IRQ_U300_GPIO_PORT3, |
| 181 | .flags = IORESOURCE_IRQ, |
| 182 | }, |
| 183 | { |
| 184 | .name = "gpio4", |
| 185 | .start = IRQ_U300_GPIO_PORT4, |
| 186 | .end = IRQ_U300_GPIO_PORT4, |
| 187 | .flags = IORESOURCE_IRQ, |
| 188 | }, |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 189 | #endif |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 190 | #ifdef CONFIG_MACH_U300_BS335 |
| 191 | { |
| 192 | .name = "gpio5", |
| 193 | .start = IRQ_U300_GPIO_PORT5, |
| 194 | .end = IRQ_U300_GPIO_PORT5, |
| 195 | .flags = IORESOURCE_IRQ, |
| 196 | }, |
| 197 | { |
| 198 | .name = "gpio6", |
| 199 | .start = IRQ_U300_GPIO_PORT6, |
| 200 | .end = IRQ_U300_GPIO_PORT6, |
| 201 | .flags = IORESOURCE_IRQ, |
| 202 | }, |
| 203 | #endif /* CONFIG_MACH_U300_BS335 */ |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 204 | }; |
| 205 | |
| 206 | static struct resource keypad_resources[] = { |
| 207 | { |
| 208 | .start = U300_KEYPAD_BASE, |
| 209 | .end = U300_KEYPAD_BASE + SZ_4K - 1, |
| 210 | .flags = IORESOURCE_MEM, |
| 211 | }, |
| 212 | { |
| 213 | .name = "coh901461-press", |
| 214 | .start = IRQ_U300_KEYPAD_KEYBF, |
| 215 | .end = IRQ_U300_KEYPAD_KEYBF, |
| 216 | .flags = IORESOURCE_IRQ, |
| 217 | }, |
| 218 | { |
| 219 | .name = "coh901461-release", |
| 220 | .start = IRQ_U300_KEYPAD_KEYBR, |
| 221 | .end = IRQ_U300_KEYPAD_KEYBR, |
| 222 | .flags = IORESOURCE_IRQ, |
| 223 | }, |
| 224 | }; |
| 225 | |
| 226 | static struct resource rtc_resources[] = { |
| 227 | { |
| 228 | .start = U300_RTC_BASE, |
| 229 | .end = U300_RTC_BASE + SZ_4K - 1, |
| 230 | .flags = IORESOURCE_MEM, |
| 231 | }, |
| 232 | { |
| 233 | .start = IRQ_U300_RTC, |
| 234 | .end = IRQ_U300_RTC, |
| 235 | .flags = IORESOURCE_IRQ, |
| 236 | }, |
| 237 | }; |
| 238 | |
| 239 | /* |
| 240 | * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2) |
| 241 | * but these are not yet used by the driver. |
| 242 | */ |
| 243 | static struct resource fsmc_resources[] = { |
| 244 | { |
Linus Walleij | 93ac5a5 | 2010-09-13 00:35:37 +0200 | [diff] [blame] | 245 | .name = "nand_data", |
| 246 | .start = U300_NAND_CS0_PHYS_BASE, |
| 247 | .end = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1, |
| 248 | .flags = IORESOURCE_MEM, |
| 249 | }, |
| 250 | { |
| 251 | .name = "fsmc_regs", |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 252 | .start = U300_NAND_IF_PHYS_BASE, |
| 253 | .end = U300_NAND_IF_PHYS_BASE + SZ_4K - 1, |
| 254 | .flags = IORESOURCE_MEM, |
| 255 | }, |
| 256 | }; |
| 257 | |
| 258 | static struct resource i2c0_resources[] = { |
| 259 | { |
| 260 | .start = U300_I2C0_BASE, |
| 261 | .end = U300_I2C0_BASE + SZ_4K - 1, |
| 262 | .flags = IORESOURCE_MEM, |
| 263 | }, |
| 264 | { |
| 265 | .start = IRQ_U300_I2C0, |
| 266 | .end = IRQ_U300_I2C0, |
| 267 | .flags = IORESOURCE_IRQ, |
| 268 | }, |
| 269 | }; |
| 270 | |
| 271 | static struct resource i2c1_resources[] = { |
| 272 | { |
| 273 | .start = U300_I2C1_BASE, |
| 274 | .end = U300_I2C1_BASE + SZ_4K - 1, |
| 275 | .flags = IORESOURCE_MEM, |
| 276 | }, |
| 277 | { |
| 278 | .start = IRQ_U300_I2C1, |
| 279 | .end = IRQ_U300_I2C1, |
| 280 | .flags = IORESOURCE_IRQ, |
| 281 | }, |
| 282 | |
| 283 | }; |
| 284 | |
| 285 | static struct resource wdog_resources[] = { |
| 286 | { |
| 287 | .start = U300_WDOG_BASE, |
| 288 | .end = U300_WDOG_BASE + SZ_4K - 1, |
| 289 | .flags = IORESOURCE_MEM, |
| 290 | }, |
| 291 | { |
| 292 | .start = IRQ_U300_WDOG, |
| 293 | .end = IRQ_U300_WDOG, |
| 294 | .flags = IORESOURCE_IRQ, |
| 295 | } |
| 296 | }; |
| 297 | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 298 | static struct resource dma_resource[] = { |
| 299 | { |
| 300 | .start = U300_DMAC_BASE, |
| 301 | .end = U300_DMAC_BASE + PAGE_SIZE - 1, |
| 302 | .flags = IORESOURCE_MEM, |
| 303 | }, |
| 304 | { |
| 305 | .start = IRQ_U300_DMA, |
| 306 | .end = IRQ_U300_DMA, |
| 307 | .flags = IORESOURCE_IRQ, |
| 308 | } |
| 309 | }; |
| 310 | |
| 311 | #ifdef CONFIG_MACH_U300_BS335 |
| 312 | /* points out all dma slave channels. |
| 313 | * Syntax is [A1, B1, A2, B2, .... ,-1,-1] |
| 314 | * Select all channels from A to B, end of list is marked with -1,-1 |
| 315 | */ |
| 316 | static int dma_slave_channels[] = { |
| 317 | U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, |
| 318 | U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1}; |
| 319 | |
| 320 | /* points out all dma memcpy channels. */ |
| 321 | static int dma_memcpy_channels[] = { |
| 322 | U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1}; |
| 323 | |
| 324 | #else /* CONFIG_MACH_U300_BS335 */ |
| 325 | |
| 326 | static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1}; |
| 327 | static int dma_memcpy_channels[] = { |
| 328 | U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1}; |
| 329 | |
| 330 | #endif |
| 331 | |
| 332 | /** register dma for memory access |
| 333 | * |
| 334 | * active 1 means dma intends to access memory |
| 335 | * 0 means dma wont access memory |
| 336 | */ |
| 337 | static void coh901318_access_memory_state(struct device *dev, bool active) |
| 338 | { |
| 339 | } |
| 340 | |
| 341 | #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \ |
| 342 | COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \ |
| 343 | COH901318_CX_CFG_LCR_DISABLE | \ |
| 344 | COH901318_CX_CFG_TC_IRQ_ENABLE | \ |
| 345 | COH901318_CX_CFG_BE_IRQ_ENABLE) |
| 346 | #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \ |
| 347 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \ |
| 348 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \ |
| 349 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \ |
| 350 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \ |
| 351 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \ |
| 352 | COH901318_CX_CTRL_MASTER_MODE_M1RW | \ |
| 353 | COH901318_CX_CTRL_TCP_DISABLE | \ |
| 354 | COH901318_CX_CTRL_TC_IRQ_DISABLE | \ |
| 355 | COH901318_CX_CTRL_HSP_DISABLE | \ |
| 356 | COH901318_CX_CTRL_HSS_DISABLE | \ |
| 357 | COH901318_CX_CTRL_DDMA_LEGACY | \ |
| 358 | COH901318_CX_CTRL_PRDD_SOURCE) |
| 359 | #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \ |
| 360 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \ |
| 361 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \ |
| 362 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \ |
| 363 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \ |
| 364 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \ |
| 365 | COH901318_CX_CTRL_MASTER_MODE_M1RW | \ |
| 366 | COH901318_CX_CTRL_TCP_DISABLE | \ |
| 367 | COH901318_CX_CTRL_TC_IRQ_DISABLE | \ |
| 368 | COH901318_CX_CTRL_HSP_DISABLE | \ |
| 369 | COH901318_CX_CTRL_HSS_DISABLE | \ |
| 370 | COH901318_CX_CTRL_DDMA_LEGACY | \ |
| 371 | COH901318_CX_CTRL_PRDD_SOURCE) |
| 372 | #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \ |
| 373 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \ |
| 374 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \ |
| 375 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \ |
| 376 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \ |
| 377 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \ |
| 378 | COH901318_CX_CTRL_MASTER_MODE_M1RW | \ |
| 379 | COH901318_CX_CTRL_TCP_DISABLE | \ |
| 380 | COH901318_CX_CTRL_TC_IRQ_ENABLE | \ |
| 381 | COH901318_CX_CTRL_HSP_DISABLE | \ |
| 382 | COH901318_CX_CTRL_HSS_DISABLE | \ |
| 383 | COH901318_CX_CTRL_DDMA_LEGACY | \ |
| 384 | COH901318_CX_CTRL_PRDD_SOURCE) |
| 385 | |
| 386 | const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = { |
| 387 | { |
| 388 | .number = U300_DMA_MSL_TX_0, |
| 389 | .name = "MSL TX 0", |
| 390 | .priority_high = 0, |
| 391 | .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20, |
| 392 | }, |
| 393 | { |
| 394 | .number = U300_DMA_MSL_TX_1, |
| 395 | .name = "MSL TX 1", |
| 396 | .priority_high = 0, |
| 397 | .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20, |
| 398 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 399 | COH901318_CX_CFG_LCR_DISABLE | |
| 400 | COH901318_CX_CFG_TC_IRQ_ENABLE | |
| 401 | COH901318_CX_CFG_BE_IRQ_ENABLE, |
| 402 | .param.ctrl_lli_chained = 0 | |
| 403 | COH901318_CX_CTRL_TC_ENABLE | |
| 404 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 405 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 406 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | |
| 407 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 408 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | |
| 409 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | |
| 410 | COH901318_CX_CTRL_TCP_DISABLE | |
| 411 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 412 | COH901318_CX_CTRL_HSP_ENABLE | |
| 413 | COH901318_CX_CTRL_HSS_DISABLE | |
| 414 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 415 | COH901318_CX_CTRL_PRDD_SOURCE, |
| 416 | .param.ctrl_lli = 0 | |
| 417 | COH901318_CX_CTRL_TC_ENABLE | |
| 418 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 419 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 420 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | |
| 421 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 422 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | |
| 423 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | |
| 424 | COH901318_CX_CTRL_TCP_ENABLE | |
| 425 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 426 | COH901318_CX_CTRL_HSP_ENABLE | |
| 427 | COH901318_CX_CTRL_HSS_DISABLE | |
| 428 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 429 | COH901318_CX_CTRL_PRDD_SOURCE, |
| 430 | .param.ctrl_lli_last = 0 | |
| 431 | COH901318_CX_CTRL_TC_ENABLE | |
| 432 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 433 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 434 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | |
| 435 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 436 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | |
| 437 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | |
| 438 | COH901318_CX_CTRL_TCP_ENABLE | |
| 439 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 440 | COH901318_CX_CTRL_HSP_ENABLE | |
| 441 | COH901318_CX_CTRL_HSS_DISABLE | |
| 442 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 443 | COH901318_CX_CTRL_PRDD_SOURCE, |
| 444 | }, |
| 445 | { |
| 446 | .number = U300_DMA_MSL_TX_2, |
| 447 | .name = "MSL TX 2", |
| 448 | .priority_high = 0, |
| 449 | .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20, |
| 450 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 451 | COH901318_CX_CFG_LCR_DISABLE | |
| 452 | COH901318_CX_CFG_TC_IRQ_ENABLE | |
| 453 | COH901318_CX_CFG_BE_IRQ_ENABLE, |
| 454 | .param.ctrl_lli_chained = 0 | |
| 455 | COH901318_CX_CTRL_TC_ENABLE | |
| 456 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 457 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 458 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | |
| 459 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 460 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | |
| 461 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | |
| 462 | COH901318_CX_CTRL_TCP_DISABLE | |
| 463 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 464 | COH901318_CX_CTRL_HSP_ENABLE | |
| 465 | COH901318_CX_CTRL_HSS_DISABLE | |
| 466 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 467 | COH901318_CX_CTRL_PRDD_SOURCE, |
| 468 | .param.ctrl_lli = 0 | |
| 469 | COH901318_CX_CTRL_TC_ENABLE | |
| 470 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 471 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 472 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | |
| 473 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 474 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | |
| 475 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | |
| 476 | COH901318_CX_CTRL_TCP_ENABLE | |
| 477 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 478 | COH901318_CX_CTRL_HSP_ENABLE | |
| 479 | COH901318_CX_CTRL_HSS_DISABLE | |
| 480 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 481 | COH901318_CX_CTRL_PRDD_SOURCE, |
| 482 | .param.ctrl_lli_last = 0 | |
| 483 | COH901318_CX_CTRL_TC_ENABLE | |
| 484 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 485 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 486 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | |
| 487 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 488 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | |
| 489 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | |
| 490 | COH901318_CX_CTRL_TCP_ENABLE | |
| 491 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 492 | COH901318_CX_CTRL_HSP_ENABLE | |
| 493 | COH901318_CX_CTRL_HSS_DISABLE | |
| 494 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 495 | COH901318_CX_CTRL_PRDD_SOURCE, |
| 496 | .desc_nbr_max = 10, |
| 497 | }, |
| 498 | { |
| 499 | .number = U300_DMA_MSL_TX_3, |
| 500 | .name = "MSL TX 3", |
| 501 | .priority_high = 0, |
| 502 | .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20, |
| 503 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 504 | COH901318_CX_CFG_LCR_DISABLE | |
| 505 | COH901318_CX_CFG_TC_IRQ_ENABLE | |
| 506 | COH901318_CX_CFG_BE_IRQ_ENABLE, |
| 507 | .param.ctrl_lli_chained = 0 | |
| 508 | COH901318_CX_CTRL_TC_ENABLE | |
| 509 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 510 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 511 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | |
| 512 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 513 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | |
| 514 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | |
| 515 | COH901318_CX_CTRL_TCP_DISABLE | |
| 516 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 517 | COH901318_CX_CTRL_HSP_ENABLE | |
| 518 | COH901318_CX_CTRL_HSS_DISABLE | |
| 519 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 520 | COH901318_CX_CTRL_PRDD_SOURCE, |
| 521 | .param.ctrl_lli = 0 | |
| 522 | COH901318_CX_CTRL_TC_ENABLE | |
| 523 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 524 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 525 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | |
| 526 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 527 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | |
| 528 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | |
| 529 | COH901318_CX_CTRL_TCP_ENABLE | |
| 530 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 531 | COH901318_CX_CTRL_HSP_ENABLE | |
| 532 | COH901318_CX_CTRL_HSS_DISABLE | |
| 533 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 534 | COH901318_CX_CTRL_PRDD_SOURCE, |
| 535 | .param.ctrl_lli_last = 0 | |
| 536 | COH901318_CX_CTRL_TC_ENABLE | |
| 537 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 538 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 539 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | |
| 540 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 541 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | |
| 542 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | |
| 543 | COH901318_CX_CTRL_TCP_ENABLE | |
| 544 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 545 | COH901318_CX_CTRL_HSP_ENABLE | |
| 546 | COH901318_CX_CTRL_HSS_DISABLE | |
| 547 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 548 | COH901318_CX_CTRL_PRDD_SOURCE, |
| 549 | }, |
| 550 | { |
| 551 | .number = U300_DMA_MSL_TX_4, |
| 552 | .name = "MSL TX 4", |
| 553 | .priority_high = 0, |
| 554 | .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20, |
| 555 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 556 | COH901318_CX_CFG_LCR_DISABLE | |
| 557 | COH901318_CX_CFG_TC_IRQ_ENABLE | |
| 558 | COH901318_CX_CFG_BE_IRQ_ENABLE, |
| 559 | .param.ctrl_lli_chained = 0 | |
| 560 | COH901318_CX_CTRL_TC_ENABLE | |
| 561 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 562 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 563 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | |
| 564 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 565 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | |
| 566 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | |
| 567 | COH901318_CX_CTRL_TCP_DISABLE | |
| 568 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 569 | COH901318_CX_CTRL_HSP_ENABLE | |
| 570 | COH901318_CX_CTRL_HSS_DISABLE | |
| 571 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 572 | COH901318_CX_CTRL_PRDD_SOURCE, |
| 573 | .param.ctrl_lli = 0 | |
| 574 | COH901318_CX_CTRL_TC_ENABLE | |
| 575 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 576 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 577 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | |
| 578 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 579 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | |
| 580 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | |
| 581 | COH901318_CX_CTRL_TCP_ENABLE | |
| 582 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 583 | COH901318_CX_CTRL_HSP_ENABLE | |
| 584 | COH901318_CX_CTRL_HSS_DISABLE | |
| 585 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 586 | COH901318_CX_CTRL_PRDD_SOURCE, |
| 587 | .param.ctrl_lli_last = 0 | |
| 588 | COH901318_CX_CTRL_TC_ENABLE | |
| 589 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 590 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 591 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | |
| 592 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 593 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | |
| 594 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | |
| 595 | COH901318_CX_CTRL_TCP_ENABLE | |
| 596 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 597 | COH901318_CX_CTRL_HSP_ENABLE | |
| 598 | COH901318_CX_CTRL_HSS_DISABLE | |
| 599 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 600 | COH901318_CX_CTRL_PRDD_SOURCE, |
| 601 | }, |
| 602 | { |
| 603 | .number = U300_DMA_MSL_TX_5, |
| 604 | .name = "MSL TX 5", |
| 605 | .priority_high = 0, |
| 606 | .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20, |
| 607 | }, |
| 608 | { |
| 609 | .number = U300_DMA_MSL_TX_6, |
| 610 | .name = "MSL TX 6", |
| 611 | .priority_high = 0, |
| 612 | .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20, |
| 613 | }, |
| 614 | { |
| 615 | .number = U300_DMA_MSL_RX_0, |
| 616 | .name = "MSL RX 0", |
| 617 | .priority_high = 0, |
| 618 | .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220, |
| 619 | }, |
| 620 | { |
| 621 | .number = U300_DMA_MSL_RX_1, |
| 622 | .name = "MSL RX 1", |
| 623 | .priority_high = 0, |
| 624 | .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220, |
| 625 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 626 | COH901318_CX_CFG_LCR_DISABLE | |
| 627 | COH901318_CX_CFG_TC_IRQ_ENABLE | |
| 628 | COH901318_CX_CFG_BE_IRQ_ENABLE, |
| 629 | .param.ctrl_lli_chained = 0 | |
| 630 | COH901318_CX_CTRL_TC_ENABLE | |
| 631 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 632 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 633 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | |
| 634 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 635 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | |
| 636 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | |
| 637 | COH901318_CX_CTRL_TCP_DISABLE | |
| 638 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 639 | COH901318_CX_CTRL_HSP_ENABLE | |
| 640 | COH901318_CX_CTRL_HSS_DISABLE | |
| 641 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | |
| 642 | COH901318_CX_CTRL_PRDD_DEST, |
| 643 | .param.ctrl_lli = 0, |
| 644 | .param.ctrl_lli_last = 0 | |
| 645 | COH901318_CX_CTRL_TC_ENABLE | |
| 646 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 647 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 648 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | |
| 649 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 650 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | |
| 651 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | |
| 652 | COH901318_CX_CTRL_TCP_DISABLE | |
| 653 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 654 | COH901318_CX_CTRL_HSP_ENABLE | |
| 655 | COH901318_CX_CTRL_HSS_DISABLE | |
| 656 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | |
| 657 | COH901318_CX_CTRL_PRDD_DEST, |
| 658 | }, |
| 659 | { |
| 660 | .number = U300_DMA_MSL_RX_2, |
| 661 | .name = "MSL RX 2", |
| 662 | .priority_high = 0, |
| 663 | .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220, |
| 664 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 665 | COH901318_CX_CFG_LCR_DISABLE | |
| 666 | COH901318_CX_CFG_TC_IRQ_ENABLE | |
| 667 | COH901318_CX_CFG_BE_IRQ_ENABLE, |
| 668 | .param.ctrl_lli_chained = 0 | |
| 669 | COH901318_CX_CTRL_TC_ENABLE | |
| 670 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 671 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 672 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | |
| 673 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 674 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | |
| 675 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | |
| 676 | COH901318_CX_CTRL_TCP_DISABLE | |
| 677 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 678 | COH901318_CX_CTRL_HSP_ENABLE | |
| 679 | COH901318_CX_CTRL_HSS_DISABLE | |
| 680 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | |
| 681 | COH901318_CX_CTRL_PRDD_DEST, |
| 682 | .param.ctrl_lli = 0 | |
| 683 | COH901318_CX_CTRL_TC_ENABLE | |
| 684 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 685 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 686 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | |
| 687 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 688 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | |
| 689 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | |
| 690 | COH901318_CX_CTRL_TCP_DISABLE | |
| 691 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 692 | COH901318_CX_CTRL_HSP_ENABLE | |
| 693 | COH901318_CX_CTRL_HSS_DISABLE | |
| 694 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | |
| 695 | COH901318_CX_CTRL_PRDD_DEST, |
| 696 | .param.ctrl_lli_last = 0 | |
| 697 | COH901318_CX_CTRL_TC_ENABLE | |
| 698 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 699 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 700 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | |
| 701 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 702 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | |
| 703 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | |
| 704 | COH901318_CX_CTRL_TCP_DISABLE | |
| 705 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 706 | COH901318_CX_CTRL_HSP_ENABLE | |
| 707 | COH901318_CX_CTRL_HSS_DISABLE | |
| 708 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | |
| 709 | COH901318_CX_CTRL_PRDD_DEST, |
| 710 | }, |
| 711 | { |
| 712 | .number = U300_DMA_MSL_RX_3, |
| 713 | .name = "MSL RX 3", |
| 714 | .priority_high = 0, |
| 715 | .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220, |
| 716 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 717 | COH901318_CX_CFG_LCR_DISABLE | |
| 718 | COH901318_CX_CFG_TC_IRQ_ENABLE | |
| 719 | COH901318_CX_CFG_BE_IRQ_ENABLE, |
| 720 | .param.ctrl_lli_chained = 0 | |
| 721 | COH901318_CX_CTRL_TC_ENABLE | |
| 722 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 723 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 724 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | |
| 725 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 726 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | |
| 727 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | |
| 728 | COH901318_CX_CTRL_TCP_DISABLE | |
| 729 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 730 | COH901318_CX_CTRL_HSP_ENABLE | |
| 731 | COH901318_CX_CTRL_HSS_DISABLE | |
| 732 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | |
| 733 | COH901318_CX_CTRL_PRDD_DEST, |
| 734 | .param.ctrl_lli = 0 | |
| 735 | COH901318_CX_CTRL_TC_ENABLE | |
| 736 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 737 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 738 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | |
| 739 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 740 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | |
| 741 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | |
| 742 | COH901318_CX_CTRL_TCP_DISABLE | |
| 743 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 744 | COH901318_CX_CTRL_HSP_ENABLE | |
| 745 | COH901318_CX_CTRL_HSS_DISABLE | |
| 746 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | |
| 747 | COH901318_CX_CTRL_PRDD_DEST, |
| 748 | .param.ctrl_lli_last = 0 | |
| 749 | COH901318_CX_CTRL_TC_ENABLE | |
| 750 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 751 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 752 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | |
| 753 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 754 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | |
| 755 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | |
| 756 | COH901318_CX_CTRL_TCP_DISABLE | |
| 757 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 758 | COH901318_CX_CTRL_HSP_ENABLE | |
| 759 | COH901318_CX_CTRL_HSS_DISABLE | |
| 760 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | |
| 761 | COH901318_CX_CTRL_PRDD_DEST, |
| 762 | }, |
| 763 | { |
| 764 | .number = U300_DMA_MSL_RX_4, |
| 765 | .name = "MSL RX 4", |
| 766 | .priority_high = 0, |
| 767 | .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220, |
| 768 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 769 | COH901318_CX_CFG_LCR_DISABLE | |
| 770 | COH901318_CX_CFG_TC_IRQ_ENABLE | |
| 771 | COH901318_CX_CFG_BE_IRQ_ENABLE, |
| 772 | .param.ctrl_lli_chained = 0 | |
| 773 | COH901318_CX_CTRL_TC_ENABLE | |
| 774 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 775 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 776 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | |
| 777 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 778 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | |
| 779 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | |
| 780 | COH901318_CX_CTRL_TCP_DISABLE | |
| 781 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 782 | COH901318_CX_CTRL_HSP_ENABLE | |
| 783 | COH901318_CX_CTRL_HSS_DISABLE | |
| 784 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | |
| 785 | COH901318_CX_CTRL_PRDD_DEST, |
| 786 | .param.ctrl_lli = 0 | |
| 787 | COH901318_CX_CTRL_TC_ENABLE | |
| 788 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 789 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 790 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | |
| 791 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 792 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | |
| 793 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | |
| 794 | COH901318_CX_CTRL_TCP_DISABLE | |
| 795 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 796 | COH901318_CX_CTRL_HSP_ENABLE | |
| 797 | COH901318_CX_CTRL_HSS_DISABLE | |
| 798 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | |
| 799 | COH901318_CX_CTRL_PRDD_DEST, |
| 800 | .param.ctrl_lli_last = 0 | |
| 801 | COH901318_CX_CTRL_TC_ENABLE | |
| 802 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 803 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 804 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | |
| 805 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 806 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | |
| 807 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | |
| 808 | COH901318_CX_CTRL_TCP_DISABLE | |
| 809 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 810 | COH901318_CX_CTRL_HSP_ENABLE | |
| 811 | COH901318_CX_CTRL_HSS_DISABLE | |
| 812 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | |
| 813 | COH901318_CX_CTRL_PRDD_DEST, |
| 814 | }, |
| 815 | { |
| 816 | .number = U300_DMA_MSL_RX_5, |
| 817 | .name = "MSL RX 5", |
| 818 | .priority_high = 0, |
| 819 | .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220, |
| 820 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 821 | COH901318_CX_CFG_LCR_DISABLE | |
| 822 | COH901318_CX_CFG_TC_IRQ_ENABLE | |
| 823 | COH901318_CX_CFG_BE_IRQ_ENABLE, |
| 824 | .param.ctrl_lli_chained = 0 | |
| 825 | COH901318_CX_CTRL_TC_ENABLE | |
| 826 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 827 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 828 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | |
| 829 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 830 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | |
| 831 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | |
| 832 | COH901318_CX_CTRL_TCP_DISABLE | |
| 833 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 834 | COH901318_CX_CTRL_HSP_ENABLE | |
| 835 | COH901318_CX_CTRL_HSS_DISABLE | |
| 836 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | |
| 837 | COH901318_CX_CTRL_PRDD_DEST, |
| 838 | .param.ctrl_lli = 0 | |
| 839 | COH901318_CX_CTRL_TC_ENABLE | |
| 840 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 841 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 842 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | |
| 843 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 844 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | |
| 845 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | |
| 846 | COH901318_CX_CTRL_TCP_DISABLE | |
| 847 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 848 | COH901318_CX_CTRL_HSP_ENABLE | |
| 849 | COH901318_CX_CTRL_HSS_DISABLE | |
| 850 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | |
| 851 | COH901318_CX_CTRL_PRDD_DEST, |
| 852 | .param.ctrl_lli_last = 0 | |
| 853 | COH901318_CX_CTRL_TC_ENABLE | |
| 854 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | |
| 855 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 856 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | |
| 857 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 858 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | |
| 859 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | |
| 860 | COH901318_CX_CTRL_TCP_DISABLE | |
| 861 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 862 | COH901318_CX_CTRL_HSP_ENABLE | |
| 863 | COH901318_CX_CTRL_HSS_DISABLE | |
| 864 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | |
| 865 | COH901318_CX_CTRL_PRDD_DEST, |
| 866 | }, |
| 867 | { |
| 868 | .number = U300_DMA_MSL_RX_6, |
| 869 | .name = "MSL RX 6", |
| 870 | .priority_high = 0, |
| 871 | .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220, |
| 872 | }, |
Linus Walleij | ec8f125 | 2010-08-13 11:31:59 +0200 | [diff] [blame] | 873 | /* |
| 874 | * Don't set up device address, burst count or size of src |
| 875 | * or dst bus for this peripheral - handled by PrimeCell |
| 876 | * DMA extension. |
| 877 | */ |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 878 | { |
| 879 | .number = U300_DMA_MMCSD_RX_TX, |
| 880 | .name = "MMCSD RX TX", |
| 881 | .priority_high = 0, |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 882 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 883 | COH901318_CX_CFG_LCR_DISABLE | |
| 884 | COH901318_CX_CFG_TC_IRQ_ENABLE | |
| 885 | COH901318_CX_CFG_BE_IRQ_ENABLE, |
| 886 | .param.ctrl_lli_chained = 0 | |
| 887 | COH901318_CX_CTRL_TC_ENABLE | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 888 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
Linus Walleij | d409566 | 2010-02-14 19:41:35 +0100 | [diff] [blame] | 889 | COH901318_CX_CTRL_TCP_ENABLE | |
Linus Walleij | ec8f125 | 2010-08-13 11:31:59 +0200 | [diff] [blame] | 890 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 891 | COH901318_CX_CTRL_HSP_ENABLE | |
| 892 | COH901318_CX_CTRL_HSS_DISABLE | |
| 893 | COH901318_CX_CTRL_DDMA_LEGACY, |
| 894 | .param.ctrl_lli = 0 | |
| 895 | COH901318_CX_CTRL_TC_ENABLE | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 896 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 897 | COH901318_CX_CTRL_TCP_ENABLE | |
Linus Walleij | ec8f125 | 2010-08-13 11:31:59 +0200 | [diff] [blame] | 898 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 899 | COH901318_CX_CTRL_HSP_ENABLE | |
| 900 | COH901318_CX_CTRL_HSS_DISABLE | |
| 901 | COH901318_CX_CTRL_DDMA_LEGACY, |
| 902 | .param.ctrl_lli_last = 0 | |
| 903 | COH901318_CX_CTRL_TC_ENABLE | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 904 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
Linus Walleij | d409566 | 2010-02-14 19:41:35 +0100 | [diff] [blame] | 905 | COH901318_CX_CTRL_TCP_DISABLE | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 906 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 907 | COH901318_CX_CTRL_HSP_ENABLE | |
| 908 | COH901318_CX_CTRL_HSS_DISABLE | |
| 909 | COH901318_CX_CTRL_DDMA_LEGACY, |
| 910 | |
| 911 | }, |
| 912 | { |
| 913 | .number = U300_DMA_MSPRO_TX, |
| 914 | .name = "MSPRO TX", |
| 915 | .priority_high = 0, |
| 916 | }, |
| 917 | { |
| 918 | .number = U300_DMA_MSPRO_RX, |
| 919 | .name = "MSPRO RX", |
| 920 | .priority_high = 0, |
| 921 | }, |
Linus Walleij | ec8f125 | 2010-08-13 11:31:59 +0200 | [diff] [blame] | 922 | /* |
| 923 | * Don't set up device address, burst count or size of src |
| 924 | * or dst bus for this peripheral - handled by PrimeCell |
| 925 | * DMA extension. |
| 926 | */ |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 927 | { |
| 928 | .number = U300_DMA_UART0_TX, |
| 929 | .name = "UART0 TX", |
| 930 | .priority_high = 0, |
Linus Walleij | ec8f125 | 2010-08-13 11:31:59 +0200 | [diff] [blame] | 931 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
| 932 | COH901318_CX_CFG_LCR_DISABLE | |
| 933 | COH901318_CX_CFG_TC_IRQ_ENABLE | |
| 934 | COH901318_CX_CFG_BE_IRQ_ENABLE, |
| 935 | .param.ctrl_lli_chained = 0 | |
| 936 | COH901318_CX_CTRL_TC_ENABLE | |
| 937 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 938 | COH901318_CX_CTRL_TCP_ENABLE | |
| 939 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 940 | COH901318_CX_CTRL_HSP_ENABLE | |
| 941 | COH901318_CX_CTRL_HSS_DISABLE | |
| 942 | COH901318_CX_CTRL_DDMA_LEGACY, |
| 943 | .param.ctrl_lli = 0 | |
| 944 | COH901318_CX_CTRL_TC_ENABLE | |
| 945 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 946 | COH901318_CX_CTRL_TCP_ENABLE | |
| 947 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 948 | COH901318_CX_CTRL_HSP_ENABLE | |
| 949 | COH901318_CX_CTRL_HSS_DISABLE | |
| 950 | COH901318_CX_CTRL_DDMA_LEGACY, |
| 951 | .param.ctrl_lli_last = 0 | |
| 952 | COH901318_CX_CTRL_TC_ENABLE | |
| 953 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 954 | COH901318_CX_CTRL_TCP_ENABLE | |
| 955 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 956 | COH901318_CX_CTRL_HSP_ENABLE | |
| 957 | COH901318_CX_CTRL_HSS_DISABLE | |
| 958 | COH901318_CX_CTRL_DDMA_LEGACY, |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 959 | }, |
| 960 | { |
| 961 | .number = U300_DMA_UART0_RX, |
| 962 | .name = "UART0 RX", |
| 963 | .priority_high = 0, |
Linus Walleij | ec8f125 | 2010-08-13 11:31:59 +0200 | [diff] [blame] | 964 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
| 965 | COH901318_CX_CFG_LCR_DISABLE | |
| 966 | COH901318_CX_CFG_TC_IRQ_ENABLE | |
| 967 | COH901318_CX_CFG_BE_IRQ_ENABLE, |
| 968 | .param.ctrl_lli_chained = 0 | |
| 969 | COH901318_CX_CTRL_TC_ENABLE | |
| 970 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 971 | COH901318_CX_CTRL_TCP_ENABLE | |
| 972 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 973 | COH901318_CX_CTRL_HSP_ENABLE | |
| 974 | COH901318_CX_CTRL_HSS_DISABLE | |
| 975 | COH901318_CX_CTRL_DDMA_LEGACY, |
| 976 | .param.ctrl_lli = 0 | |
| 977 | COH901318_CX_CTRL_TC_ENABLE | |
| 978 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 979 | COH901318_CX_CTRL_TCP_ENABLE | |
| 980 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 981 | COH901318_CX_CTRL_HSP_ENABLE | |
| 982 | COH901318_CX_CTRL_HSS_DISABLE | |
| 983 | COH901318_CX_CTRL_DDMA_LEGACY, |
| 984 | .param.ctrl_lli_last = 0 | |
| 985 | COH901318_CX_CTRL_TC_ENABLE | |
| 986 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 987 | COH901318_CX_CTRL_TCP_ENABLE | |
| 988 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 989 | COH901318_CX_CTRL_HSP_ENABLE | |
| 990 | COH901318_CX_CTRL_HSS_DISABLE | |
| 991 | COH901318_CX_CTRL_DDMA_LEGACY, |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 992 | }, |
| 993 | { |
| 994 | .number = U300_DMA_APEX_TX, |
| 995 | .name = "APEX TX", |
| 996 | .priority_high = 0, |
| 997 | }, |
| 998 | { |
| 999 | .number = U300_DMA_APEX_RX, |
| 1000 | .name = "APEX RX", |
| 1001 | .priority_high = 0, |
| 1002 | }, |
| 1003 | { |
| 1004 | .number = U300_DMA_PCM_I2S0_TX, |
| 1005 | .name = "PCM I2S0 TX", |
| 1006 | .priority_high = 1, |
| 1007 | .dev_addr = U300_PCM_I2S0_BASE + 0x14, |
| 1008 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 1009 | COH901318_CX_CFG_LCR_DISABLE | |
| 1010 | COH901318_CX_CFG_TC_IRQ_ENABLE | |
| 1011 | COH901318_CX_CFG_BE_IRQ_ENABLE, |
| 1012 | .param.ctrl_lli_chained = 0 | |
| 1013 | COH901318_CX_CTRL_TC_ENABLE | |
| 1014 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | |
| 1015 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 1016 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | |
| 1017 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 1018 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | |
| 1019 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 1020 | COH901318_CX_CTRL_TCP_DISABLE | |
| 1021 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 1022 | COH901318_CX_CTRL_HSP_ENABLE | |
| 1023 | COH901318_CX_CTRL_HSS_DISABLE | |
| 1024 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 1025 | COH901318_CX_CTRL_PRDD_SOURCE, |
| 1026 | .param.ctrl_lli = 0 | |
| 1027 | COH901318_CX_CTRL_TC_ENABLE | |
| 1028 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | |
| 1029 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 1030 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | |
| 1031 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 1032 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | |
| 1033 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 1034 | COH901318_CX_CTRL_TCP_ENABLE | |
| 1035 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 1036 | COH901318_CX_CTRL_HSP_ENABLE | |
| 1037 | COH901318_CX_CTRL_HSS_DISABLE | |
| 1038 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 1039 | COH901318_CX_CTRL_PRDD_SOURCE, |
| 1040 | .param.ctrl_lli_last = 0 | |
| 1041 | COH901318_CX_CTRL_TC_ENABLE | |
| 1042 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | |
| 1043 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 1044 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | |
| 1045 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 1046 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | |
| 1047 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 1048 | COH901318_CX_CTRL_TCP_ENABLE | |
Linus Walleij | ec8f125 | 2010-08-13 11:31:59 +0200 | [diff] [blame] | 1049 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 1050 | COH901318_CX_CTRL_HSP_ENABLE | |
| 1051 | COH901318_CX_CTRL_HSS_DISABLE | |
| 1052 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 1053 | COH901318_CX_CTRL_PRDD_SOURCE, |
| 1054 | }, |
| 1055 | { |
| 1056 | .number = U300_DMA_PCM_I2S0_RX, |
| 1057 | .name = "PCM I2S0 RX", |
| 1058 | .priority_high = 1, |
| 1059 | .dev_addr = U300_PCM_I2S0_BASE + 0x10, |
| 1060 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 1061 | COH901318_CX_CFG_LCR_DISABLE | |
| 1062 | COH901318_CX_CFG_TC_IRQ_ENABLE | |
| 1063 | COH901318_CX_CFG_BE_IRQ_ENABLE, |
| 1064 | .param.ctrl_lli_chained = 0 | |
| 1065 | COH901318_CX_CTRL_TC_ENABLE | |
| 1066 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | |
| 1067 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 1068 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | |
| 1069 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 1070 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | |
| 1071 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 1072 | COH901318_CX_CTRL_TCP_DISABLE | |
| 1073 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 1074 | COH901318_CX_CTRL_HSP_ENABLE | |
| 1075 | COH901318_CX_CTRL_HSS_DISABLE | |
| 1076 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 1077 | COH901318_CX_CTRL_PRDD_DEST, |
| 1078 | .param.ctrl_lli = 0 | |
| 1079 | COH901318_CX_CTRL_TC_ENABLE | |
| 1080 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | |
| 1081 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 1082 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | |
| 1083 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 1084 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | |
| 1085 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 1086 | COH901318_CX_CTRL_TCP_ENABLE | |
| 1087 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 1088 | COH901318_CX_CTRL_HSP_ENABLE | |
| 1089 | COH901318_CX_CTRL_HSS_DISABLE | |
| 1090 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 1091 | COH901318_CX_CTRL_PRDD_DEST, |
| 1092 | .param.ctrl_lli_last = 0 | |
| 1093 | COH901318_CX_CTRL_TC_ENABLE | |
| 1094 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | |
| 1095 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 1096 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | |
| 1097 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 1098 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | |
| 1099 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 1100 | COH901318_CX_CTRL_TCP_ENABLE | |
| 1101 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 1102 | COH901318_CX_CTRL_HSP_ENABLE | |
| 1103 | COH901318_CX_CTRL_HSS_DISABLE | |
| 1104 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 1105 | COH901318_CX_CTRL_PRDD_DEST, |
| 1106 | }, |
| 1107 | { |
| 1108 | .number = U300_DMA_PCM_I2S1_TX, |
| 1109 | .name = "PCM I2S1 TX", |
| 1110 | .priority_high = 1, |
| 1111 | .dev_addr = U300_PCM_I2S1_BASE + 0x14, |
| 1112 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 1113 | COH901318_CX_CFG_LCR_DISABLE | |
| 1114 | COH901318_CX_CFG_TC_IRQ_ENABLE | |
| 1115 | COH901318_CX_CFG_BE_IRQ_ENABLE, |
| 1116 | .param.ctrl_lli_chained = 0 | |
| 1117 | COH901318_CX_CTRL_TC_ENABLE | |
| 1118 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | |
| 1119 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 1120 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | |
| 1121 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 1122 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | |
| 1123 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 1124 | COH901318_CX_CTRL_TCP_DISABLE | |
| 1125 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 1126 | COH901318_CX_CTRL_HSP_ENABLE | |
| 1127 | COH901318_CX_CTRL_HSS_DISABLE | |
| 1128 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 1129 | COH901318_CX_CTRL_PRDD_SOURCE, |
| 1130 | .param.ctrl_lli = 0 | |
| 1131 | COH901318_CX_CTRL_TC_ENABLE | |
| 1132 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | |
| 1133 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 1134 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | |
| 1135 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 1136 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | |
| 1137 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 1138 | COH901318_CX_CTRL_TCP_ENABLE | |
| 1139 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 1140 | COH901318_CX_CTRL_HSP_ENABLE | |
| 1141 | COH901318_CX_CTRL_HSS_DISABLE | |
| 1142 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 1143 | COH901318_CX_CTRL_PRDD_SOURCE, |
| 1144 | .param.ctrl_lli_last = 0 | |
| 1145 | COH901318_CX_CTRL_TC_ENABLE | |
| 1146 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | |
| 1147 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 1148 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | |
| 1149 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 1150 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | |
| 1151 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 1152 | COH901318_CX_CTRL_TCP_ENABLE | |
| 1153 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 1154 | COH901318_CX_CTRL_HSP_ENABLE | |
| 1155 | COH901318_CX_CTRL_HSS_DISABLE | |
| 1156 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 1157 | COH901318_CX_CTRL_PRDD_SOURCE, |
| 1158 | }, |
| 1159 | { |
| 1160 | .number = U300_DMA_PCM_I2S1_RX, |
| 1161 | .name = "PCM I2S1 RX", |
| 1162 | .priority_high = 1, |
| 1163 | .dev_addr = U300_PCM_I2S1_BASE + 0x10, |
| 1164 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 1165 | COH901318_CX_CFG_LCR_DISABLE | |
| 1166 | COH901318_CX_CFG_TC_IRQ_ENABLE | |
| 1167 | COH901318_CX_CFG_BE_IRQ_ENABLE, |
| 1168 | .param.ctrl_lli_chained = 0 | |
| 1169 | COH901318_CX_CTRL_TC_ENABLE | |
| 1170 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | |
| 1171 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 1172 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | |
| 1173 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 1174 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | |
| 1175 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 1176 | COH901318_CX_CTRL_TCP_DISABLE | |
| 1177 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 1178 | COH901318_CX_CTRL_HSP_ENABLE | |
| 1179 | COH901318_CX_CTRL_HSS_DISABLE | |
| 1180 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 1181 | COH901318_CX_CTRL_PRDD_DEST, |
| 1182 | .param.ctrl_lli = 0 | |
| 1183 | COH901318_CX_CTRL_TC_ENABLE | |
| 1184 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | |
| 1185 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 1186 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | |
| 1187 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 1188 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | |
| 1189 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 1190 | COH901318_CX_CTRL_TCP_ENABLE | |
| 1191 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 1192 | COH901318_CX_CTRL_HSP_ENABLE | |
| 1193 | COH901318_CX_CTRL_HSS_DISABLE | |
| 1194 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 1195 | COH901318_CX_CTRL_PRDD_DEST, |
| 1196 | .param.ctrl_lli_last = 0 | |
| 1197 | COH901318_CX_CTRL_TC_ENABLE | |
| 1198 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | |
| 1199 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
| 1200 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | |
| 1201 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | |
| 1202 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | |
| 1203 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 1204 | COH901318_CX_CTRL_TCP_ENABLE | |
| 1205 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 1206 | COH901318_CX_CTRL_HSP_ENABLE | |
| 1207 | COH901318_CX_CTRL_HSS_DISABLE | |
| 1208 | COH901318_CX_CTRL_DDMA_LEGACY | |
| 1209 | COH901318_CX_CTRL_PRDD_DEST, |
| 1210 | }, |
| 1211 | { |
| 1212 | .number = U300_DMA_XGAM_CDI, |
| 1213 | .name = "XGAM CDI", |
| 1214 | .priority_high = 0, |
| 1215 | }, |
| 1216 | { |
| 1217 | .number = U300_DMA_XGAM_PDI, |
| 1218 | .name = "XGAM PDI", |
| 1219 | .priority_high = 0, |
| 1220 | }, |
Linus Walleij | ec8f125 | 2010-08-13 11:31:59 +0200 | [diff] [blame] | 1221 | /* |
| 1222 | * Don't set up device address, burst count or size of src |
| 1223 | * or dst bus for this peripheral - handled by PrimeCell |
| 1224 | * DMA extension. |
| 1225 | */ |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 1226 | { |
| 1227 | .number = U300_DMA_SPI_TX, |
| 1228 | .name = "SPI TX", |
| 1229 | .priority_high = 0, |
Linus Walleij | ec8f125 | 2010-08-13 11:31:59 +0200 | [diff] [blame] | 1230 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
| 1231 | COH901318_CX_CFG_LCR_DISABLE | |
| 1232 | COH901318_CX_CFG_TC_IRQ_ENABLE | |
| 1233 | COH901318_CX_CFG_BE_IRQ_ENABLE, |
| 1234 | .param.ctrl_lli_chained = 0 | |
| 1235 | COH901318_CX_CTRL_TC_ENABLE | |
| 1236 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 1237 | COH901318_CX_CTRL_TCP_DISABLE | |
| 1238 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 1239 | COH901318_CX_CTRL_HSP_ENABLE | |
| 1240 | COH901318_CX_CTRL_HSS_DISABLE | |
| 1241 | COH901318_CX_CTRL_DDMA_LEGACY, |
| 1242 | .param.ctrl_lli = 0 | |
| 1243 | COH901318_CX_CTRL_TC_ENABLE | |
| 1244 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 1245 | COH901318_CX_CTRL_TCP_DISABLE | |
| 1246 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 1247 | COH901318_CX_CTRL_HSP_ENABLE | |
| 1248 | COH901318_CX_CTRL_HSS_DISABLE | |
| 1249 | COH901318_CX_CTRL_DDMA_LEGACY, |
| 1250 | .param.ctrl_lli_last = 0 | |
| 1251 | COH901318_CX_CTRL_TC_ENABLE | |
| 1252 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 1253 | COH901318_CX_CTRL_TCP_DISABLE | |
| 1254 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 1255 | COH901318_CX_CTRL_HSP_ENABLE | |
| 1256 | COH901318_CX_CTRL_HSS_DISABLE | |
| 1257 | COH901318_CX_CTRL_DDMA_LEGACY, |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 1258 | }, |
| 1259 | { |
| 1260 | .number = U300_DMA_SPI_RX, |
| 1261 | .name = "SPI RX", |
| 1262 | .priority_high = 0, |
Linus Walleij | ec8f125 | 2010-08-13 11:31:59 +0200 | [diff] [blame] | 1263 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
| 1264 | COH901318_CX_CFG_LCR_DISABLE | |
| 1265 | COH901318_CX_CFG_TC_IRQ_ENABLE | |
| 1266 | COH901318_CX_CFG_BE_IRQ_ENABLE, |
| 1267 | .param.ctrl_lli_chained = 0 | |
| 1268 | COH901318_CX_CTRL_TC_ENABLE | |
| 1269 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 1270 | COH901318_CX_CTRL_TCP_DISABLE | |
| 1271 | COH901318_CX_CTRL_TC_IRQ_DISABLE | |
| 1272 | COH901318_CX_CTRL_HSP_ENABLE | |
| 1273 | COH901318_CX_CTRL_HSS_DISABLE | |
| 1274 | COH901318_CX_CTRL_DDMA_LEGACY, |
| 1275 | .param.ctrl_lli = 0 | |
| 1276 | COH901318_CX_CTRL_TC_ENABLE | |
| 1277 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 1278 | COH901318_CX_CTRL_TCP_DISABLE | |
| 1279 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 1280 | COH901318_CX_CTRL_HSP_ENABLE | |
| 1281 | COH901318_CX_CTRL_HSS_DISABLE | |
| 1282 | COH901318_CX_CTRL_DDMA_LEGACY, |
| 1283 | .param.ctrl_lli_last = 0 | |
| 1284 | COH901318_CX_CTRL_TC_ENABLE | |
| 1285 | COH901318_CX_CTRL_MASTER_MODE_M1RW | |
| 1286 | COH901318_CX_CTRL_TCP_DISABLE | |
| 1287 | COH901318_CX_CTRL_TC_IRQ_ENABLE | |
| 1288 | COH901318_CX_CTRL_HSP_ENABLE | |
| 1289 | COH901318_CX_CTRL_HSS_DISABLE | |
| 1290 | COH901318_CX_CTRL_DDMA_LEGACY, |
| 1291 | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 1292 | }, |
| 1293 | { |
| 1294 | .number = U300_DMA_GENERAL_PURPOSE_0, |
| 1295 | .name = "GENERAL 00", |
| 1296 | .priority_high = 0, |
| 1297 | |
| 1298 | .param.config = flags_memcpy_config, |
| 1299 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, |
| 1300 | .param.ctrl_lli = flags_memcpy_lli, |
| 1301 | .param.ctrl_lli_last = flags_memcpy_lli_last, |
| 1302 | }, |
| 1303 | { |
| 1304 | .number = U300_DMA_GENERAL_PURPOSE_1, |
| 1305 | .name = "GENERAL 01", |
| 1306 | .priority_high = 0, |
| 1307 | |
| 1308 | .param.config = flags_memcpy_config, |
| 1309 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, |
| 1310 | .param.ctrl_lli = flags_memcpy_lli, |
| 1311 | .param.ctrl_lli_last = flags_memcpy_lli_last, |
| 1312 | }, |
| 1313 | { |
| 1314 | .number = U300_DMA_GENERAL_PURPOSE_2, |
| 1315 | .name = "GENERAL 02", |
| 1316 | .priority_high = 0, |
| 1317 | |
| 1318 | .param.config = flags_memcpy_config, |
| 1319 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, |
| 1320 | .param.ctrl_lli = flags_memcpy_lli, |
| 1321 | .param.ctrl_lli_last = flags_memcpy_lli_last, |
| 1322 | }, |
| 1323 | { |
| 1324 | .number = U300_DMA_GENERAL_PURPOSE_3, |
| 1325 | .name = "GENERAL 03", |
| 1326 | .priority_high = 0, |
| 1327 | |
| 1328 | .param.config = flags_memcpy_config, |
| 1329 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, |
| 1330 | .param.ctrl_lli = flags_memcpy_lli, |
| 1331 | .param.ctrl_lli_last = flags_memcpy_lli_last, |
| 1332 | }, |
| 1333 | { |
| 1334 | .number = U300_DMA_GENERAL_PURPOSE_4, |
| 1335 | .name = "GENERAL 04", |
| 1336 | .priority_high = 0, |
| 1337 | |
| 1338 | .param.config = flags_memcpy_config, |
| 1339 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, |
| 1340 | .param.ctrl_lli = flags_memcpy_lli, |
| 1341 | .param.ctrl_lli_last = flags_memcpy_lli_last, |
| 1342 | }, |
| 1343 | { |
| 1344 | .number = U300_DMA_GENERAL_PURPOSE_5, |
| 1345 | .name = "GENERAL 05", |
| 1346 | .priority_high = 0, |
| 1347 | |
| 1348 | .param.config = flags_memcpy_config, |
| 1349 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, |
| 1350 | .param.ctrl_lli = flags_memcpy_lli, |
| 1351 | .param.ctrl_lli_last = flags_memcpy_lli_last, |
| 1352 | }, |
| 1353 | { |
| 1354 | .number = U300_DMA_GENERAL_PURPOSE_6, |
| 1355 | .name = "GENERAL 06", |
| 1356 | .priority_high = 0, |
| 1357 | |
| 1358 | .param.config = flags_memcpy_config, |
| 1359 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, |
| 1360 | .param.ctrl_lli = flags_memcpy_lli, |
| 1361 | .param.ctrl_lli_last = flags_memcpy_lli_last, |
| 1362 | }, |
| 1363 | { |
| 1364 | .number = U300_DMA_GENERAL_PURPOSE_7, |
| 1365 | .name = "GENERAL 07", |
| 1366 | .priority_high = 0, |
| 1367 | |
| 1368 | .param.config = flags_memcpy_config, |
| 1369 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, |
| 1370 | .param.ctrl_lli = flags_memcpy_lli, |
| 1371 | .param.ctrl_lli_last = flags_memcpy_lli_last, |
| 1372 | }, |
| 1373 | { |
| 1374 | .number = U300_DMA_GENERAL_PURPOSE_8, |
| 1375 | .name = "GENERAL 08", |
| 1376 | .priority_high = 0, |
| 1377 | |
| 1378 | .param.config = flags_memcpy_config, |
| 1379 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, |
| 1380 | .param.ctrl_lli = flags_memcpy_lli, |
| 1381 | .param.ctrl_lli_last = flags_memcpy_lli_last, |
| 1382 | }, |
| 1383 | #ifdef CONFIG_MACH_U300_BS335 |
| 1384 | { |
| 1385 | .number = U300_DMA_UART1_TX, |
| 1386 | .name = "UART1 TX", |
| 1387 | .priority_high = 0, |
| 1388 | }, |
| 1389 | { |
| 1390 | .number = U300_DMA_UART1_RX, |
| 1391 | .name = "UART1 RX", |
| 1392 | .priority_high = 0, |
| 1393 | } |
| 1394 | #else |
| 1395 | { |
| 1396 | .number = U300_DMA_GENERAL_PURPOSE_9, |
| 1397 | .name = "GENERAL 09", |
| 1398 | .priority_high = 0, |
| 1399 | |
| 1400 | .param.config = flags_memcpy_config, |
| 1401 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, |
| 1402 | .param.ctrl_lli = flags_memcpy_lli, |
| 1403 | .param.ctrl_lli_last = flags_memcpy_lli_last, |
| 1404 | }, |
| 1405 | { |
| 1406 | .number = U300_DMA_GENERAL_PURPOSE_10, |
| 1407 | .name = "GENERAL 10", |
| 1408 | .priority_high = 0, |
| 1409 | |
| 1410 | .param.config = flags_memcpy_config, |
| 1411 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, |
| 1412 | .param.ctrl_lli = flags_memcpy_lli, |
| 1413 | .param.ctrl_lli_last = flags_memcpy_lli_last, |
| 1414 | } |
| 1415 | #endif |
| 1416 | }; |
| 1417 | |
| 1418 | |
| 1419 | static struct coh901318_platform coh901318_platform = { |
| 1420 | .chans_slave = dma_slave_channels, |
| 1421 | .chans_memcpy = dma_memcpy_channels, |
| 1422 | .access_memory_state = coh901318_access_memory_state, |
| 1423 | .chan_conf = chan_config, |
| 1424 | .max_channels = U300_DMA_CHANNELS, |
| 1425 | }; |
| 1426 | |
Linus Walleij | 98da352 | 2011-05-02 20:54:38 +0200 | [diff] [blame] | 1427 | static struct resource pinmux_resources[] = { |
| 1428 | { |
| 1429 | .start = U300_SYSCON_BASE, |
| 1430 | .end = U300_SYSCON_BASE + SZ_4K - 1, |
| 1431 | .flags = IORESOURCE_MEM, |
| 1432 | }, |
| 1433 | }; |
| 1434 | |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1435 | static struct platform_device wdog_device = { |
Linus Walleij | 633e81a | 2010-01-25 07:18:16 +0100 | [diff] [blame] | 1436 | .name = "coh901327_wdog", |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1437 | .id = -1, |
| 1438 | .num_resources = ARRAY_SIZE(wdog_resources), |
| 1439 | .resource = wdog_resources, |
| 1440 | }; |
| 1441 | |
| 1442 | static struct platform_device i2c0_device = { |
Linus Walleij | 6be2a0c | 2009-08-13 21:42:01 +0100 | [diff] [blame] | 1443 | .name = "stu300", |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1444 | .id = 0, |
| 1445 | .num_resources = ARRAY_SIZE(i2c0_resources), |
| 1446 | .resource = i2c0_resources, |
| 1447 | }; |
| 1448 | |
| 1449 | static struct platform_device i2c1_device = { |
Linus Walleij | 6be2a0c | 2009-08-13 21:42:01 +0100 | [diff] [blame] | 1450 | .name = "stu300", |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1451 | .id = 1, |
| 1452 | .num_resources = ARRAY_SIZE(i2c1_resources), |
| 1453 | .resource = i2c1_resources, |
| 1454 | }; |
| 1455 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 1456 | /* |
| 1457 | * The different variants have a few different versions of the |
| 1458 | * GPIO block, with different number of ports. |
| 1459 | */ |
| 1460 | static struct u300_gpio_platform u300_gpio_plat = { |
| 1461 | #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) |
| 1462 | .variant = U300_GPIO_COH901335, |
| 1463 | .ports = 3, |
| 1464 | #endif |
| 1465 | #ifdef CONFIG_MACH_U300_BS335 |
| 1466 | .variant = U300_GPIO_COH901571_3_BS335, |
| 1467 | .ports = 7, |
| 1468 | #endif |
| 1469 | #ifdef CONFIG_MACH_U300_BS365 |
| 1470 | .variant = U300_GPIO_COH901571_3_BS365, |
| 1471 | .ports = 5, |
| 1472 | #endif |
| 1473 | .gpio_base = 0, |
| 1474 | .gpio_irq_base = IRQ_U300_GPIO_BASE, |
| 1475 | }; |
| 1476 | |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1477 | static struct platform_device gpio_device = { |
| 1478 | .name = "u300-gpio", |
| 1479 | .id = -1, |
| 1480 | .num_resources = ARRAY_SIZE(gpio_resources), |
| 1481 | .resource = gpio_resources, |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 1482 | .dev = { |
| 1483 | .platform_data = &u300_gpio_plat, |
| 1484 | }, |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1485 | }; |
| 1486 | |
| 1487 | static struct platform_device keypad_device = { |
| 1488 | .name = "keypad", |
| 1489 | .id = -1, |
| 1490 | .num_resources = ARRAY_SIZE(keypad_resources), |
| 1491 | .resource = keypad_resources, |
| 1492 | }; |
| 1493 | |
| 1494 | static struct platform_device rtc_device = { |
Linus Walleij | 378ce74 | 2009-11-14 01:03:24 +0100 | [diff] [blame] | 1495 | .name = "rtc-coh901331", |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1496 | .id = -1, |
| 1497 | .num_resources = ARRAY_SIZE(rtc_resources), |
| 1498 | .resource = rtc_resources, |
| 1499 | }; |
| 1500 | |
Linus Walleij | 93ac5a5 | 2010-09-13 00:35:37 +0200 | [diff] [blame] | 1501 | static struct mtd_partition u300_partitions[] = { |
| 1502 | { |
| 1503 | .name = "bootrecords", |
| 1504 | .offset = 0, |
| 1505 | .size = SZ_128K, |
| 1506 | }, |
| 1507 | { |
| 1508 | .name = "free", |
| 1509 | .offset = SZ_128K, |
| 1510 | .size = 8064 * SZ_1K, |
| 1511 | }, |
| 1512 | { |
| 1513 | .name = "platform", |
| 1514 | .offset = 8192 * SZ_1K, |
| 1515 | .size = 253952 * SZ_1K, |
| 1516 | }, |
| 1517 | }; |
| 1518 | |
| 1519 | static struct fsmc_nand_platform_data nand_platform_data = { |
| 1520 | .partitions = u300_partitions, |
| 1521 | .nr_partitions = ARRAY_SIZE(u300_partitions), |
| 1522 | .options = NAND_SKIP_BBTSCAN, |
| 1523 | .width = FSMC_NAND_BW8, |
| 1524 | }; |
| 1525 | |
| 1526 | static struct platform_device nand_device = { |
| 1527 | .name = "fsmc-nand", |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1528 | .id = -1, |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1529 | .resource = fsmc_resources, |
Linus Walleij | 93ac5a5 | 2010-09-13 00:35:37 +0200 | [diff] [blame] | 1530 | .num_resources = ARRAY_SIZE(fsmc_resources), |
| 1531 | .dev = { |
| 1532 | .platform_data = &nand_platform_data, |
| 1533 | }, |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1534 | }; |
| 1535 | |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 1536 | static struct platform_device dma_device = { |
| 1537 | .name = "coh901318", |
| 1538 | .id = -1, |
| 1539 | .resource = dma_resource, |
| 1540 | .num_resources = ARRAY_SIZE(dma_resource), |
| 1541 | .dev = { |
| 1542 | .platform_data = &coh901318_platform, |
| 1543 | .coherent_dma_mask = ~0, |
| 1544 | }, |
| 1545 | }; |
| 1546 | |
Linus Walleij | 98da352 | 2011-05-02 20:54:38 +0200 | [diff] [blame] | 1547 | static struct platform_device pinmux_device = { |
| 1548 | .name = "pinmux-u300", |
| 1549 | .id = -1, |
| 1550 | .num_resources = ARRAY_SIZE(pinmux_resources), |
| 1551 | .resource = pinmux_resources, |
| 1552 | }; |
| 1553 | |
| 1554 | /* Pinmux settings */ |
Linus Walleij | 97607d1 | 2011-11-29 12:52:39 +0100 | [diff] [blame] | 1555 | static struct pinmux_map __initdata u300_pinmux_map[] = { |
Linus Walleij | 98da352 | 2011-05-02 20:54:38 +0200 | [diff] [blame] | 1556 | /* anonymous maps for chip power and EMIFs */ |
Stephen Warren | 528b783 | 2011-12-09 16:59:04 -0700 | [diff] [blame] | 1557 | PINMUX_MAP_SYS_HOG("POWER", "pinmux-u300", "power"), |
| 1558 | PINMUX_MAP_SYS_HOG("EMIF0", "pinmux-u300", "emif0"), |
| 1559 | PINMUX_MAP_SYS_HOG("EMIF1", "pinmux-u300", "emif1"), |
Linus Walleij | 98da352 | 2011-05-02 20:54:38 +0200 | [diff] [blame] | 1560 | /* per-device maps for MMC/SD, SPI and UART */ |
Stephen Warren | 528b783 | 2011-12-09 16:59:04 -0700 | [diff] [blame] | 1561 | PINMUX_MAP("MMCSD", "pinmux-u300", "mmc0", "mmci"), |
| 1562 | PINMUX_MAP("SPI", "pinmux-u300", "spi0", "pl022"), |
| 1563 | PINMUX_MAP("UART0", "pinmux-u300", "uart0", "uart0"), |
Linus Walleij | 98da352 | 2011-05-02 20:54:38 +0200 | [diff] [blame] | 1564 | }; |
| 1565 | |
| 1566 | struct u300_mux_hog { |
| 1567 | const char *name; |
| 1568 | struct device *dev; |
| 1569 | struct pinmux *pmx; |
| 1570 | }; |
| 1571 | |
| 1572 | static struct u300_mux_hog u300_mux_hogs[] = { |
| 1573 | { |
| 1574 | .name = "uart0", |
| 1575 | .dev = &uart0_device.dev, |
| 1576 | }, |
| 1577 | { |
| 1578 | .name = "spi0", |
| 1579 | .dev = &pl022_device.dev, |
| 1580 | }, |
| 1581 | { |
| 1582 | .name = "mmc0", |
| 1583 | .dev = &mmcsd_device.dev, |
| 1584 | }, |
| 1585 | }; |
| 1586 | |
| 1587 | static int __init u300_pinmux_fetch(void) |
| 1588 | { |
| 1589 | int i; |
| 1590 | |
| 1591 | for (i = 0; i < ARRAY_SIZE(u300_mux_hogs); i++) { |
| 1592 | struct pinmux *pmx; |
| 1593 | int ret; |
| 1594 | |
| 1595 | pmx = pinmux_get(u300_mux_hogs[i].dev, NULL); |
| 1596 | if (IS_ERR(pmx)) { |
| 1597 | pr_err("u300: could not get pinmux hog %s\n", |
| 1598 | u300_mux_hogs[i].name); |
| 1599 | continue; |
| 1600 | } |
| 1601 | ret = pinmux_enable(pmx); |
| 1602 | if (ret) { |
| 1603 | pr_err("u300: could enable pinmux hog %s\n", |
| 1604 | u300_mux_hogs[i].name); |
| 1605 | continue; |
| 1606 | } |
| 1607 | u300_mux_hogs[i].pmx = pmx; |
| 1608 | } |
| 1609 | return 0; |
| 1610 | } |
| 1611 | subsys_initcall(u300_pinmux_fetch); |
| 1612 | |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1613 | /* |
| 1614 | * Notice that AMBA devices are initialized before platform devices. |
| 1615 | * |
| 1616 | */ |
| 1617 | static struct platform_device *platform_devs[] __initdata = { |
Linus Walleij | 08d1e2e | 2009-12-17 09:46:24 +0100 | [diff] [blame] | 1618 | &dma_device, |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1619 | &i2c0_device, |
| 1620 | &i2c1_device, |
| 1621 | &keypad_device, |
| 1622 | &rtc_device, |
| 1623 | &gpio_device, |
Linus Walleij | 93ac5a5 | 2010-09-13 00:35:37 +0200 | [diff] [blame] | 1624 | &nand_device, |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1625 | &wdog_device, |
Linus Walleij | 98da352 | 2011-05-02 20:54:38 +0200 | [diff] [blame] | 1626 | &pinmux_device, |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1627 | }; |
| 1628 | |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1629 | /* |
| 1630 | * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected |
| 1631 | * together so some interrupts are connected to the first one and some |
| 1632 | * to the second one. |
| 1633 | */ |
| 1634 | void __init u300_init_irq(void) |
| 1635 | { |
| 1636 | u32 mask[2] = {0, 0}; |
Linus Walleij | b7276b2 | 2010-08-05 07:58:58 +0100 | [diff] [blame] | 1637 | struct clk *clk; |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1638 | int i; |
| 1639 | |
Linus Walleij | 379aae5 | 2010-08-05 07:58:13 +0100 | [diff] [blame] | 1640 | /* initialize clocking early, we want to clock the INTCON */ |
| 1641 | u300_clock_init(); |
| 1642 | |
Linus Walleij | b7276b2 | 2010-08-05 07:58:58 +0100 | [diff] [blame] | 1643 | /* Clock the interrupt controller */ |
| 1644 | clk = clk_get_sys("intcon", NULL); |
| 1645 | BUG_ON(IS_ERR(clk)); |
| 1646 | clk_enable(clk); |
| 1647 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 1648 | for (i = 0; i < U300_VIC_IRQS_END; i++) |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1649 | set_bit(i, (unsigned long *) &mask[0]); |
Linus Walleij | 6860107 | 2009-07-06 18:04:28 +0100 | [diff] [blame] | 1650 | vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]); |
| 1651 | vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]); |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1652 | } |
| 1653 | |
| 1654 | |
| 1655 | /* |
| 1656 | * U300 platforms peripheral handling |
| 1657 | */ |
| 1658 | struct db_chip { |
| 1659 | u16 chipid; |
| 1660 | const char *name; |
| 1661 | }; |
| 1662 | |
| 1663 | /* |
| 1664 | * This is a list of the Digital Baseband chips used in the U300 platform. |
| 1665 | */ |
| 1666 | static struct db_chip db_chips[] __initdata = { |
| 1667 | { |
| 1668 | .chipid = 0xb800, |
| 1669 | .name = "DB3000", |
| 1670 | }, |
| 1671 | { |
| 1672 | .chipid = 0xc000, |
| 1673 | .name = "DB3100", |
| 1674 | }, |
| 1675 | { |
| 1676 | .chipid = 0xc800, |
| 1677 | .name = "DB3150", |
| 1678 | }, |
| 1679 | { |
| 1680 | .chipid = 0xd800, |
| 1681 | .name = "DB3200", |
| 1682 | }, |
| 1683 | { |
| 1684 | .chipid = 0xe000, |
| 1685 | .name = "DB3250", |
| 1686 | }, |
| 1687 | { |
| 1688 | .chipid = 0xe800, |
| 1689 | .name = "DB3210", |
| 1690 | }, |
| 1691 | { |
| 1692 | .chipid = 0xf000, |
| 1693 | .name = "DB3350 P1x", |
| 1694 | }, |
| 1695 | { |
| 1696 | .chipid = 0xf100, |
| 1697 | .name = "DB3350 P2x", |
| 1698 | }, |
| 1699 | { |
| 1700 | .chipid = 0x0000, /* List terminator */ |
| 1701 | .name = NULL, |
| 1702 | } |
| 1703 | }; |
| 1704 | |
Linus Walleij | a2bb9f4 | 2009-08-13 21:57:22 +0100 | [diff] [blame] | 1705 | static void __init u300_init_check_chip(void) |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1706 | { |
| 1707 | |
| 1708 | u16 val; |
| 1709 | struct db_chip *chip; |
| 1710 | const char *chipname; |
| 1711 | const char unknown[] = "UNKNOWN"; |
| 1712 | |
| 1713 | /* Read out and print chip ID */ |
| 1714 | val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR); |
| 1715 | /* This is in funky bigendian order... */ |
| 1716 | val = (val & 0xFFU) << 8 | (val >> 8); |
| 1717 | chip = db_chips; |
| 1718 | chipname = unknown; |
| 1719 | |
| 1720 | for ( ; chip->chipid; chip++) { |
| 1721 | if (chip->chipid == (val & 0xFF00U)) { |
| 1722 | chipname = chip->name; |
| 1723 | break; |
| 1724 | } |
| 1725 | } |
| 1726 | printk(KERN_INFO "Initializing U300 system on %s baseband chip " \ |
| 1727 | "(chip ID 0x%04x)\n", chipname, val); |
| 1728 | |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1729 | #ifdef CONFIG_MACH_U300_BS330 |
| 1730 | if ((val & 0xFF00U) != 0xd800) { |
| 1731 | printk(KERN_ERR "Platform configured for BS330 " \ |
| 1732 | "with DB3200 but %s detected, expect problems!", |
| 1733 | chipname); |
| 1734 | } |
| 1735 | #endif |
| 1736 | #ifdef CONFIG_MACH_U300_BS335 |
| 1737 | if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) { |
Linus Walleij | ec8f125 | 2010-08-13 11:31:59 +0200 | [diff] [blame] | 1738 | printk(KERN_ERR "Platform configured for BS335 " \ |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1739 | " with DB3350 but %s detected, expect problems!", |
| 1740 | chipname); |
| 1741 | } |
| 1742 | #endif |
| 1743 | #ifdef CONFIG_MACH_U300_BS365 |
| 1744 | if ((val & 0xFF00U) != 0xe800) { |
| 1745 | printk(KERN_ERR "Platform configured for BS365 " \ |
| 1746 | "with DB3210 but %s detected, expect problems!", |
| 1747 | chipname); |
| 1748 | } |
| 1749 | #endif |
| 1750 | |
| 1751 | |
| 1752 | } |
| 1753 | |
| 1754 | /* |
| 1755 | * Some devices and their resources require reserved physical memory from |
| 1756 | * the end of the available RAM. This function traverses the list of devices |
Daniel Mack | 3ad2f3f | 2010-02-03 08:01:28 +0800 | [diff] [blame] | 1757 | * and assigns actual addresses to these. |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1758 | */ |
| 1759 | static void __init u300_assign_physmem(void) |
| 1760 | { |
| 1761 | unsigned long curr_start = __pa(high_memory); |
| 1762 | int i, j; |
| 1763 | |
| 1764 | for (i = 0; i < ARRAY_SIZE(platform_devs); i++) { |
| 1765 | for (j = 0; j < platform_devs[i]->num_resources; j++) { |
| 1766 | struct resource *const res = |
| 1767 | &platform_devs[i]->resource[j]; |
| 1768 | |
| 1769 | if (IORESOURCE_MEM == res->flags && |
| 1770 | 0 == res->start) { |
| 1771 | res->start = curr_start; |
| 1772 | res->end += curr_start; |
Joe Perches | 28f65c11 | 2011-06-09 09:13:32 -0700 | [diff] [blame] | 1773 | curr_start += resource_size(res); |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1774 | |
| 1775 | printk(KERN_INFO "core.c: Mapping RAM " \ |
| 1776 | "%#x-%#x to device %s:%s\n", |
| 1777 | res->start, res->end, |
| 1778 | platform_devs[i]->name, res->name); |
| 1779 | } |
| 1780 | } |
| 1781 | } |
| 1782 | } |
| 1783 | |
| 1784 | void __init u300_init_devices(void) |
| 1785 | { |
| 1786 | int i; |
| 1787 | u16 val; |
| 1788 | |
| 1789 | /* Check what platform we run and print some status information */ |
| 1790 | u300_init_check_chip(); |
| 1791 | |
| 1792 | /* Set system to run at PLL208, max performance, a known state. */ |
| 1793 | val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); |
| 1794 | val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK; |
| 1795 | writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); |
| 1796 | /* Wait for the PLL208 to lock if not locked in yet */ |
| 1797 | while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) & |
| 1798 | U300_SYSCON_CSR_PLL208_LOCK_IND)); |
Linus Walleij | c7c8c78 | 2009-08-14 10:59:05 +0100 | [diff] [blame] | 1799 | /* Initialize SPI device with some board specifics */ |
| 1800 | u300_spi_init(&pl022_device); |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1801 | |
| 1802 | /* Register the AMBA devices in the AMBA bus abstraction layer */ |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1803 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { |
| 1804 | struct amba_device *d = amba_devs[i]; |
| 1805 | amba_device_register(d, &iomem_resource); |
| 1806 | } |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1807 | |
| 1808 | u300_assign_physmem(); |
| 1809 | |
Linus Walleij | 98da352 | 2011-05-02 20:54:38 +0200 | [diff] [blame] | 1810 | /* Initialize pinmuxing */ |
| 1811 | pinmux_register_mappings(u300_pinmux_map, |
| 1812 | ARRAY_SIZE(u300_pinmux_map)); |
| 1813 | |
Linus Walleij | 6be2a0c | 2009-08-13 21:42:01 +0100 | [diff] [blame] | 1814 | /* Register subdevices on the I2C buses */ |
| 1815 | u300_i2c_register_board_devices(); |
| 1816 | |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1817 | /* Register the platform devices */ |
| 1818 | platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); |
| 1819 | |
Linus Walleij | ec8f125 | 2010-08-13 11:31:59 +0200 | [diff] [blame] | 1820 | /* Register subdevices on the SPI bus */ |
| 1821 | u300_spi_register_board_devices(); |
| 1822 | |
Linus Walleij | c43ed56 | 2011-08-09 21:30:01 +0200 | [diff] [blame] | 1823 | /* Enable SEMI self refresh */ |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1824 | val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) | |
| 1825 | U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE; |
| 1826 | writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR); |
Linus Walleij | bb3cee2 | 2009-04-23 10:22:13 +0100 | [diff] [blame] | 1827 | } |
| 1828 | |
| 1829 | static int core_module_init(void) |
| 1830 | { |
| 1831 | /* |
| 1832 | * This needs to be initialized later: it needs the input framework |
| 1833 | * to be initialized first. |
| 1834 | */ |
| 1835 | return mmc_init(&mmcsd_device); |
| 1836 | } |
| 1837 | module_init(core_module_init); |
Russell King | 7e3974b | 2011-11-05 15:51:25 +0000 | [diff] [blame] | 1838 | |
| 1839 | /* Forward declare this function from the watchdog */ |
| 1840 | void coh901327_watchdog_reset(void); |
| 1841 | |
| 1842 | void u300_restart(char mode, const char *cmd) |
| 1843 | { |
| 1844 | switch (mode) { |
| 1845 | case 's': |
| 1846 | case 'h': |
Russell King | 7e3974b | 2011-11-05 15:51:25 +0000 | [diff] [blame] | 1847 | #ifdef CONFIG_COH901327_WATCHDOG |
| 1848 | coh901327_watchdog_reset(); |
| 1849 | #endif |
| 1850 | break; |
| 1851 | default: |
| 1852 | /* Do nothing */ |
| 1853 | break; |
| 1854 | } |
| 1855 | /* Wait for system do die/reset. */ |
| 1856 | while (1); |
| 1857 | } |