Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Versatile Express Core Tile Cortex A9x4 Support |
| 3 | */ |
| 4 | #include <linux/init.h> |
Tejun Heo | 68aaae9 | 2010-03-30 02:52:45 +0900 | [diff] [blame] | 5 | #include <linux/gfp.h> |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 6 | #include <linux/device.h> |
| 7 | #include <linux/dma-mapping.h> |
Will Deacon | f417cba | 2010-04-15 10:16:26 +0100 | [diff] [blame] | 8 | #include <linux/platform_device.h> |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 9 | #include <linux/amba/bus.h> |
| 10 | #include <linux/amba/clcd.h> |
Jean-Christop PLAGNIOL-VILLARD | 6d803ba | 2010-11-17 10:04:33 +0100 | [diff] [blame] | 11 | #include <linux/clkdev.h> |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 12 | |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 13 | #include <asm/hardware/arm_timer.h> |
| 14 | #include <asm/hardware/cache-l2x0.h> |
| 15 | #include <asm/hardware/gic.h> |
Will Deacon | f417cba | 2010-04-15 10:16:26 +0100 | [diff] [blame] | 16 | #include <asm/pmu.h> |
Will Deacon | 80b5efbd | 2011-02-28 17:01:04 +0100 | [diff] [blame] | 17 | #include <asm/smp_scu.h> |
Will Deacon | bde28b8 | 2010-07-09 13:52:09 +0100 | [diff] [blame] | 18 | #include <asm/smp_twd.h> |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 19 | |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 20 | #include <mach/ct-ca9x4.h> |
| 21 | |
Rob Herring | 8a9618f | 2010-10-06 16:18:08 +0100 | [diff] [blame] | 22 | #include <asm/hardware/timer-sp.h> |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 23 | |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 24 | #include <asm/mach/map.h> |
| 25 | #include <asm/mach/time.h> |
| 26 | |
| 27 | #include "core.h" |
| 28 | |
| 29 | #include <mach/motherboard.h> |
| 30 | |
Russell King | 0fb44b9 | 2011-01-18 20:13:51 +0000 | [diff] [blame] | 31 | #include <plat/clcd.h> |
| 32 | |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 33 | #define V2M_PA_CS7 0x10000000 |
| 34 | |
| 35 | static struct map_desc ct_ca9x4_io_desc[] __initdata = { |
| 36 | { |
| 37 | .virtual = __MMIO_P2V(CT_CA9X4_MPIC), |
| 38 | .pfn = __phys_to_pfn(CT_CA9X4_MPIC), |
| 39 | .length = SZ_16K, |
| 40 | .type = MT_DEVICE, |
| 41 | }, { |
| 42 | .virtual = __MMIO_P2V(CT_CA9X4_SP804_TIMER), |
| 43 | .pfn = __phys_to_pfn(CT_CA9X4_SP804_TIMER), |
| 44 | .length = SZ_4K, |
| 45 | .type = MT_DEVICE, |
| 46 | }, { |
| 47 | .virtual = __MMIO_P2V(CT_CA9X4_L2CC), |
| 48 | .pfn = __phys_to_pfn(CT_CA9X4_L2CC), |
| 49 | .length = SZ_4K, |
| 50 | .type = MT_DEVICE, |
| 51 | }, |
| 52 | }; |
| 53 | |
| 54 | static void __init ct_ca9x4_map_io(void) |
| 55 | { |
Will Deacon | e56c010 | 2010-11-10 15:59:11 +0100 | [diff] [blame] | 56 | #ifdef CONFIG_LOCAL_TIMERS |
Will Deacon | bde28b8 | 2010-07-09 13:52:09 +0100 | [diff] [blame] | 57 | twd_base = MMIO_P2V(A9_MPCORE_TWD); |
Will Deacon | e56c010 | 2010-11-10 15:59:11 +0100 | [diff] [blame] | 58 | #endif |
Will Deacon | 80b5efbd | 2011-02-28 17:01:04 +0100 | [diff] [blame] | 59 | iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc)); |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 60 | } |
| 61 | |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 62 | static void __init ct_ca9x4_init_irq(void) |
| 63 | { |
Russell King | ff2e27a | 2010-12-04 16:13:29 +0000 | [diff] [blame] | 64 | gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST), |
| 65 | MMIO_P2V(A9_MPCORE_GIC_CPU)); |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 66 | } |
| 67 | |
| 68 | #if 0 |
Russell King | cdaf9a2 | 2010-10-05 11:29:28 +0100 | [diff] [blame] | 69 | static void __init ct_ca9x4_timer_init(void) |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 70 | { |
| 71 | writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL); |
| 72 | writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL); |
| 73 | |
Russell King | fb593cf | 2011-05-12 12:08:23 +0100 | [diff] [blame] | 74 | sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), "ct-timer1"); |
Russell King | 57cc4f7 | 2011-05-12 15:31:13 +0100 | [diff] [blame] | 75 | sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0, |
| 76 | "ct-timer0"); |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 77 | } |
| 78 | |
| 79 | static struct sys_timer ct_ca9x4_timer = { |
| 80 | .init = ct_ca9x4_timer_init, |
| 81 | }; |
| 82 | #endif |
| 83 | |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 84 | static void ct_ca9x4_clcd_enable(struct clcd_fb *fb) |
| 85 | { |
| 86 | v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0); |
| 87 | v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE_DB1, 2); |
| 88 | } |
| 89 | |
| 90 | static int ct_ca9x4_clcd_setup(struct clcd_fb *fb) |
| 91 | { |
| 92 | unsigned long framesize = 1024 * 768 * 2; |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 93 | |
Russell King | 0fb44b9 | 2011-01-18 20:13:51 +0000 | [diff] [blame] | 94 | fb->panel = versatile_clcd_get_panel("XVGA"); |
| 95 | if (!fb->panel) |
| 96 | return -EINVAL; |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 97 | |
Russell King | 0fb44b9 | 2011-01-18 20:13:51 +0000 | [diff] [blame] | 98 | return versatile_clcd_setup_dma(fb, framesize); |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 99 | } |
| 100 | |
| 101 | static struct clcd_board ct_ca9x4_clcd_data = { |
| 102 | .name = "CT-CA9X4", |
Russell King | 0fb44b9 | 2011-01-18 20:13:51 +0000 | [diff] [blame] | 103 | .caps = CLCD_CAP_5551 | CLCD_CAP_565, |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 104 | .check = clcdfb_check, |
| 105 | .decode = clcdfb_decode, |
| 106 | .enable = ct_ca9x4_clcd_enable, |
| 107 | .setup = ct_ca9x4_clcd_setup, |
Russell King | 0fb44b9 | 2011-01-18 20:13:51 +0000 | [diff] [blame] | 108 | .mmap = versatile_clcd_mmap_dma, |
| 109 | .remove = versatile_clcd_remove_dma, |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 110 | }; |
| 111 | |
Russell King | cdd4e1a | 2011-12-18 12:07:09 +0000 | [diff] [blame] | 112 | static AMBA_AHB_DEVICE(clcd, "ct:clcd", 0, CT_CA9X4_CLCDC, IRQ_CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data); |
| 113 | static AMBA_APB_DEVICE(dmc, "ct:dmc", 0, CT_CA9X4_DMC, IRQ_CT_CA9X4_DMC, NULL); |
| 114 | static AMBA_APB_DEVICE(smc, "ct:smc", 0, CT_CA9X4_SMC, IRQ_CT_CA9X4_SMC, NULL); |
| 115 | static AMBA_APB_DEVICE(gpio, "ct:gpio", 0, CT_CA9X4_GPIO, IRQ_CT_CA9X4_GPIO, NULL); |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 116 | |
| 117 | static struct amba_device *ct_ca9x4_amba_devs[] __initdata = { |
| 118 | &clcd_device, |
| 119 | &dmc_device, |
| 120 | &smc_device, |
| 121 | &gpio_device, |
| 122 | }; |
| 123 | |
| 124 | |
| 125 | static long ct_round(struct clk *clk, unsigned long rate) |
| 126 | { |
| 127 | return rate; |
| 128 | } |
| 129 | |
| 130 | static int ct_set(struct clk *clk, unsigned long rate) |
| 131 | { |
| 132 | return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_DB1 | 1, rate); |
| 133 | } |
| 134 | |
| 135 | static const struct clk_ops osc1_clk_ops = { |
| 136 | .round = ct_round, |
| 137 | .set = ct_set, |
| 138 | }; |
| 139 | |
| 140 | static struct clk osc1_clk = { |
| 141 | .ops = &osc1_clk_ops, |
| 142 | .rate = 24000000, |
| 143 | }; |
| 144 | |
Russell King | 7ff550d | 2011-05-12 13:31:48 +0100 | [diff] [blame] | 145 | static struct clk ct_sp804_clk = { |
| 146 | .rate = 1000000, |
| 147 | }; |
| 148 | |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 149 | static struct clk_lookup lookups[] = { |
| 150 | { /* CLCD */ |
| 151 | .dev_id = "ct:clcd", |
| 152 | .clk = &osc1_clk, |
Russell King | 7ff550d | 2011-05-12 13:31:48 +0100 | [diff] [blame] | 153 | }, { /* SP804 timers */ |
| 154 | .dev_id = "sp804", |
Russell King | 23828a7 | 2011-05-12 15:45:16 +0100 | [diff] [blame] | 155 | .con_id = "ct-timer0", |
| 156 | .clk = &ct_sp804_clk, |
| 157 | }, { /* SP804 timers */ |
| 158 | .dev_id = "sp804", |
Russell King | 7ff550d | 2011-05-12 13:31:48 +0100 | [diff] [blame] | 159 | .con_id = "ct-timer1", |
| 160 | .clk = &ct_sp804_clk, |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 161 | }, |
| 162 | }; |
| 163 | |
Will Deacon | f417cba | 2010-04-15 10:16:26 +0100 | [diff] [blame] | 164 | static struct resource pmu_resources[] = { |
| 165 | [0] = { |
| 166 | .start = IRQ_CT_CA9X4_PMU_CPU0, |
| 167 | .end = IRQ_CT_CA9X4_PMU_CPU0, |
| 168 | .flags = IORESOURCE_IRQ, |
| 169 | }, |
| 170 | [1] = { |
| 171 | .start = IRQ_CT_CA9X4_PMU_CPU1, |
| 172 | .end = IRQ_CT_CA9X4_PMU_CPU1, |
| 173 | .flags = IORESOURCE_IRQ, |
| 174 | }, |
| 175 | [2] = { |
| 176 | .start = IRQ_CT_CA9X4_PMU_CPU2, |
| 177 | .end = IRQ_CT_CA9X4_PMU_CPU2, |
| 178 | .flags = IORESOURCE_IRQ, |
| 179 | }, |
| 180 | [3] = { |
| 181 | .start = IRQ_CT_CA9X4_PMU_CPU3, |
| 182 | .end = IRQ_CT_CA9X4_PMU_CPU3, |
| 183 | .flags = IORESOURCE_IRQ, |
| 184 | }, |
| 185 | }; |
| 186 | |
| 187 | static struct platform_device pmu_device = { |
| 188 | .name = "arm-pmu", |
| 189 | .id = ARM_PMU_DEVICE_CPU, |
| 190 | .num_resources = ARRAY_SIZE(pmu_resources), |
| 191 | .resource = pmu_resources, |
| 192 | }; |
| 193 | |
Russell King | 493a451 | 2011-01-11 13:07:52 +0000 | [diff] [blame] | 194 | static void __init ct_ca9x4_init_early(void) |
| 195 | { |
| 196 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); |
Russell King | 493a451 | 2011-01-11 13:07:52 +0000 | [diff] [blame] | 197 | } |
| 198 | |
Russell King | cdaf9a2 | 2010-10-05 11:29:28 +0100 | [diff] [blame] | 199 | static void __init ct_ca9x4_init(void) |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 200 | { |
| 201 | int i; |
| 202 | |
| 203 | #ifdef CONFIG_CACHE_L2X0 |
Will Deacon | 2de59fe | 2010-09-27 14:55:15 +0100 | [diff] [blame] | 204 | void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC); |
| 205 | |
| 206 | /* set RAM latencies to 1 cycle for this core tile. */ |
| 207 | writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL); |
| 208 | writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL); |
| 209 | |
| 210 | l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff); |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 211 | #endif |
| 212 | |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 213 | for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++) |
| 214 | amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource); |
Will Deacon | f417cba | 2010-04-15 10:16:26 +0100 | [diff] [blame] | 215 | |
| 216 | platform_device_register(&pmu_device); |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 217 | } |
| 218 | |
Will Deacon | 80b5efbd | 2011-02-28 17:01:04 +0100 | [diff] [blame] | 219 | #ifdef CONFIG_SMP |
Russell King | 94ae027 | 2012-01-18 19:40:13 +0000 | [diff] [blame] | 220 | static void __init ct_ca9x4_init_cpu_map(void) |
Will Deacon | 80b5efbd | 2011-02-28 17:01:04 +0100 | [diff] [blame] | 221 | { |
| 222 | int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU)); |
| 223 | |
Russell King | a06f916 | 2011-10-20 22:04:18 +0100 | [diff] [blame] | 224 | if (ncores > nr_cpu_ids) { |
| 225 | pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", |
| 226 | ncores, nr_cpu_ids); |
| 227 | ncores = nr_cpu_ids; |
| 228 | } |
| 229 | |
Will Deacon | 80b5efbd | 2011-02-28 17:01:04 +0100 | [diff] [blame] | 230 | for (i = 0; i < ncores; ++i) |
| 231 | set_cpu_possible(i, true); |
Russell King | 0f7b332 | 2011-04-03 13:01:30 +0100 | [diff] [blame] | 232 | |
| 233 | set_smp_cross_call(gic_raise_softirq); |
Will Deacon | 80b5efbd | 2011-02-28 17:01:04 +0100 | [diff] [blame] | 234 | } |
| 235 | |
Russell King | 94ae027 | 2012-01-18 19:40:13 +0000 | [diff] [blame] | 236 | static void __init ct_ca9x4_smp_enable(unsigned int max_cpus) |
Will Deacon | 80b5efbd | 2011-02-28 17:01:04 +0100 | [diff] [blame] | 237 | { |
Will Deacon | 80b5efbd | 2011-02-28 17:01:04 +0100 | [diff] [blame] | 238 | scu_enable(MMIO_P2V(A9_MPCORE_SCU)); |
| 239 | } |
Russell King | fef88f1 | 2010-02-28 17:26:25 +0000 | [diff] [blame] | 240 | #endif |
Will Deacon | 80b5efbd | 2011-02-28 17:01:04 +0100 | [diff] [blame] | 241 | |
| 242 | struct ct_desc ct_ca9x4_desc __initdata = { |
| 243 | .id = V2M_CT_ID_CA9, |
| 244 | .name = "CA9x4", |
| 245 | .map_io = ct_ca9x4_map_io, |
| 246 | .init_early = ct_ca9x4_init_early, |
| 247 | .init_irq = ct_ca9x4_init_irq, |
| 248 | .init_tile = ct_ca9x4_init, |
| 249 | #ifdef CONFIG_SMP |
| 250 | .init_cpu_map = ct_ca9x4_init_cpu_map, |
| 251 | .smp_enable = ct_ca9x4_smp_enable, |
| 252 | #endif |
| 253 | }; |