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Vinod Koulb3c567e2010-07-21 13:28:10 +05301/*
2 * intel_mid_dma.c - Intel Langwell DMA Drivers
3 *
4 * Copyright (C) 2008-10 Intel Corp
5 * Author: Vinod Koul <vinod.koul@intel.com>
6 * The driver design is based on dw_dmac driver
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 *
22 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
23 *
24 *
25 */
26#include <linux/pci.h>
27#include <linux/interrupt.h>
Koul, Vinod53a61ba2010-10-04 10:42:40 +000028#include <linux/pm_runtime.h>
Vinod Koulb3c567e2010-07-21 13:28:10 +053029#include <linux/intel_mid_dma.h>
Paul Gortmaker7c52d552011-05-27 12:33:10 -040030#include <linux/module.h>
Vinod Koulb3c567e2010-07-21 13:28:10 +053031
32#define MAX_CHAN 4 /*max ch across controllers*/
33#include "intel_mid_dma_regs.h"
34
35#define INTEL_MID_DMAC1_ID 0x0814
36#define INTEL_MID_DMAC2_ID 0x0813
37#define INTEL_MID_GP_DMAC2_ID 0x0827
38#define INTEL_MFLD_DMAC1_ID 0x0830
39#define LNW_PERIPHRAL_MASK_BASE 0xFFAE8008
40#define LNW_PERIPHRAL_MASK_SIZE 0x10
41#define LNW_PERIPHRAL_STATUS 0x0
42#define LNW_PERIPHRAL_MASK 0x8
43
44struct intel_mid_dma_probe_info {
45 u8 max_chan;
46 u8 ch_base;
47 u16 block_size;
48 u32 pimr_mask;
49};
50
51#define INFO(_max_chan, _ch_base, _block_size, _pimr_mask) \
52 ((kernel_ulong_t)&(struct intel_mid_dma_probe_info) { \
53 .max_chan = (_max_chan), \
54 .ch_base = (_ch_base), \
55 .block_size = (_block_size), \
56 .pimr_mask = (_pimr_mask), \
57 })
58
59/*****************************************************************************
60Utility Functions*/
61/**
62 * get_ch_index - convert status to channel
63 * @status: status mask
64 * @base: dma ch base value
65 *
66 * Modify the status mask and return the channel index needing
67 * attention (or -1 if neither)
68 */
69static int get_ch_index(int *status, unsigned int base)
70{
71 int i;
72 for (i = 0; i < MAX_CHAN; i++) {
73 if (*status & (1 << (i + base))) {
74 *status = *status & ~(1 << (i + base));
75 pr_debug("MDMA: index %d New status %x\n", i, *status);
76 return i;
77 }
78 }
79 return -1;
80}
81
82/**
83 * get_block_ts - calculates dma transaction length
84 * @len: dma transfer length
85 * @tx_width: dma transfer src width
86 * @block_size: dma controller max block size
87 *
88 * Based on src width calculate the DMA trsaction length in data items
89 * return data items or FFFF if exceeds max length for block
90 */
91static int get_block_ts(int len, int tx_width, int block_size)
92{
93 int byte_width = 0, block_ts = 0;
94
95 switch (tx_width) {
Koul, Vinod20dd6392010-10-04 10:38:43 +000096 case DMA_SLAVE_BUSWIDTH_1_BYTE:
Vinod Koulb3c567e2010-07-21 13:28:10 +053097 byte_width = 1;
98 break;
Koul, Vinod20dd6392010-10-04 10:38:43 +000099 case DMA_SLAVE_BUSWIDTH_2_BYTES:
Vinod Koulb3c567e2010-07-21 13:28:10 +0530100 byte_width = 2;
101 break;
Koul, Vinod20dd6392010-10-04 10:38:43 +0000102 case DMA_SLAVE_BUSWIDTH_4_BYTES:
Vinod Koulb3c567e2010-07-21 13:28:10 +0530103 default:
104 byte_width = 4;
105 break;
106 }
107
108 block_ts = len/byte_width;
109 if (block_ts > block_size)
110 block_ts = 0xFFFF;
111 return block_ts;
112}
113
114/*****************************************************************************
115DMAC1 interrupt Functions*/
116
117/**
118 * dmac1_mask_periphral_intr - mask the periphral interrupt
Vinod Koul4598fc22011-10-10 12:33:59 +0530119 * @mid: dma device for which masking is required
Vinod Koulb3c567e2010-07-21 13:28:10 +0530120 *
121 * Masks the DMA periphral interrupt
122 * this is valid for DMAC1 family controllers only
123 * This controller should have periphral mask registers already mapped
124 */
Vinod Koul4598fc22011-10-10 12:33:59 +0530125static void dmac1_mask_periphral_intr(struct middma_device *mid)
Vinod Koulb3c567e2010-07-21 13:28:10 +0530126{
127 u32 pimr;
Vinod Koulb3c567e2010-07-21 13:28:10 +0530128
129 if (mid->pimr_mask) {
130 pimr = readl(mid->mask_reg + LNW_PERIPHRAL_MASK);
131 pimr |= mid->pimr_mask;
132 writel(pimr, mid->mask_reg + LNW_PERIPHRAL_MASK);
133 }
134 return;
135}
136
137/**
138 * dmac1_unmask_periphral_intr - unmask the periphral interrupt
139 * @midc: dma channel for which masking is required
140 *
141 * UnMasks the DMA periphral interrupt,
142 * this is valid for DMAC1 family controllers only
143 * This controller should have periphral mask registers already mapped
144 */
145static void dmac1_unmask_periphral_intr(struct intel_mid_dma_chan *midc)
146{
147 u32 pimr;
148 struct middma_device *mid = to_middma_device(midc->chan.device);
149
150 if (mid->pimr_mask) {
151 pimr = readl(mid->mask_reg + LNW_PERIPHRAL_MASK);
152 pimr &= ~mid->pimr_mask;
153 writel(pimr, mid->mask_reg + LNW_PERIPHRAL_MASK);
154 }
155 return;
156}
157
158/**
159 * enable_dma_interrupt - enable the periphral interrupt
160 * @midc: dma channel for which enable interrupt is required
161 *
162 * Enable the DMA periphral interrupt,
163 * this is valid for DMAC1 family controllers only
164 * This controller should have periphral mask registers already mapped
165 */
166static void enable_dma_interrupt(struct intel_mid_dma_chan *midc)
167{
168 dmac1_unmask_periphral_intr(midc);
169
170 /*en ch interrupts*/
171 iowrite32(UNMASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_TFR);
172 iowrite32(UNMASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_ERR);
173 return;
174}
175
176/**
177 * disable_dma_interrupt - disable the periphral interrupt
178 * @midc: dma channel for which disable interrupt is required
179 *
180 * Disable the DMA periphral interrupt,
181 * this is valid for DMAC1 family controllers only
182 * This controller should have periphral mask registers already mapped
183 */
184static void disable_dma_interrupt(struct intel_mid_dma_chan *midc)
185{
186 /*Check LPE PISR, make sure fwd is disabled*/
Vinod Koulb3c567e2010-07-21 13:28:10 +0530187 iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_BLOCK);
188 iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_TFR);
189 iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_ERR);
190 return;
191}
192
193/*****************************************************************************
194DMA channel helper Functions*/
195/**
196 * mid_desc_get - get a descriptor
197 * @midc: dma channel for which descriptor is required
198 *
199 * Obtain a descriptor for the channel. Returns NULL if none are free.
200 * Once the descriptor is returned it is private until put on another
201 * list or freed
202 */
203static struct intel_mid_dma_desc *midc_desc_get(struct intel_mid_dma_chan *midc)
204{
205 struct intel_mid_dma_desc *desc, *_desc;
206 struct intel_mid_dma_desc *ret = NULL;
207
208 spin_lock_bh(&midc->lock);
209 list_for_each_entry_safe(desc, _desc, &midc->free_list, desc_node) {
210 if (async_tx_test_ack(&desc->txd)) {
211 list_del(&desc->desc_node);
212 ret = desc;
213 break;
214 }
215 }
216 spin_unlock_bh(&midc->lock);
217 return ret;
218}
219
220/**
221 * mid_desc_put - put a descriptor
222 * @midc: dma channel for which descriptor is required
223 * @desc: descriptor to put
224 *
225 * Return a descriptor from lwn_desc_get back to the free pool
226 */
227static void midc_desc_put(struct intel_mid_dma_chan *midc,
228 struct intel_mid_dma_desc *desc)
229{
230 if (desc) {
231 spin_lock_bh(&midc->lock);
232 list_add_tail(&desc->desc_node, &midc->free_list);
233 spin_unlock_bh(&midc->lock);
234 }
235}
236/**
237 * midc_dostart - begin a DMA transaction
238 * @midc: channel for which txn is to be started
239 * @first: first descriptor of series
240 *
241 * Load a transaction into the engine. This must be called with midc->lock
242 * held and bh disabled.
243 */
244static void midc_dostart(struct intel_mid_dma_chan *midc,
245 struct intel_mid_dma_desc *first)
246{
247 struct middma_device *mid = to_middma_device(midc->chan.device);
248
249 /* channel is idle */
Koul, Vinod53a61ba2010-10-04 10:42:40 +0000250 if (midc->busy && test_ch_en(midc->dma_base, midc->ch_id)) {
Vinod Koulb3c567e2010-07-21 13:28:10 +0530251 /*error*/
252 pr_err("ERR_MDMA: channel is busy in start\n");
253 /* The tasklet will hopefully advance the queue... */
254 return;
255 }
Koul, Vinod53a61ba2010-10-04 10:42:40 +0000256 midc->busy = true;
Vinod Koulb3c567e2010-07-21 13:28:10 +0530257 /*write registers and en*/
258 iowrite32(first->sar, midc->ch_regs + SAR);
259 iowrite32(first->dar, midc->ch_regs + DAR);
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000260 iowrite32(first->lli_phys, midc->ch_regs + LLP);
Vinod Koulb3c567e2010-07-21 13:28:10 +0530261 iowrite32(first->cfg_hi, midc->ch_regs + CFG_HIGH);
262 iowrite32(first->cfg_lo, midc->ch_regs + CFG_LOW);
263 iowrite32(first->ctl_lo, midc->ch_regs + CTL_LOW);
264 iowrite32(first->ctl_hi, midc->ch_regs + CTL_HIGH);
265 pr_debug("MDMA:TX SAR %x,DAR %x,CFGL %x,CFGH %x,CTLH %x, CTLL %x\n",
266 (int)first->sar, (int)first->dar, first->cfg_hi,
267 first->cfg_lo, first->ctl_hi, first->ctl_lo);
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000268 first->status = DMA_IN_PROGRESS;
Vinod Koulb3c567e2010-07-21 13:28:10 +0530269
270 iowrite32(ENABLE_CHANNEL(midc->ch_id), mid->dma_base + DMA_CHAN_EN);
Vinod Koulb3c567e2010-07-21 13:28:10 +0530271}
272
273/**
274 * midc_descriptor_complete - process completed descriptor
275 * @midc: channel owning the descriptor
276 * @desc: the descriptor itself
277 *
278 * Process a completed descriptor and perform any callbacks upon
279 * the completion. The completion handling drops the lock during the
280 * callbacks but must be called with the lock held.
281 */
282static void midc_descriptor_complete(struct intel_mid_dma_chan *midc,
Adrian Hunter1fded072011-12-16 11:01:38 +0200283 struct intel_mid_dma_desc *desc)
284 __releases(&midc->lock) __acquires(&midc->lock)
Vinod Koulb3c567e2010-07-21 13:28:10 +0530285{
286 struct dma_async_tx_descriptor *txd = &desc->txd;
287 dma_async_tx_callback callback_txd = NULL;
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000288 struct intel_mid_dma_lli *llitem;
Vinod Koulb3c567e2010-07-21 13:28:10 +0530289 void *param_txd = NULL;
290
291 midc->completed = txd->cookie;
292 callback_txd = txd->callback;
293 param_txd = txd->callback_param;
294
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000295 if (desc->lli != NULL) {
296 /*clear the DONE bit of completed LLI in memory*/
297 llitem = desc->lli + desc->current_lli;
298 llitem->ctl_hi &= CLEAR_DONE;
299 if (desc->current_lli < desc->lli_length-1)
300 (desc->current_lli)++;
301 else
302 desc->current_lli = 0;
303 }
Vinod Koulb3c567e2010-07-21 13:28:10 +0530304 spin_unlock_bh(&midc->lock);
305 if (callback_txd) {
306 pr_debug("MDMA: TXD callback set ... calling\n");
307 callback_txd(param_txd);
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000308 }
309 if (midc->raw_tfr) {
310 desc->status = DMA_SUCCESS;
311 if (desc->lli != NULL) {
312 pci_pool_free(desc->lli_pool, desc->lli,
313 desc->lli_phys);
314 pci_pool_destroy(desc->lli_pool);
Adrian Hunter1fded072011-12-16 11:01:38 +0200315 desc->lli = NULL;
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000316 }
317 list_move(&desc->desc_node, &midc->free_list);
318 midc->busy = false;
Vinod Koulb3c567e2010-07-21 13:28:10 +0530319 }
320 spin_lock_bh(&midc->lock);
321
322}
323/**
324 * midc_scan_descriptors - check the descriptors in channel
325 * mark completed when tx is completete
326 * @mid: device
327 * @midc: channel to scan
328 *
329 * Walk the descriptor chain for the device and process any entries
330 * that are complete.
331 */
332static void midc_scan_descriptors(struct middma_device *mid,
333 struct intel_mid_dma_chan *midc)
334{
335 struct intel_mid_dma_desc *desc = NULL, *_desc = NULL;
336
337 /*tx is complete*/
338 list_for_each_entry_safe(desc, _desc, &midc->active_list, desc_node) {
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000339 if (desc->status == DMA_IN_PROGRESS)
Vinod Koulb3c567e2010-07-21 13:28:10 +0530340 midc_descriptor_complete(midc, desc);
Vinod Koulb3c567e2010-07-21 13:28:10 +0530341 }
342 return;
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000343 }
344/**
345 * midc_lli_fill_sg - Helper function to convert
346 * SG list to Linked List Items.
347 *@midc: Channel
348 *@desc: DMA descriptor
349 *@sglist: Pointer to SG list
350 *@sglen: SG list length
351 *@flags: DMA transaction flags
352 *
353 * Walk through the SG list and convert the SG list into Linked
354 * List Items (LLI).
355 */
356static int midc_lli_fill_sg(struct intel_mid_dma_chan *midc,
357 struct intel_mid_dma_desc *desc,
358 struct scatterlist *sglist,
359 unsigned int sglen,
360 unsigned int flags)
361{
362 struct intel_mid_dma_slave *mids;
363 struct scatterlist *sg;
364 dma_addr_t lli_next, sg_phy_addr;
365 struct intel_mid_dma_lli *lli_bloc_desc;
366 union intel_mid_dma_ctl_lo ctl_lo;
367 union intel_mid_dma_ctl_hi ctl_hi;
368 int i;
Vinod Koulb3c567e2010-07-21 13:28:10 +0530369
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000370 pr_debug("MDMA: Entered midc_lli_fill_sg\n");
Koul, Vinod20dd6392010-10-04 10:38:43 +0000371 mids = midc->mid_slave;
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000372
373 lli_bloc_desc = desc->lli;
374 lli_next = desc->lli_phys;
375
376 ctl_lo.ctl_lo = desc->ctl_lo;
377 ctl_hi.ctl_hi = desc->ctl_hi;
378 for_each_sg(sglist, sg, sglen, i) {
379 /*Populate CTL_LOW and LLI values*/
380 if (i != sglen - 1) {
381 lli_next = lli_next +
382 sizeof(struct intel_mid_dma_lli);
383 } else {
384 /*Check for circular list, otherwise terminate LLI to ZERO*/
385 if (flags & DMA_PREP_CIRCULAR_LIST) {
386 pr_debug("MDMA: LLI is configured in circular mode\n");
387 lli_next = desc->lli_phys;
388 } else {
389 lli_next = 0;
390 ctl_lo.ctlx.llp_dst_en = 0;
391 ctl_lo.ctlx.llp_src_en = 0;
392 }
393 }
394 /*Populate CTL_HI values*/
395 ctl_hi.ctlx.block_ts = get_block_ts(sg->length,
396 desc->width,
397 midc->dma->block_size);
398 /*Populate SAR and DAR values*/
399 sg_phy_addr = sg_phys(sg);
Vinod Kouldb8196d2011-10-13 22:34:23 +0530400 if (desc->dirn == DMA_MEM_TO_DEV) {
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000401 lli_bloc_desc->sar = sg_phy_addr;
Koul, Vinod20dd6392010-10-04 10:38:43 +0000402 lli_bloc_desc->dar = mids->dma_slave.dst_addr;
Vinod Kouldb8196d2011-10-13 22:34:23 +0530403 } else if (desc->dirn == DMA_DEV_TO_MEM) {
Koul, Vinod20dd6392010-10-04 10:38:43 +0000404 lli_bloc_desc->sar = mids->dma_slave.src_addr;
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000405 lli_bloc_desc->dar = sg_phy_addr;
406 }
407 /*Copy values into block descriptor in system memroy*/
408 lli_bloc_desc->llp = lli_next;
409 lli_bloc_desc->ctl_lo = ctl_lo.ctl_lo;
410 lli_bloc_desc->ctl_hi = ctl_hi.ctl_hi;
411
412 lli_bloc_desc++;
413 }
414 /*Copy very first LLI values to descriptor*/
415 desc->ctl_lo = desc->lli->ctl_lo;
416 desc->ctl_hi = desc->lli->ctl_hi;
417 desc->sar = desc->lli->sar;
418 desc->dar = desc->lli->dar;
419
420 return 0;
421}
Vinod Koulb3c567e2010-07-21 13:28:10 +0530422/*****************************************************************************
423DMA engine callback Functions*/
424/**
425 * intel_mid_dma_tx_submit - callback to submit DMA transaction
426 * @tx: dma engine descriptor
427 *
428 * Submit the DMA trasaction for this descriptor, start if ch idle
429 */
430static dma_cookie_t intel_mid_dma_tx_submit(struct dma_async_tx_descriptor *tx)
431{
432 struct intel_mid_dma_desc *desc = to_intel_mid_dma_desc(tx);
433 struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(tx->chan);
434 dma_cookie_t cookie;
435
436 spin_lock_bh(&midc->lock);
437 cookie = midc->chan.cookie;
438
439 if (++cookie < 0)
440 cookie = 1;
441
442 midc->chan.cookie = cookie;
443 desc->txd.cookie = cookie;
444
445
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000446 if (list_empty(&midc->active_list))
Vinod Koulb3c567e2010-07-21 13:28:10 +0530447 list_add_tail(&desc->desc_node, &midc->active_list);
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000448 else
Vinod Koulb3c567e2010-07-21 13:28:10 +0530449 list_add_tail(&desc->desc_node, &midc->queue);
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000450
451 midc_dostart(midc, desc);
Vinod Koulb3c567e2010-07-21 13:28:10 +0530452 spin_unlock_bh(&midc->lock);
453
454 return cookie;
455}
456
457/**
458 * intel_mid_dma_issue_pending - callback to issue pending txn
459 * @chan: chan where pending trascation needs to be checked and submitted
460 *
461 * Call for scan to issue pending descriptors
462 */
463static void intel_mid_dma_issue_pending(struct dma_chan *chan)
464{
465 struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan);
466
467 spin_lock_bh(&midc->lock);
468 if (!list_empty(&midc->queue))
469 midc_scan_descriptors(to_middma_device(chan->device), midc);
470 spin_unlock_bh(&midc->lock);
471}
472
473/**
474 * intel_mid_dma_tx_status - Return status of txn
475 * @chan: chan for where status needs to be checked
476 * @cookie: cookie for txn
477 * @txstate: DMA txn state
478 *
479 * Return status of DMA txn
480 */
481static enum dma_status intel_mid_dma_tx_status(struct dma_chan *chan,
482 dma_cookie_t cookie,
483 struct dma_tx_state *txstate)
484{
485 struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan);
486 dma_cookie_t last_used;
487 dma_cookie_t last_complete;
488 int ret;
489
490 last_complete = midc->completed;
491 last_used = chan->cookie;
492
493 ret = dma_async_is_complete(cookie, last_complete, last_used);
494 if (ret != DMA_SUCCESS) {
Adrian Hunter1fded072011-12-16 11:01:38 +0200495 spin_lock_bh(&midc->lock);
Vinod Koulb3c567e2010-07-21 13:28:10 +0530496 midc_scan_descriptors(to_middma_device(chan->device), midc);
Adrian Hunter1fded072011-12-16 11:01:38 +0200497 spin_unlock_bh(&midc->lock);
Vinod Koulb3c567e2010-07-21 13:28:10 +0530498
499 last_complete = midc->completed;
500 last_used = chan->cookie;
501
502 ret = dma_async_is_complete(cookie, last_complete, last_used);
503 }
504
505 if (txstate) {
506 txstate->last = last_complete;
507 txstate->used = last_used;
508 txstate->residue = 0;
509 }
510 return ret;
511}
512
Koul, Vinod20dd6392010-10-04 10:38:43 +0000513static int dma_slave_control(struct dma_chan *chan, unsigned long arg)
514{
515 struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan);
516 struct dma_slave_config *slave = (struct dma_slave_config *)arg;
517 struct intel_mid_dma_slave *mid_slave;
518
519 BUG_ON(!midc);
520 BUG_ON(!slave);
521 pr_debug("MDMA: slave control called\n");
522
523 mid_slave = to_intel_mid_dma_slave(slave);
524
525 BUG_ON(!mid_slave);
526
527 midc->mid_slave = mid_slave;
528 return 0;
529}
Vinod Koulb3c567e2010-07-21 13:28:10 +0530530/**
531 * intel_mid_dma_device_control - DMA device control
532 * @chan: chan for DMA control
533 * @cmd: control cmd
534 * @arg: cmd arg value
535 *
536 * Perform DMA control command
537 */
538static int intel_mid_dma_device_control(struct dma_chan *chan,
539 enum dma_ctrl_cmd cmd, unsigned long arg)
540{
541 struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan);
542 struct middma_device *mid = to_middma_device(chan->device);
543 struct intel_mid_dma_desc *desc, *_desc;
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000544 union intel_mid_dma_cfg_lo cfg_lo;
Vinod Koulb3c567e2010-07-21 13:28:10 +0530545
Koul, Vinod20dd6392010-10-04 10:38:43 +0000546 if (cmd == DMA_SLAVE_CONFIG)
547 return dma_slave_control(chan, arg);
548
Vinod Koulb3c567e2010-07-21 13:28:10 +0530549 if (cmd != DMA_TERMINATE_ALL)
550 return -ENXIO;
551
552 spin_lock_bh(&midc->lock);
Koul, Vinod53a61ba2010-10-04 10:42:40 +0000553 if (midc->busy == false) {
Vinod Koulb3c567e2010-07-21 13:28:10 +0530554 spin_unlock_bh(&midc->lock);
555 return 0;
556 }
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000557 /*Suspend and disable the channel*/
558 cfg_lo.cfg_lo = ioread32(midc->ch_regs + CFG_LOW);
559 cfg_lo.cfgx.ch_susp = 1;
560 iowrite32(cfg_lo.cfg_lo, midc->ch_regs + CFG_LOW);
561 iowrite32(DISABLE_CHANNEL(midc->ch_id), mid->dma_base + DMA_CHAN_EN);
562 midc->busy = false;
563 /* Disable interrupts */
564 disable_dma_interrupt(midc);
Vinod Koulb3c567e2010-07-21 13:28:10 +0530565 midc->descs_allocated = 0;
Vinod Koulb3c567e2010-07-21 13:28:10 +0530566
Vinod Koulb3c567e2010-07-21 13:28:10 +0530567 spin_unlock_bh(&midc->lock);
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000568 list_for_each_entry_safe(desc, _desc, &midc->active_list, desc_node) {
569 if (desc->lli != NULL) {
570 pci_pool_free(desc->lli_pool, desc->lli,
571 desc->lli_phys);
572 pci_pool_destroy(desc->lli_pool);
Adrian Hunter1fded072011-12-16 11:01:38 +0200573 desc->lli = NULL;
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000574 }
575 list_move(&desc->desc_node, &midc->free_list);
Vinod Koulb3c567e2010-07-21 13:28:10 +0530576 }
577 return 0;
578}
579
Vinod Koulb3c567e2010-07-21 13:28:10 +0530580
581/**
582 * intel_mid_dma_prep_memcpy - Prep memcpy txn
583 * @chan: chan for DMA transfer
584 * @dest: destn address
585 * @src: src address
586 * @len: DMA transfer len
587 * @flags: DMA flags
588 *
589 * Perform a DMA memcpy. Note we support slave periphral DMA transfers only
590 * The periphral txn details should be filled in slave structure properly
591 * Returns the descriptor for this txn
592 */
593static struct dma_async_tx_descriptor *intel_mid_dma_prep_memcpy(
594 struct dma_chan *chan, dma_addr_t dest,
595 dma_addr_t src, size_t len, unsigned long flags)
596{
597 struct intel_mid_dma_chan *midc;
598 struct intel_mid_dma_desc *desc = NULL;
599 struct intel_mid_dma_slave *mids;
600 union intel_mid_dma_ctl_lo ctl_lo;
601 union intel_mid_dma_ctl_hi ctl_hi;
602 union intel_mid_dma_cfg_lo cfg_lo;
603 union intel_mid_dma_cfg_hi cfg_hi;
Koul, Vinod20dd6392010-10-04 10:38:43 +0000604 enum dma_slave_buswidth width;
Vinod Koulb3c567e2010-07-21 13:28:10 +0530605
606 pr_debug("MDMA: Prep for memcpy\n");
Koul, Vinod8b649222010-10-04 10:38:25 +0000607 BUG_ON(!chan);
Vinod Koulb3c567e2010-07-21 13:28:10 +0530608 if (!len)
609 return NULL;
610
Vinod Koulb3c567e2010-07-21 13:28:10 +0530611 midc = to_intel_mid_dma_chan(chan);
Koul, Vinod8b649222010-10-04 10:38:25 +0000612 BUG_ON(!midc);
Vinod Koulb3c567e2010-07-21 13:28:10 +0530613
Koul, Vinod20dd6392010-10-04 10:38:43 +0000614 mids = midc->mid_slave;
615 BUG_ON(!mids);
616
Vinod Koulb3c567e2010-07-21 13:28:10 +0530617 pr_debug("MDMA:called for DMA %x CH %d Length %zu\n",
618 midc->dma->pci_id, midc->ch_id, len);
619 pr_debug("MDMA:Cfg passed Mode %x, Dirn %x, HS %x, Width %x\n",
Koul, Vinod20dd6392010-10-04 10:38:43 +0000620 mids->cfg_mode, mids->dma_slave.direction,
621 mids->hs_mode, mids->dma_slave.src_addr_width);
Vinod Koulb3c567e2010-07-21 13:28:10 +0530622
623 /*calculate CFG_LO*/
624 if (mids->hs_mode == LNW_DMA_SW_HS) {
625 cfg_lo.cfg_lo = 0;
626 cfg_lo.cfgx.hs_sel_dst = 1;
627 cfg_lo.cfgx.hs_sel_src = 1;
628 } else if (mids->hs_mode == LNW_DMA_HW_HS)
629 cfg_lo.cfg_lo = 0x00000;
630
631 /*calculate CFG_HI*/
632 if (mids->cfg_mode == LNW_DMA_MEM_TO_MEM) {
633 /*SW HS only*/
634 cfg_hi.cfg_hi = 0;
635 } else {
636 cfg_hi.cfg_hi = 0;
637 if (midc->dma->pimr_mask) {
638 cfg_hi.cfgx.protctl = 0x0; /*default value*/
639 cfg_hi.cfgx.fifo_mode = 1;
Vinod Kouldb8196d2011-10-13 22:34:23 +0530640 if (mids->dma_slave.direction == DMA_MEM_TO_DEV) {
Vinod Koulb3c567e2010-07-21 13:28:10 +0530641 cfg_hi.cfgx.src_per = 0;
642 if (mids->device_instance == 0)
643 cfg_hi.cfgx.dst_per = 3;
644 if (mids->device_instance == 1)
645 cfg_hi.cfgx.dst_per = 1;
Vinod Kouldb8196d2011-10-13 22:34:23 +0530646 } else if (mids->dma_slave.direction == DMA_DEV_TO_MEM) {
Vinod Koulb3c567e2010-07-21 13:28:10 +0530647 if (mids->device_instance == 0)
648 cfg_hi.cfgx.src_per = 2;
649 if (mids->device_instance == 1)
650 cfg_hi.cfgx.src_per = 0;
651 cfg_hi.cfgx.dst_per = 0;
652 }
653 } else {
654 cfg_hi.cfgx.protctl = 0x1; /*default value*/
655 cfg_hi.cfgx.src_per = cfg_hi.cfgx.dst_per =
656 midc->ch_id - midc->dma->chan_base;
657 }
658 }
659
660 /*calculate CTL_HI*/
661 ctl_hi.ctlx.reser = 0;
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000662 ctl_hi.ctlx.done = 0;
Koul, Vinod20dd6392010-10-04 10:38:43 +0000663 width = mids->dma_slave.src_addr_width;
Vinod Koulb3c567e2010-07-21 13:28:10 +0530664
665 ctl_hi.ctlx.block_ts = get_block_ts(len, width, midc->dma->block_size);
666 pr_debug("MDMA:calc len %d for block size %d\n",
667 ctl_hi.ctlx.block_ts, midc->dma->block_size);
668 /*calculate CTL_LO*/
669 ctl_lo.ctl_lo = 0;
670 ctl_lo.ctlx.int_en = 1;
Koul, Vinod20dd6392010-10-04 10:38:43 +0000671 ctl_lo.ctlx.dst_msize = mids->dma_slave.src_maxburst;
672 ctl_lo.ctlx.src_msize = mids->dma_slave.dst_maxburst;
Vinod Koulb3c567e2010-07-21 13:28:10 +0530673
Feng Tang0be035f2010-12-02 17:14:30 +0800674 /*
675 * Here we need some translation from "enum dma_slave_buswidth"
676 * to the format for our dma controller
677 * standard intel_mid_dmac's format
678 * 1 Byte 0b000
679 * 2 Bytes 0b001
680 * 4 Bytes 0b010
681 */
682 ctl_lo.ctlx.dst_tr_width = mids->dma_slave.dst_addr_width / 2;
683 ctl_lo.ctlx.src_tr_width = mids->dma_slave.src_addr_width / 2;
684
Vinod Koulb3c567e2010-07-21 13:28:10 +0530685 if (mids->cfg_mode == LNW_DMA_MEM_TO_MEM) {
686 ctl_lo.ctlx.tt_fc = 0;
687 ctl_lo.ctlx.sinc = 0;
688 ctl_lo.ctlx.dinc = 0;
689 } else {
Vinod Kouldb8196d2011-10-13 22:34:23 +0530690 if (mids->dma_slave.direction == DMA_MEM_TO_DEV) {
Vinod Koulb3c567e2010-07-21 13:28:10 +0530691 ctl_lo.ctlx.sinc = 0;
692 ctl_lo.ctlx.dinc = 2;
693 ctl_lo.ctlx.tt_fc = 1;
Vinod Kouldb8196d2011-10-13 22:34:23 +0530694 } else if (mids->dma_slave.direction == DMA_DEV_TO_MEM) {
Vinod Koulb3c567e2010-07-21 13:28:10 +0530695 ctl_lo.ctlx.sinc = 2;
696 ctl_lo.ctlx.dinc = 0;
697 ctl_lo.ctlx.tt_fc = 2;
698 }
699 }
700
701 pr_debug("MDMA:Calc CTL LO %x, CTL HI %x, CFG LO %x, CFG HI %x\n",
702 ctl_lo.ctl_lo, ctl_hi.ctl_hi, cfg_lo.cfg_lo, cfg_hi.cfg_hi);
703
704 enable_dma_interrupt(midc);
705
706 desc = midc_desc_get(midc);
707 if (desc == NULL)
708 goto err_desc_get;
709 desc->sar = src;
710 desc->dar = dest ;
711 desc->len = len;
712 desc->cfg_hi = cfg_hi.cfg_hi;
713 desc->cfg_lo = cfg_lo.cfg_lo;
714 desc->ctl_lo = ctl_lo.ctl_lo;
715 desc->ctl_hi = ctl_hi.ctl_hi;
716 desc->width = width;
Koul, Vinod20dd6392010-10-04 10:38:43 +0000717 desc->dirn = mids->dma_slave.direction;
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000718 desc->lli_phys = 0;
719 desc->lli = NULL;
720 desc->lli_pool = NULL;
Vinod Koulb3c567e2010-07-21 13:28:10 +0530721 return &desc->txd;
722
723err_desc_get:
724 pr_err("ERR_MDMA: Failed to get desc\n");
725 midc_desc_put(midc, desc);
726 return NULL;
727}
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000728/**
729 * intel_mid_dma_prep_slave_sg - Prep slave sg txn
730 * @chan: chan for DMA transfer
731 * @sgl: scatter gather list
732 * @sg_len: length of sg txn
733 * @direction: DMA transfer dirtn
734 * @flags: DMA flags
735 *
736 * Prepares LLI based periphral transfer
737 */
738static struct dma_async_tx_descriptor *intel_mid_dma_prep_slave_sg(
739 struct dma_chan *chan, struct scatterlist *sgl,
Vinod Kouldb8196d2011-10-13 22:34:23 +0530740 unsigned int sg_len, enum dma_transfer_direction direction,
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000741 unsigned long flags)
742{
743 struct intel_mid_dma_chan *midc = NULL;
744 struct intel_mid_dma_slave *mids = NULL;
745 struct intel_mid_dma_desc *desc = NULL;
746 struct dma_async_tx_descriptor *txd = NULL;
747 union intel_mid_dma_ctl_lo ctl_lo;
748
749 pr_debug("MDMA: Prep for slave SG\n");
750
751 if (!sg_len) {
752 pr_err("MDMA: Invalid SG length\n");
753 return NULL;
754 }
755 midc = to_intel_mid_dma_chan(chan);
756 BUG_ON(!midc);
757
Koul, Vinod20dd6392010-10-04 10:38:43 +0000758 mids = midc->mid_slave;
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000759 BUG_ON(!mids);
760
761 if (!midc->dma->pimr_mask) {
Feng Tang0be035f2010-12-02 17:14:30 +0800762 /* We can still handle sg list with only one item */
763 if (sg_len == 1) {
764 txd = intel_mid_dma_prep_memcpy(chan,
765 mids->dma_slave.dst_addr,
766 mids->dma_slave.src_addr,
767 sgl->length,
768 flags);
769 return txd;
770 } else {
771 pr_warn("MDMA: SG list is not supported by this controller\n");
772 return NULL;
773 }
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000774 }
775
776 pr_debug("MDMA: SG Length = %d, direction = %d, Flags = %#lx\n",
777 sg_len, direction, flags);
778
779 txd = intel_mid_dma_prep_memcpy(chan, 0, 0, sgl->length, flags);
780 if (NULL == txd) {
781 pr_err("MDMA: Prep memcpy failed\n");
782 return NULL;
783 }
Feng Tang0be035f2010-12-02 17:14:30 +0800784
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000785 desc = to_intel_mid_dma_desc(txd);
786 desc->dirn = direction;
787 ctl_lo.ctl_lo = desc->ctl_lo;
788 ctl_lo.ctlx.llp_dst_en = 1;
789 ctl_lo.ctlx.llp_src_en = 1;
790 desc->ctl_lo = ctl_lo.ctl_lo;
791 desc->lli_length = sg_len;
792 desc->current_lli = 0;
793 /* DMA coherent memory pool for LLI descriptors*/
794 desc->lli_pool = pci_pool_create("intel_mid_dma_lli_pool",
795 midc->dma->pdev,
796 (sizeof(struct intel_mid_dma_lli)*sg_len),
797 32, 0);
798 if (NULL == desc->lli_pool) {
799 pr_err("MID_DMA:LLI pool create failed\n");
800 return NULL;
801 }
802
803 desc->lli = pci_pool_alloc(desc->lli_pool, GFP_KERNEL, &desc->lli_phys);
804 if (!desc->lli) {
805 pr_err("MID_DMA: LLI alloc failed\n");
806 pci_pool_destroy(desc->lli_pool);
807 return NULL;
808 }
809
810 midc_lli_fill_sg(midc, desc, sgl, sg_len, flags);
811 if (flags & DMA_PREP_INTERRUPT) {
812 iowrite32(UNMASK_INTR_REG(midc->ch_id),
813 midc->dma_base + MASK_BLOCK);
814 pr_debug("MDMA:Enabled Block interrupt\n");
815 }
816 return &desc->txd;
817}
Vinod Koulb3c567e2010-07-21 13:28:10 +0530818
819/**
820 * intel_mid_dma_free_chan_resources - Frees dma resources
821 * @chan: chan requiring attention
822 *
823 * Frees the allocated resources on this DMA chan
824 */
825static void intel_mid_dma_free_chan_resources(struct dma_chan *chan)
826{
827 struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan);
828 struct middma_device *mid = to_middma_device(chan->device);
829 struct intel_mid_dma_desc *desc, *_desc;
830
Koul, Vinod53a61ba2010-10-04 10:42:40 +0000831 if (true == midc->busy) {
Vinod Koulb3c567e2010-07-21 13:28:10 +0530832 /*trying to free ch in use!!!!!*/
833 pr_err("ERR_MDMA: trying to free ch in use\n");
834 }
Koul, Vinod53a61ba2010-10-04 10:42:40 +0000835 pm_runtime_put(&mid->pdev->dev);
Vinod Koulb3c567e2010-07-21 13:28:10 +0530836 spin_lock_bh(&midc->lock);
837 midc->descs_allocated = 0;
838 list_for_each_entry_safe(desc, _desc, &midc->active_list, desc_node) {
839 list_del(&desc->desc_node);
840 pci_pool_free(mid->dma_pool, desc, desc->txd.phys);
841 }
842 list_for_each_entry_safe(desc, _desc, &midc->free_list, desc_node) {
843 list_del(&desc->desc_node);
844 pci_pool_free(mid->dma_pool, desc, desc->txd.phys);
845 }
846 list_for_each_entry_safe(desc, _desc, &midc->queue, desc_node) {
847 list_del(&desc->desc_node);
848 pci_pool_free(mid->dma_pool, desc, desc->txd.phys);
849 }
850 spin_unlock_bh(&midc->lock);
851 midc->in_use = false;
Koul, Vinod53a61ba2010-10-04 10:42:40 +0000852 midc->busy = false;
Vinod Koulb3c567e2010-07-21 13:28:10 +0530853 /* Disable CH interrupts */
854 iowrite32(MASK_INTR_REG(midc->ch_id), mid->dma_base + MASK_BLOCK);
855 iowrite32(MASK_INTR_REG(midc->ch_id), mid->dma_base + MASK_ERR);
856}
857
858/**
859 * intel_mid_dma_alloc_chan_resources - Allocate dma resources
860 * @chan: chan requiring attention
861 *
862 * Allocates DMA resources on this chan
863 * Return the descriptors allocated
864 */
865static int intel_mid_dma_alloc_chan_resources(struct dma_chan *chan)
866{
867 struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan);
868 struct middma_device *mid = to_middma_device(chan->device);
869 struct intel_mid_dma_desc *desc;
870 dma_addr_t phys;
871 int i = 0;
872
Koul, Vinod53a61ba2010-10-04 10:42:40 +0000873 pm_runtime_get_sync(&mid->pdev->dev);
874
875 if (mid->state == SUSPENDED) {
Kristen Carlson Accardi87307902011-12-16 11:01:40 +0200876 if (dma_resume(&mid->pdev->dev)) {
Koul, Vinod53a61ba2010-10-04 10:42:40 +0000877 pr_err("ERR_MDMA: resume failed");
878 return -EFAULT;
879 }
880 }
Vinod Koulb3c567e2010-07-21 13:28:10 +0530881
882 /* ASSERT: channel is idle */
883 if (test_ch_en(mid->dma_base, midc->ch_id)) {
884 /*ch is not idle*/
885 pr_err("ERR_MDMA: ch not idle\n");
Koul, Vinod53a61ba2010-10-04 10:42:40 +0000886 pm_runtime_put(&mid->pdev->dev);
Vinod Koulb3c567e2010-07-21 13:28:10 +0530887 return -EIO;
888 }
889 midc->completed = chan->cookie = 1;
890
891 spin_lock_bh(&midc->lock);
892 while (midc->descs_allocated < DESCS_PER_CHANNEL) {
893 spin_unlock_bh(&midc->lock);
894 desc = pci_pool_alloc(mid->dma_pool, GFP_KERNEL, &phys);
895 if (!desc) {
896 pr_err("ERR_MDMA: desc failed\n");
Koul, Vinod53a61ba2010-10-04 10:42:40 +0000897 pm_runtime_put(&mid->pdev->dev);
Vinod Koulb3c567e2010-07-21 13:28:10 +0530898 return -ENOMEM;
899 /*check*/
900 }
901 dma_async_tx_descriptor_init(&desc->txd, chan);
902 desc->txd.tx_submit = intel_mid_dma_tx_submit;
903 desc->txd.flags = DMA_CTRL_ACK;
904 desc->txd.phys = phys;
905 spin_lock_bh(&midc->lock);
906 i = ++midc->descs_allocated;
907 list_add_tail(&desc->desc_node, &midc->free_list);
908 }
909 spin_unlock_bh(&midc->lock);
Koul, Vinod53a61ba2010-10-04 10:42:40 +0000910 midc->in_use = true;
911 midc->busy = false;
Vinod Koulb3c567e2010-07-21 13:28:10 +0530912 pr_debug("MID_DMA: Desc alloc done ret: %d desc\n", i);
913 return i;
914}
915
916/**
917 * midc_handle_error - Handle DMA txn error
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300918 * @mid: controller where error occurred
919 * @midc: chan where error occurred
Vinod Koulb3c567e2010-07-21 13:28:10 +0530920 *
921 * Scan the descriptor for error
922 */
923static void midc_handle_error(struct middma_device *mid,
924 struct intel_mid_dma_chan *midc)
925{
926 midc_scan_descriptors(mid, midc);
927}
928
929/**
930 * dma_tasklet - DMA interrupt tasklet
931 * @data: tasklet arg (the controller structure)
932 *
933 * Scan the controller for interrupts for completion/error
934 * Clear the interrupt and call for handling completion/error
935 */
936static void dma_tasklet(unsigned long data)
937{
938 struct middma_device *mid = NULL;
939 struct intel_mid_dma_chan *midc = NULL;
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000940 u32 status, raw_tfr, raw_block;
Vinod Koulb3c567e2010-07-21 13:28:10 +0530941 int i;
942
943 mid = (struct middma_device *)data;
944 if (mid == NULL) {
945 pr_err("ERR_MDMA: tasklet Null param\n");
946 return;
947 }
948 pr_debug("MDMA: in tasklet for device %x\n", mid->pci_id);
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000949 raw_tfr = ioread32(mid->dma_base + RAW_TFR);
950 raw_block = ioread32(mid->dma_base + RAW_BLOCK);
951 status = raw_tfr | raw_block;
Vinod Koulb3c567e2010-07-21 13:28:10 +0530952 status &= mid->intr_mask;
953 while (status) {
954 /*txn interrupt*/
955 i = get_ch_index(&status, mid->chan_base);
956 if (i < 0) {
957 pr_err("ERR_MDMA:Invalid ch index %x\n", i);
958 return;
959 }
960 midc = &mid->ch[i];
961 if (midc == NULL) {
962 pr_err("ERR_MDMA:Null param midc\n");
963 return;
964 }
965 pr_debug("MDMA:Tx complete interrupt %x, Ch No %d Index %d\n",
966 status, midc->ch_id, i);
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000967 midc->raw_tfr = raw_tfr;
968 midc->raw_block = raw_block;
969 spin_lock_bh(&midc->lock);
Vinod Koulb3c567e2010-07-21 13:28:10 +0530970 /*clearing this interrupts first*/
971 iowrite32((1 << midc->ch_id), mid->dma_base + CLEAR_TFR);
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000972 if (raw_block) {
973 iowrite32((1 << midc->ch_id),
974 mid->dma_base + CLEAR_BLOCK);
975 }
Vinod Koulb3c567e2010-07-21 13:28:10 +0530976 midc_scan_descriptors(mid, midc);
977 pr_debug("MDMA:Scan of desc... complete, unmasking\n");
978 iowrite32(UNMASK_INTR_REG(midc->ch_id),
979 mid->dma_base + MASK_TFR);
Ramesh Babu K V576e3c32010-10-04 10:37:53 +0000980 if (raw_block) {
981 iowrite32(UNMASK_INTR_REG(midc->ch_id),
982 mid->dma_base + MASK_BLOCK);
983 }
Vinod Koulb3c567e2010-07-21 13:28:10 +0530984 spin_unlock_bh(&midc->lock);
985 }
986
987 status = ioread32(mid->dma_base + RAW_ERR);
988 status &= mid->intr_mask;
989 while (status) {
990 /*err interrupt*/
991 i = get_ch_index(&status, mid->chan_base);
992 if (i < 0) {
993 pr_err("ERR_MDMA:Invalid ch index %x\n", i);
994 return;
995 }
996 midc = &mid->ch[i];
997 if (midc == NULL) {
998 pr_err("ERR_MDMA:Null param midc\n");
999 return;
1000 }
1001 pr_debug("MDMA:Tx complete interrupt %x, Ch No %d Index %d\n",
1002 status, midc->ch_id, i);
1003
1004 iowrite32((1 << midc->ch_id), mid->dma_base + CLEAR_ERR);
1005 spin_lock_bh(&midc->lock);
1006 midc_handle_error(mid, midc);
1007 iowrite32(UNMASK_INTR_REG(midc->ch_id),
1008 mid->dma_base + MASK_ERR);
1009 spin_unlock_bh(&midc->lock);
1010 }
1011 pr_debug("MDMA:Exiting takslet...\n");
1012 return;
1013}
1014
1015static void dma_tasklet1(unsigned long data)
1016{
1017 pr_debug("MDMA:in takslet1...\n");
1018 return dma_tasklet(data);
1019}
1020
1021static void dma_tasklet2(unsigned long data)
1022{
1023 pr_debug("MDMA:in takslet2...\n");
1024 return dma_tasklet(data);
1025}
1026
1027/**
1028 * intel_mid_dma_interrupt - DMA ISR
1029 * @irq: IRQ where interrupt occurred
1030 * @data: ISR cllback data (the controller structure)
1031 *
1032 * See if this is our interrupt if so then schedule the tasklet
1033 * otherwise ignore
1034 */
1035static irqreturn_t intel_mid_dma_interrupt(int irq, void *data)
1036{
1037 struct middma_device *mid = data;
Yong Wangb306df52010-10-04 10:37:02 +00001038 u32 tfr_status, err_status;
Vinod Koulb3c567e2010-07-21 13:28:10 +05301039 int call_tasklet = 0;
1040
Yong Wangb306df52010-10-04 10:37:02 +00001041 tfr_status = ioread32(mid->dma_base + RAW_TFR);
1042 err_status = ioread32(mid->dma_base + RAW_ERR);
1043 if (!tfr_status && !err_status)
1044 return IRQ_NONE;
1045
Vinod Koulb3c567e2010-07-21 13:28:10 +05301046 /*DMA Interrupt*/
1047 pr_debug("MDMA:Got an interrupt on irq %d\n", irq);
Yong Wangb306df52010-10-04 10:37:02 +00001048 pr_debug("MDMA: Status %x, Mask %x\n", tfr_status, mid->intr_mask);
1049 tfr_status &= mid->intr_mask;
1050 if (tfr_status) {
Vinod Koulb3c567e2010-07-21 13:28:10 +05301051 /*need to disable intr*/
Ramesh Babu K V576e3c32010-10-04 10:37:53 +00001052 iowrite32((tfr_status << INT_MASK_WE), mid->dma_base + MASK_TFR);
1053 iowrite32((tfr_status << INT_MASK_WE), mid->dma_base + MASK_BLOCK);
Yong Wangb306df52010-10-04 10:37:02 +00001054 pr_debug("MDMA: Calling tasklet %x\n", tfr_status);
Vinod Koulb3c567e2010-07-21 13:28:10 +05301055 call_tasklet = 1;
1056 }
Yong Wangb306df52010-10-04 10:37:02 +00001057 err_status &= mid->intr_mask;
1058 if (err_status) {
1059 iowrite32(MASK_INTR_REG(err_status), mid->dma_base + MASK_ERR);
Vinod Koulb3c567e2010-07-21 13:28:10 +05301060 call_tasklet = 1;
1061 }
1062 if (call_tasklet)
1063 tasklet_schedule(&mid->tasklet);
1064
1065 return IRQ_HANDLED;
1066}
1067
1068static irqreturn_t intel_mid_dma_interrupt1(int irq, void *data)
1069{
1070 return intel_mid_dma_interrupt(irq, data);
1071}
1072
1073static irqreturn_t intel_mid_dma_interrupt2(int irq, void *data)
1074{
1075 return intel_mid_dma_interrupt(irq, data);
1076}
1077
1078/**
1079 * mid_setup_dma - Setup the DMA controller
1080 * @pdev: Controller PCI device structure
1081 *
Uwe Kleine-Königb5950762010-11-01 15:38:34 -04001082 * Initialize the DMA controller, channels, registers with DMA engine,
1083 * ISR. Initialize DMA controller channels.
Vinod Koulb3c567e2010-07-21 13:28:10 +05301084 */
1085static int mid_setup_dma(struct pci_dev *pdev)
1086{
1087 struct middma_device *dma = pci_get_drvdata(pdev);
1088 int err, i;
Vinod Koulb3c567e2010-07-21 13:28:10 +05301089
1090 /* DMA coherent memory pool for DMA descriptor allocations */
1091 dma->dma_pool = pci_pool_create("intel_mid_dma_desc_pool", pdev,
1092 sizeof(struct intel_mid_dma_desc),
1093 32, 0);
1094 if (NULL == dma->dma_pool) {
1095 pr_err("ERR_MDMA:pci_pool_create failed\n");
1096 err = -ENOMEM;
Vinod Koulb3c567e2010-07-21 13:28:10 +05301097 goto err_dma_pool;
1098 }
1099
1100 INIT_LIST_HEAD(&dma->common.channels);
1101 dma->pci_id = pdev->device;
1102 if (dma->pimr_mask) {
1103 dma->mask_reg = ioremap(LNW_PERIPHRAL_MASK_BASE,
1104 LNW_PERIPHRAL_MASK_SIZE);
1105 if (dma->mask_reg == NULL) {
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001106 pr_err("ERR_MDMA:Can't map periphral intr space !!\n");
Adrian Hunter2a0ff7a2011-12-16 11:01:39 +02001107 err = -ENOMEM;
1108 goto err_ioremap;
Vinod Koulb3c567e2010-07-21 13:28:10 +05301109 }
1110 } else
1111 dma->mask_reg = NULL;
1112
1113 pr_debug("MDMA:Adding %d channel for this controller\n", dma->max_chan);
1114 /*init CH structures*/
1115 dma->intr_mask = 0;
Koul, Vinod53a61ba2010-10-04 10:42:40 +00001116 dma->state = RUNNING;
Vinod Koulb3c567e2010-07-21 13:28:10 +05301117 for (i = 0; i < dma->max_chan; i++) {
1118 struct intel_mid_dma_chan *midch = &dma->ch[i];
1119
1120 midch->chan.device = &dma->common;
1121 midch->chan.cookie = 1;
Vinod Koulb3c567e2010-07-21 13:28:10 +05301122 midch->ch_id = dma->chan_base + i;
1123 pr_debug("MDMA:Init CH %d, ID %d\n", i, midch->ch_id);
1124
1125 midch->dma_base = dma->dma_base;
1126 midch->ch_regs = dma->dma_base + DMA_CH_SIZE * midch->ch_id;
1127 midch->dma = dma;
1128 dma->intr_mask |= 1 << (dma->chan_base + i);
1129 spin_lock_init(&midch->lock);
1130
1131 INIT_LIST_HEAD(&midch->active_list);
1132 INIT_LIST_HEAD(&midch->queue);
1133 INIT_LIST_HEAD(&midch->free_list);
1134 /*mask interrupts*/
1135 iowrite32(MASK_INTR_REG(midch->ch_id),
1136 dma->dma_base + MASK_BLOCK);
1137 iowrite32(MASK_INTR_REG(midch->ch_id),
1138 dma->dma_base + MASK_SRC_TRAN);
1139 iowrite32(MASK_INTR_REG(midch->ch_id),
1140 dma->dma_base + MASK_DST_TRAN);
1141 iowrite32(MASK_INTR_REG(midch->ch_id),
1142 dma->dma_base + MASK_ERR);
1143 iowrite32(MASK_INTR_REG(midch->ch_id),
1144 dma->dma_base + MASK_TFR);
1145
1146 disable_dma_interrupt(midch);
1147 list_add_tail(&midch->chan.device_node, &dma->common.channels);
1148 }
1149 pr_debug("MDMA: Calc Mask as %x for this controller\n", dma->intr_mask);
1150
1151 /*init dma structure*/
1152 dma_cap_zero(dma->common.cap_mask);
1153 dma_cap_set(DMA_MEMCPY, dma->common.cap_mask);
1154 dma_cap_set(DMA_SLAVE, dma->common.cap_mask);
1155 dma_cap_set(DMA_PRIVATE, dma->common.cap_mask);
1156 dma->common.dev = &pdev->dev;
Vinod Koulb3c567e2010-07-21 13:28:10 +05301157
1158 dma->common.device_alloc_chan_resources =
1159 intel_mid_dma_alloc_chan_resources;
1160 dma->common.device_free_chan_resources =
1161 intel_mid_dma_free_chan_resources;
1162
1163 dma->common.device_tx_status = intel_mid_dma_tx_status;
1164 dma->common.device_prep_dma_memcpy = intel_mid_dma_prep_memcpy;
1165 dma->common.device_issue_pending = intel_mid_dma_issue_pending;
1166 dma->common.device_prep_slave_sg = intel_mid_dma_prep_slave_sg;
1167 dma->common.device_control = intel_mid_dma_device_control;
1168
1169 /*enable dma cntrl*/
1170 iowrite32(REG_BIT0, dma->dma_base + DMA_CFG);
1171
1172 /*register irq */
1173 if (dma->pimr_mask) {
Vinod Koulb3c567e2010-07-21 13:28:10 +05301174 pr_debug("MDMA:Requesting irq shared for DMAC1\n");
1175 err = request_irq(pdev->irq, intel_mid_dma_interrupt1,
1176 IRQF_SHARED, "INTEL_MID_DMAC1", dma);
1177 if (0 != err)
1178 goto err_irq;
1179 } else {
1180 dma->intr_mask = 0x03;
Vinod Koulb3c567e2010-07-21 13:28:10 +05301181 pr_debug("MDMA:Requesting irq for DMAC2\n");
1182 err = request_irq(pdev->irq, intel_mid_dma_interrupt2,
Yong Wang03b96dc2010-10-04 10:37:27 +00001183 IRQF_SHARED, "INTEL_MID_DMAC2", dma);
Vinod Koulb3c567e2010-07-21 13:28:10 +05301184 if (0 != err)
1185 goto err_irq;
1186 }
1187 /*register device w/ engine*/
1188 err = dma_async_device_register(&dma->common);
1189 if (0 != err) {
1190 pr_err("ERR_MDMA:device_register failed: %d\n", err);
1191 goto err_engine;
1192 }
1193 if (dma->pimr_mask) {
1194 pr_debug("setting up tasklet1 for DMAC1\n");
1195 tasklet_init(&dma->tasklet, dma_tasklet1, (unsigned long)dma);
1196 } else {
1197 pr_debug("setting up tasklet2 for DMAC2\n");
1198 tasklet_init(&dma->tasklet, dma_tasklet2, (unsigned long)dma);
1199 }
1200 return 0;
1201
1202err_engine:
1203 free_irq(pdev->irq, dma);
1204err_irq:
Adrian Hunter2a0ff7a2011-12-16 11:01:39 +02001205 if (dma->mask_reg)
1206 iounmap(dma->mask_reg);
1207err_ioremap:
Vinod Koulb3c567e2010-07-21 13:28:10 +05301208 pci_pool_destroy(dma->dma_pool);
Vinod Koulb3c567e2010-07-21 13:28:10 +05301209err_dma_pool:
1210 pr_err("ERR_MDMA:setup_dma failed: %d\n", err);
1211 return err;
1212
1213}
1214
1215/**
1216 * middma_shutdown - Shutdown the DMA controller
1217 * @pdev: Controller PCI device structure
1218 *
1219 * Called by remove
1220 * Unregister DMa controller, clear all structures and free interrupt
1221 */
1222static void middma_shutdown(struct pci_dev *pdev)
1223{
1224 struct middma_device *device = pci_get_drvdata(pdev);
1225
1226 dma_async_device_unregister(&device->common);
1227 pci_pool_destroy(device->dma_pool);
1228 if (device->mask_reg)
1229 iounmap(device->mask_reg);
1230 if (device->dma_base)
1231 iounmap(device->dma_base);
1232 free_irq(pdev->irq, device);
1233 return;
1234}
1235
1236/**
1237 * intel_mid_dma_probe - PCI Probe
1238 * @pdev: Controller PCI device structure
1239 * @id: pci device id structure
1240 *
Uwe Kleine-Königb5950762010-11-01 15:38:34 -04001241 * Initialize the PCI device, map BARs, query driver data.
Vinod Koulb3c567e2010-07-21 13:28:10 +05301242 * Call setup_dma to complete contoller and chan initilzation
1243 */
1244static int __devinit intel_mid_dma_probe(struct pci_dev *pdev,
1245 const struct pci_device_id *id)
1246{
1247 struct middma_device *device;
1248 u32 base_addr, bar_size;
1249 struct intel_mid_dma_probe_info *info;
1250 int err;
1251
1252 pr_debug("MDMA: probe for %x\n", pdev->device);
1253 info = (void *)id->driver_data;
1254 pr_debug("MDMA: CH %d, base %d, block len %d, Periphral mask %x\n",
1255 info->max_chan, info->ch_base,
1256 info->block_size, info->pimr_mask);
1257
1258 err = pci_enable_device(pdev);
1259 if (err)
1260 goto err_enable_device;
1261
1262 err = pci_request_regions(pdev, "intel_mid_dmac");
1263 if (err)
1264 goto err_request_regions;
1265
1266 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1267 if (err)
1268 goto err_set_dma_mask;
1269
1270 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1271 if (err)
1272 goto err_set_dma_mask;
1273
1274 device = kzalloc(sizeof(*device), GFP_KERNEL);
1275 if (!device) {
1276 pr_err("ERR_MDMA:kzalloc failed probe\n");
1277 err = -ENOMEM;
1278 goto err_kzalloc;
1279 }
1280 device->pdev = pci_dev_get(pdev);
1281
1282 base_addr = pci_resource_start(pdev, 0);
1283 bar_size = pci_resource_len(pdev, 0);
1284 device->dma_base = ioremap_nocache(base_addr, DMA_REG_SIZE);
1285 if (!device->dma_base) {
1286 pr_err("ERR_MDMA:ioremap failed\n");
1287 err = -ENOMEM;
1288 goto err_ioremap;
1289 }
1290 pci_set_drvdata(pdev, device);
1291 pci_set_master(pdev);
1292 device->max_chan = info->max_chan;
1293 device->chan_base = info->ch_base;
1294 device->block_size = info->block_size;
1295 device->pimr_mask = info->pimr_mask;
1296
1297 err = mid_setup_dma(pdev);
1298 if (err)
1299 goto err_dma;
1300
Kristen Carlson Accardie2142df2011-03-31 11:02:43 -07001301 pm_runtime_put_noidle(&pdev->dev);
Koul, Vinod53a61ba2010-10-04 10:42:40 +00001302 pm_runtime_allow(&pdev->dev);
Vinod Koulb3c567e2010-07-21 13:28:10 +05301303 return 0;
1304
1305err_dma:
1306 iounmap(device->dma_base);
1307err_ioremap:
1308 pci_dev_put(pdev);
1309 kfree(device);
1310err_kzalloc:
1311err_set_dma_mask:
1312 pci_release_regions(pdev);
1313 pci_disable_device(pdev);
1314err_request_regions:
1315err_enable_device:
1316 pr_err("ERR_MDMA:Probe failed %d\n", err);
1317 return err;
1318}
1319
1320/**
1321 * intel_mid_dma_remove - PCI remove
1322 * @pdev: Controller PCI device structure
1323 *
1324 * Free up all resources and data
1325 * Call shutdown_dma to complete contoller and chan cleanup
1326 */
1327static void __devexit intel_mid_dma_remove(struct pci_dev *pdev)
1328{
1329 struct middma_device *device = pci_get_drvdata(pdev);
Kristen Carlson Accardie2142df2011-03-31 11:02:43 -07001330
1331 pm_runtime_get_noresume(&pdev->dev);
1332 pm_runtime_forbid(&pdev->dev);
Vinod Koulb3c567e2010-07-21 13:28:10 +05301333 middma_shutdown(pdev);
1334 pci_dev_put(pdev);
1335 kfree(device);
1336 pci_release_regions(pdev);
1337 pci_disable_device(pdev);
1338}
1339
Koul, Vinod53a61ba2010-10-04 10:42:40 +00001340/* Power Management */
1341/*
1342* dma_suspend - PCI suspend function
1343*
1344* @pci: PCI device structure
1345* @state: PM message
1346*
1347* This function is called by OS when a power event occurs
1348*/
Kristen Carlson Accardi87307902011-12-16 11:01:40 +02001349static int dma_suspend(struct device *dev)
Koul, Vinod53a61ba2010-10-04 10:42:40 +00001350{
Kristen Carlson Accardi87307902011-12-16 11:01:40 +02001351 struct pci_dev *pci = to_pci_dev(dev);
Koul, Vinod53a61ba2010-10-04 10:42:40 +00001352 int i;
1353 struct middma_device *device = pci_get_drvdata(pci);
1354 pr_debug("MDMA: dma_suspend called\n");
1355
1356 for (i = 0; i < device->max_chan; i++) {
1357 if (device->ch[i].in_use)
1358 return -EAGAIN;
1359 }
Vinod Koul4598fc22011-10-10 12:33:59 +05301360 dmac1_mask_periphral_intr(device);
Koul, Vinod53a61ba2010-10-04 10:42:40 +00001361 device->state = SUSPENDED;
Koul, Vinod53a61ba2010-10-04 10:42:40 +00001362 pci_save_state(pci);
1363 pci_disable_device(pci);
1364 pci_set_power_state(pci, PCI_D3hot);
1365 return 0;
1366}
1367
1368/**
1369* dma_resume - PCI resume function
1370*
1371* @pci: PCI device structure
1372*
1373* This function is called by OS when a power event occurs
1374*/
Kristen Carlson Accardi87307902011-12-16 11:01:40 +02001375int dma_resume(struct device *dev)
Koul, Vinod53a61ba2010-10-04 10:42:40 +00001376{
Kristen Carlson Accardi87307902011-12-16 11:01:40 +02001377 struct pci_dev *pci = to_pci_dev(dev);
Koul, Vinod53a61ba2010-10-04 10:42:40 +00001378 int ret;
1379 struct middma_device *device = pci_get_drvdata(pci);
1380
1381 pr_debug("MDMA: dma_resume called\n");
1382 pci_set_power_state(pci, PCI_D0);
1383 pci_restore_state(pci);
1384 ret = pci_enable_device(pci);
1385 if (ret) {
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001386 pr_err("MDMA: device can't be enabled for %x\n", pci->device);
Koul, Vinod53a61ba2010-10-04 10:42:40 +00001387 return ret;
1388 }
1389 device->state = RUNNING;
1390 iowrite32(REG_BIT0, device->dma_base + DMA_CFG);
Koul, Vinod53a61ba2010-10-04 10:42:40 +00001391 return 0;
1392}
1393
1394static int dma_runtime_suspend(struct device *dev)
1395{
1396 struct pci_dev *pci_dev = to_pci_dev(dev);
Kristen Carlson Accardie2142df2011-03-31 11:02:43 -07001397 struct middma_device *device = pci_get_drvdata(pci_dev);
1398
1399 device->state = SUSPENDED;
1400 return 0;
Koul, Vinod53a61ba2010-10-04 10:42:40 +00001401}
1402
1403static int dma_runtime_resume(struct device *dev)
1404{
1405 struct pci_dev *pci_dev = to_pci_dev(dev);
Kristen Carlson Accardie2142df2011-03-31 11:02:43 -07001406 struct middma_device *device = pci_get_drvdata(pci_dev);
1407
1408 device->state = RUNNING;
1409 iowrite32(REG_BIT0, device->dma_base + DMA_CFG);
1410 return 0;
Koul, Vinod53a61ba2010-10-04 10:42:40 +00001411}
1412
1413static int dma_runtime_idle(struct device *dev)
1414{
1415 struct pci_dev *pdev = to_pci_dev(dev);
1416 struct middma_device *device = pci_get_drvdata(pdev);
1417 int i;
1418
1419 for (i = 0; i < device->max_chan; i++) {
1420 if (device->ch[i].in_use)
1421 return -EAGAIN;
1422 }
1423
1424 return pm_schedule_suspend(dev, 0);
1425}
1426
Vinod Koulb3c567e2010-07-21 13:28:10 +05301427/******************************************************************************
1428* PCI stuff
1429*/
1430static struct pci_device_id intel_mid_dma_ids[] = {
1431 { PCI_VDEVICE(INTEL, INTEL_MID_DMAC1_ID), INFO(2, 6, 4095, 0x200020)},
1432 { PCI_VDEVICE(INTEL, INTEL_MID_DMAC2_ID), INFO(2, 0, 2047, 0)},
1433 { PCI_VDEVICE(INTEL, INTEL_MID_GP_DMAC2_ID), INFO(2, 0, 2047, 0)},
1434 { PCI_VDEVICE(INTEL, INTEL_MFLD_DMAC1_ID), INFO(4, 0, 4095, 0x400040)},
1435 { 0, }
1436};
1437MODULE_DEVICE_TABLE(pci, intel_mid_dma_ids);
1438
Koul, Vinod53a61ba2010-10-04 10:42:40 +00001439static const struct dev_pm_ops intel_mid_dma_pm = {
1440 .runtime_suspend = dma_runtime_suspend,
1441 .runtime_resume = dma_runtime_resume,
1442 .runtime_idle = dma_runtime_idle,
Kristen Carlson Accardi87307902011-12-16 11:01:40 +02001443 .suspend = dma_suspend,
1444 .resume = dma_resume,
Koul, Vinod53a61ba2010-10-04 10:42:40 +00001445};
1446
Dan Williamscf2f9c52010-12-04 14:53:32 -08001447static struct pci_driver intel_mid_dma_pci_driver = {
Vinod Koulb3c567e2010-07-21 13:28:10 +05301448 .name = "Intel MID DMA",
1449 .id_table = intel_mid_dma_ids,
1450 .probe = intel_mid_dma_probe,
1451 .remove = __devexit_p(intel_mid_dma_remove),
Koul, Vinod53a61ba2010-10-04 10:42:40 +00001452#ifdef CONFIG_PM
Koul, Vinod53a61ba2010-10-04 10:42:40 +00001453 .driver = {
1454 .pm = &intel_mid_dma_pm,
1455 },
1456#endif
Vinod Koulb3c567e2010-07-21 13:28:10 +05301457};
1458
1459static int __init intel_mid_dma_init(void)
1460{
1461 pr_debug("INFO_MDMA: LNW DMA Driver Version %s\n",
1462 INTEL_MID_DMA_DRIVER_VERSION);
Dan Williamscf2f9c52010-12-04 14:53:32 -08001463 return pci_register_driver(&intel_mid_dma_pci_driver);
Vinod Koulb3c567e2010-07-21 13:28:10 +05301464}
1465fs_initcall(intel_mid_dma_init);
1466
1467static void __exit intel_mid_dma_exit(void)
1468{
Dan Williamscf2f9c52010-12-04 14:53:32 -08001469 pci_unregister_driver(&intel_mid_dma_pci_driver);
Vinod Koulb3c567e2010-07-21 13:28:10 +05301470}
1471module_exit(intel_mid_dma_exit);
1472
1473MODULE_AUTHOR("Vinod Koul <vinod.koul@intel.com>");
1474MODULE_DESCRIPTION("Intel (R) MID DMAC Driver");
1475MODULE_LICENSE("GPL v2");
1476MODULE_VERSION(INTEL_MID_DMA_DRIVER_VERSION);