| Andrew Victor | c53c9cf | 2007-05-11 21:01:28 +0100 | [diff] [blame] | 1 | /* |
| 2 | * include/asm-arm/arch-ks8695/regs-switch.h |
| 3 | * |
| 4 | * Copyright (C) 2006 Andrew Victor |
| 5 | * |
| 6 | * KS8695 - Switch Registers and bit definitions. |
| 7 | * |
| 8 | * This file is licensed under the terms of the GNU General Public |
| 9 | * License version 2. This program is licensed "as is" without any |
| 10 | * warranty of any kind, whether express or implied. |
| 11 | */ |
| 12 | |
| 13 | #ifndef KS8695_SWITCH_H |
| 14 | #define KS8695_SWITCH_H |
| 15 | |
| 16 | #define KS8695_SWITCH_OFFSET (0xF0000 + 0xe800) |
| 17 | #define KS8695_SWITCH_VA (KS8695_IO_VA + KS8695_SWITCH_OFFSET) |
| 18 | #define KS8695_SWITCH_PA (KS8695_IO_PA + KS8695_SWITCH_OFFSET) |
| 19 | |
| 20 | |
| 21 | /* |
| 22 | * Switch registers |
| 23 | */ |
| 24 | #define KS8695_SEC0 (0x00) /* Switch Engine Control 0 */ |
| 25 | #define KS8695_SEC1 (0x04) /* Switch Engine Control 1 */ |
| 26 | #define KS8695_SEC2 (0x08) /* Switch Engine Control 2 */ |
| 27 | |
| 28 | #define KS8695_P(x)_C(z) (0xc0 + (((x)-1)*3 + ((z)-1))*4) /* Port Configuration Registers */ |
| 29 | |
| 30 | #define KS8695_SEP12AN (0x48) /* Port 1 & 2 Auto-Negotiation */ |
| 31 | #define KS8695_SEP34AN (0x4c) /* Port 3 & 4 Auto-Negotiation */ |
| 32 | #define KS8695_SEIAC (0x50) /* Indirect Access Control */ |
| 33 | #define KS8695_SEIADH2 (0x54) /* Indirect Access Data High 2 */ |
| 34 | #define KS8695_SEIADH1 (0x58) /* Indirect Access Data High 1 */ |
| 35 | #define KS8695_SEIADL (0x5c) /* Indirect Access Data Low */ |
| 36 | #define KS8695_SEAFC (0x60) /* Advance Feature Control */ |
| 37 | #define KS8695_SEDSCPH (0x64) /* TOS Priority High */ |
| 38 | #define KS8695_SEDSCPL (0x68) /* TOS Priority Low */ |
| 39 | #define KS8695_SEMAH (0x6c) /* Switch Engine MAC Address High */ |
| 40 | #define KS8695_SEMAL (0x70) /* Switch Engine MAC Address Low */ |
| 41 | #define KS8695_LPPM12 (0x74) /* Port 1 & 2 PHY Power Management */ |
| 42 | #define KS8695_LPPM34 (0x78) /* Port 3 & 4 PHY Power Management */ |
| 43 | |
| 44 | |
| 45 | /* Switch Engine Control 0 */ |
| 46 | #define SEC0_LLED1S (7 << 25) /* LED1 Select */ |
| 47 | #define LLED1S_SPEED (0 << 25) |
| 48 | #define LLED1S_LINK (1 << 25) |
| 49 | #define LLED1S_DUPLEX (2 << 25) |
| 50 | #define LLED1S_COLLISION (3 << 25) |
| 51 | #define LLED1S_ACTIVITY (4 << 25) |
| 52 | #define LLED1S_FDX_COLLISION (5 << 25) |
| 53 | #define LLED1S_LINK_ACTIVITY (6 << 25) |
| 54 | #define SEC0_LLED0S (7 << 22) /* LED0 Select */ |
| 55 | #define LLED0S_SPEED (0 << 22) |
| 56 | #define LLED0S_LINK (1 << 22) |
| 57 | #define LLED0S_DUPLEX (2 << 22) |
| 58 | #define LLED0S_COLLISION (3 << 22) |
| 59 | #define LLED0S_ACTIVITY (4 << 22) |
| 60 | #define LLED0S_FDX_COLLISION (5 << 22) |
| 61 | #define LLED0S_LINK_ACTIVITY (6 << 22) |
| 62 | #define SEC0_ENABLE (1 << 0) /* Enable Switch */ |
| 63 | |
| 64 | |
| 65 | |
| 66 | #endif |