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Gregory CLEMENT928413b2015-01-08 19:11:33 +01001/*
2 * Device Tree file for Marvell Armada 385 development board
3 * (RD-88F6820-GP)
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 *
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
12 * whole.
13 *
14 * a) This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without
16 * any warranty of any kind, whether express or implied.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/dts-v1/;
43#include "armada-388.dtsi"
44#include <dt-bindings/gpio/gpio.h>
45
46/ {
47 model = "Marvell Armada 385 GP";
48 compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380";
49
50 chosen {
Thomas Petazzoni95522032015-03-03 15:41:02 +010051 stdout-path = "serial0:115200n8";
Gregory CLEMENT928413b2015-01-08 19:11:33 +010052 };
53
54 memory {
55 device_type = "memory";
56 reg = <0x00000000 0x80000000>; /* 2 GB */
57 };
58
59 soc {
60 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
Boris Brezillond716f2e2015-08-18 10:08:59 +020061 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
62 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
Marcin Wojtasc49e99c2016-03-14 09:38:58 +010063 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
64 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
Gregory CLEMENT928413b2015-01-08 19:11:33 +010065
66 internal-regs {
67 spi@10600 {
68 pinctrl-names = "default";
69 pinctrl-0 = <&spi0_pins>;
70 status = "okay";
71
72 spi-flash@0 {
73 #address-cells = <1>;
74 #size-cells = <1>;
Rafał Miłeckie9f3ed42015-05-19 13:30:46 +020075 compatible = "st,m25p128", "jedec,spi-nor";
Gregory CLEMENT928413b2015-01-08 19:11:33 +010076 reg = <0>; /* Chip select 0 */
77 spi-max-frequency = <50000000>;
78 m25p,fast-read;
79 };
80 };
81
82 i2c@11000 {
83 pinctrl-names = "default";
84 pinctrl-0 = <&i2c0_pins>;
85 status = "okay";
86 clock-frequency = <100000>;
Gregory CLEMENT928413b2015-01-08 19:11:33 +010087
88 expander0: pca9555@20 {
89 compatible = "nxp,pca9555";
90 pinctrl-names = "default";
91 pinctrl-0 = <&pca0_pins>;
92 interrupt-parent = <&gpio0>;
93 interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
94 gpio-controller;
95 #gpio-cells = <2>;
96 interrupt-controller;
97 #interrupt-cells = <2>;
98 reg = <0x20>;
99 };
100
101 expander1: pca9555@21 {
102 compatible = "nxp,pca9555";
103 pinctrl-names = "default";
104 interrupt-parent = <&gpio0>;
105 interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
106 gpio-controller;
107 #gpio-cells = <2>;
108 interrupt-controller;
109 #interrupt-cells = <2>;
110 reg = <0x21>;
111 };
112
Thomas Petazzoni7e5308b2015-06-18 14:38:40 +0200113 eeprom@57 {
114 compatible = "atmel,24c64";
115 reg = <0x57>;
116 };
Gregory CLEMENT928413b2015-01-08 19:11:33 +0100117 };
118
119 serial@12000 {
120 /*
121 * Exported on the micro USB connector CON16
122 * through an FTDI
123 */
124
125 pinctrl-names = "default";
126 pinctrl-0 = <&uart0_pins>;
127 status = "okay";
128 };
129
130 /* GE1 CON15 */
131 ethernet@30000 {
132 pinctrl-names = "default";
133 pinctrl-0 = <&ge1_rgmii_pins>;
134 status = "okay";
135 phy = <&phy1>;
136 phy-mode = "rgmii-id";
Marcin Wojtasc49e99c2016-03-14 09:38:58 +0100137 buffer-manager = <&bm>;
138 bm,pool-long = <2>;
139 bm,pool-short = <3>;
Gregory CLEMENT928413b2015-01-08 19:11:33 +0100140 };
141
142 /* CON4 */
Thomas Petazzonia165c3b2015-03-03 15:40:57 +0100143 usb@58000 {
Gregory CLEMENT928413b2015-01-08 19:11:33 +0100144 vcc-supply = <&reg_usb2_0_vbus>;
145 status = "okay";
146 };
147
148 /* GE0 CON1 */
149 ethernet@70000 {
150 pinctrl-names = "default";
151 /*
152 * The Reference Clock 0 is used to provide a
153 * clock to the PHY
154 */
155 pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
156 status = "okay";
157 phy = <&phy0>;
158 phy-mode = "rgmii-id";
Marcin Wojtasc49e99c2016-03-14 09:38:58 +0100159 buffer-manager = <&bm>;
160 bm,pool-long = <0>;
161 bm,pool-short = <1>;
Gregory CLEMENT928413b2015-01-08 19:11:33 +0100162 };
163
164
165 mdio@72004 {
166 pinctrl-names = "default";
167 pinctrl-0 = <&mdio_pins>;
168
169 phy0: ethernet-phy@1 {
170 reg = <1>;
171 };
172
173 phy1: ethernet-phy@0 {
174 reg = <0>;
175 };
176 };
177
178 sata@a8000 {
179 pinctrl-names = "default";
180 pinctrl-0 = <&sata0_pins>, <&sata1_pins>;
181 status = "okay";
182 #address-cells = <1>;
183 #size-cells = <0>;
Gregory CLEMENT0df5a6c2015-01-15 15:09:38 +0100184
185 sata0: sata-port@0 {
186 reg = <0>;
187 target-supply = <&reg_5v_sata0>;
188 };
189
190 sata1: sata-port@1 {
191 reg = <1>;
192 target-supply = <&reg_5v_sata1>;
193 };
Gregory CLEMENT928413b2015-01-08 19:11:33 +0100194 };
195
Marcin Wojtasc49e99c2016-03-14 09:38:58 +0100196 bm@c8000 {
197 status = "okay";
198 };
199
Gregory CLEMENT928413b2015-01-08 19:11:33 +0100200 sata@e0000 {
201 pinctrl-names = "default";
202 pinctrl-0 = <&sata2_pins>, <&sata3_pins>;
203 status = "okay";
204 #address-cells = <1>;
205 #size-cells = <0>;
Gregory CLEMENT0df5a6c2015-01-15 15:09:38 +0100206
207 sata2: sata-port@0 {
208 reg = <0>;
209 target-supply = <&reg_5v_sata2>;
210 };
211
212 sata3: sata-port@1 {
213 reg = <1>;
214 target-supply = <&reg_5v_sata3>;
215 };
Gregory CLEMENT928413b2015-01-08 19:11:33 +0100216 };
217
218 sdhci@d8000 {
219 pinctrl-names = "default";
220 pinctrl-0 = <&sdhci_pins>;
Gregory CLEMENT928413b2015-01-08 19:11:33 +0100221 no-1-8-v;
Marcin Wojtas6b61f242015-10-15 18:25:44 +0200222 /*
223 * A388-GP board v1.5 and higher replace
224 * hitherto card detection method based on GPIO
225 * with the one using DAT3 pin. As they are
226 * incompatible, software-based polling is
227 * enabled with 'broken-cd' property. For boards
228 * older than v1.5 it can be replaced with:
229 * 'cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;',
230 * whereas for the newer ones following can be
231 * used instead:
232 * 'dat3-cd;'
233 * 'cd-inverted;'
234 */
235 broken-cd;
Gregory CLEMENT928413b2015-01-08 19:11:33 +0100236 wp-inverted;
237 bus-width = <8>;
238 status = "okay";
239 };
240
241 /* CON5 */
242 usb3@f0000 {
243 vcc-supply = <&reg_usb2_1_vbus>;
244 status = "okay";
245 };
246
247 /* CON7 */
248 usb3@f8000 {
249 vcc-supply = <&reg_usb3_vbus>;
250 status = "okay";
251 };
252 };
253
Marcin Wojtasc49e99c2016-03-14 09:38:58 +0100254 bm-bppi {
255 status = "okay";
256 };
257
Gregory CLEMENT928413b2015-01-08 19:11:33 +0100258 pcie-controller {
259 status = "okay";
260 /*
261 * One PCIe units is accessible through
262 * standard PCIe slot on the board.
263 */
264 pcie@1,0 {
265 /* Port 0, Lane 0 */
266 status = "okay";
267 };
268
269 /*
270 * The two other PCIe units are accessible
271 * through mini PCIe slot on the board.
272 */
273 pcie@2,0 {
274 /* Port 1, Lane 0 */
275 status = "okay";
276 };
277 pcie@3,0 {
278 /* Port 2, Lane 0 */
279 status = "okay";
280 };
281 };
282
283 gpio-fan {
284 compatible = "gpio-fan";
285 gpios = <&expander1 3 GPIO_ACTIVE_HIGH>;
286 gpio-fan,speed-map = < 0 0
287 3000 1>;
288 };
289 };
290
291 reg_usb3_vbus: usb3-vbus {
292 compatible = "regulator-fixed";
293 regulator-name = "usb3-vbus";
294 regulator-min-microvolt = <5000000>;
295 regulator-max-microvolt = <5000000>;
296 enable-active-high;
297 regulator-always-on;
298 gpio = <&expander1 15 GPIO_ACTIVE_HIGH>;
299 };
300
301 reg_usb2_0_vbus: v5-vbus0 {
302 compatible = "regulator-fixed";
303 regulator-name = "v5.0-vbus0";
304 regulator-min-microvolt = <5000000>;
305 regulator-max-microvolt = <5000000>;
306 enable-active-high;
307 regulator-always-on;
308 gpio = <&expander1 14 GPIO_ACTIVE_HIGH>;
309 };
310
311 reg_usb2_1_vbus: v5-vbus1 {
312 compatible = "regulator-fixed";
313 regulator-name = "v5.0-vbus1";
314 regulator-min-microvolt = <5000000>;
315 regulator-max-microvolt = <5000000>;
316 enable-active-high;
317 regulator-always-on;
318 gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
319 };
320
Gregory CLEMENT0df5a6c2015-01-15 15:09:38 +0100321 reg_sata0: pwr-sata0 {
322 compatible = "regulator-fixed";
323 regulator-name = "pwr_en_sata0";
Thomas Petazzonib5999dc2015-06-18 14:38:39 +0200324 regulator-min-microvolt = <12000000>;
325 regulator-max-microvolt = <12000000>;
Gregory CLEMENT0df5a6c2015-01-15 15:09:38 +0100326 enable-active-high;
327 regulator-always-on;
Thomas Petazzonib5999dc2015-06-18 14:38:39 +0200328 gpio = <&expander0 2 GPIO_ACTIVE_HIGH>;
Gregory CLEMENT0df5a6c2015-01-15 15:09:38 +0100329 };
330
331 reg_5v_sata0: v5-sata0 {
332 compatible = "regulator-fixed";
333 regulator-name = "v5.0-sata0";
334 regulator-min-microvolt = <5000000>;
335 regulator-max-microvolt = <5000000>;
336 regulator-always-on;
337 vin-supply = <&reg_sata0>;
338 };
339
340 reg_12v_sata0: v12-sata0 {
341 compatible = "regulator-fixed";
342 regulator-name = "v12.0-sata0";
343 regulator-min-microvolt = <12000000>;
344 regulator-max-microvolt = <12000000>;
345 regulator-always-on;
346 vin-supply = <&reg_sata0>;
347 };
348
349 reg_sata1: pwr-sata1 {
350 regulator-name = "pwr_en_sata1";
351 compatible = "regulator-fixed";
352 regulator-min-microvolt = <12000000>;
353 regulator-max-microvolt = <12000000>;
354 enable-active-high;
355 regulator-always-on;
356 gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
357 };
358
359 reg_5v_sata1: v5-sata1 {
360 compatible = "regulator-fixed";
361 regulator-name = "v5.0-sata1";
362 regulator-min-microvolt = <5000000>;
363 regulator-max-microvolt = <5000000>;
364 regulator-always-on;
365 vin-supply = <&reg_sata1>;
366 };
367
368 reg_12v_sata1: v12-sata1 {
369 compatible = "regulator-fixed";
370 regulator-name = "v12.0-sata1";
371 regulator-min-microvolt = <12000000>;
372 regulator-max-microvolt = <12000000>;
373 regulator-always-on;
374 vin-supply = <&reg_sata1>;
375 };
376
377 reg_sata2: pwr-sata2 {
378 compatible = "regulator-fixed";
379 regulator-name = "pwr_en_sata2";
380 enable-active-high;
381 regulator-always-on;
382 gpio = <&expander0 11 GPIO_ACTIVE_HIGH>;
383 };
384
385 reg_5v_sata2: v5-sata2 {
386 compatible = "regulator-fixed";
387 regulator-name = "v5.0-sata2";
388 regulator-min-microvolt = <5000000>;
389 regulator-max-microvolt = <5000000>;
390 regulator-always-on;
391 vin-supply = <&reg_sata2>;
392 };
393
394 reg_12v_sata2: v12-sata2 {
395 compatible = "regulator-fixed";
396 regulator-name = "v12.0-sata2";
397 regulator-min-microvolt = <12000000>;
398 regulator-max-microvolt = <12000000>;
399 regulator-always-on;
400 vin-supply = <&reg_sata2>;
401 };
402
403 reg_sata3: pwr-sata3 {
404 compatible = "regulator-fixed";
405 regulator-name = "pwr_en_sata3";
406 enable-active-high;
407 regulator-always-on;
408 gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
409 };
410
411 reg_5v_sata3: v5-sata3 {
412 compatible = "regulator-fixed";
413 regulator-name = "v5.0-sata3";
414 regulator-min-microvolt = <5000000>;
415 regulator-max-microvolt = <5000000>;
416 regulator-always-on;
417 vin-supply = <&reg_sata3>;
418 };
419
420 reg_12v_sata3: v12-sata3 {
421 compatible = "regulator-fixed";
422 regulator-name = "v12.0-sata3";
423 regulator-min-microvolt = <12000000>;
424 regulator-max-microvolt = <12000000>;
425 regulator-always-on;
426 vin-supply = <&reg_sata3>;
427 };
Gregory CLEMENT928413b2015-01-08 19:11:33 +0100428};
429
430&pinctrl {
431 pca0_pins: pca0_pins {
432 marvell,pins = "mpp18";
433 marvell,function = "gpio";
434 };
435};