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eric miao2c8086a2007-09-11 19:13:17 -07001/*
2 * linux/arch/arm/mach-pxa/pxa3xx.c
3 *
4 * code specific to pxa3xx aka Monahans
5 *
6 * Copyright (C) 2006 Marvell International Ltd.
7 *
eric miaoe9bba8e2007-10-30 08:01:38 +01008 * 2007-09-02: eric miao <eric.miao@marvell.com>
eric miao2c8086a2007-09-11 19:13:17 -07009 * initial version
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/pm.h>
20#include <linux/platform_device.h>
21#include <linux/irq.h>
Russell King7b5dea12008-01-07 22:18:30 +000022#include <linux/io.h>
eric miaoc01655042008-01-28 23:00:02 +000023#include <linux/sysdev.h>
eric miao2c8086a2007-09-11 19:13:17 -070024
25#include <asm/hardware.h>
26#include <asm/arch/pxa3xx-regs.h>
27#include <asm/arch/ohci.h>
28#include <asm/arch/pm.h>
29#include <asm/arch/dma.h>
30#include <asm/arch/ssp.h>
31
32#include "generic.h"
33#include "devices.h"
34#include "clock.h"
35
36/* Crystal clock: 13MHz */
37#define BASE_CLK 13000000
38
39/* Ring Oscillator Clock: 60MHz */
40#define RO_CLK 60000000
41
42#define ACCR_D0CS (1 << 26)
eric miaoc4d1fb62008-01-28 23:00:02 +000043#define ACCR_PCCE (1 << 11)
eric miao2c8086a2007-09-11 19:13:17 -070044
45/* crystal frequency to static memory controller multiplier (SMCFS) */
46static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
47
48/* crystal frequency to HSIO bus frequency multiplier (HSS) */
49static unsigned char hss_mult[4] = { 8, 12, 16, 0 };
50
51/*
52 * Get the clock frequency as reflected by CCSR and the turbo flag.
53 * We assume these values have been applied via a fcs.
54 * If info is not 0 we also display the current settings.
55 */
56unsigned int pxa3xx_get_clk_frequency_khz(int info)
57{
58 unsigned long acsr, xclkcfg;
59 unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
60
61 /* Read XCLKCFG register turbo bit */
62 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
63 t = xclkcfg & 0x1;
64
65 acsr = ACSR;
66
67 xl = acsr & 0x1f;
68 xn = (acsr >> 8) & 0x7;
69 hss = (acsr >> 14) & 0x3;
70
71 XL = xl * BASE_CLK;
72 XN = xn * XL;
73
74 ro = acsr & ACCR_D0CS;
75
76 CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
77 HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
78
79 if (info) {
80 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
81 RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
82 (ro) ? "" : "in");
83 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
84 XL / 1000000, (XL % 1000000) / 10000, xl);
85 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
86 XN / 1000000, (XN % 1000000) / 10000, xn,
87 (t) ? "" : "in");
88 pr_info("HSIO bus clock: %d.%02dMHz\n",
89 HSS / 1000000, (HSS % 1000000) / 10000);
90 }
91
eric miao6232be32008-01-24 02:27:30 +010092 return CLK / 1000;
eric miao2c8086a2007-09-11 19:13:17 -070093}
94
95/*
96 * Return the current static memory controller clock frequency
97 * in units of 10kHz
98 */
99unsigned int pxa3xx_get_memclk_frequency_10khz(void)
100{
101 unsigned long acsr;
102 unsigned int smcfs, clk = 0;
103
104 acsr = ACSR;
105
106 smcfs = (acsr >> 23) & 0x7;
107 clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
108
109 return (clk / 10000);
110}
111
112/*
113 * Return the current HSIO bus clock frequency
114 */
115static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
116{
117 unsigned long acsr;
118 unsigned int hss, hsio_clk;
119
120 acsr = ACSR;
121
122 hss = (acsr >> 14) & 0x3;
123 hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
124
125 return hsio_clk;
126}
127
128static void clk_pxa3xx_cken_enable(struct clk *clk)
129{
130 unsigned long mask = 1ul << (clk->cken & 0x1f);
131
132 local_irq_disable();
133
134 if (clk->cken < 32)
135 CKENA |= mask;
136 else
137 CKENB |= mask;
138
139 local_irq_enable();
140}
141
142static void clk_pxa3xx_cken_disable(struct clk *clk)
143{
144 unsigned long mask = 1ul << (clk->cken & 0x1f);
145
146 local_irq_disable();
147
148 if (clk->cken < 32)
149 CKENA &= ~mask;
150 else
151 CKENB &= ~mask;
152
153 local_irq_enable();
154}
155
eric miao2a0d7182007-10-30 08:10:18 +0100156static const struct clkops clk_pxa3xx_cken_ops = {
157 .enable = clk_pxa3xx_cken_enable,
158 .disable = clk_pxa3xx_cken_disable,
159};
160
eric miao2c8086a2007-09-11 19:13:17 -0700161static const struct clkops clk_pxa3xx_hsio_ops = {
162 .enable = clk_pxa3xx_cken_enable,
163 .disable = clk_pxa3xx_cken_disable,
164 .getrate = clk_pxa3xx_hsio_getrate,
165};
166
eric miao2a0d7182007-10-30 08:10:18 +0100167#define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \
168 { \
169 .name = _name, \
170 .dev = _dev, \
171 .ops = &clk_pxa3xx_cken_ops, \
172 .rate = _rate, \
173 .cken = CKEN_##_cken, \
174 .delay = _delay, \
175 }
176
177#define PXA3xx_CK(_name, _cken, _ops, _dev) \
178 { \
179 .name = _name, \
180 .dev = _dev, \
181 .ops = _ops, \
182 .cken = CKEN_##_cken, \
183 }
184
eric miao2c8086a2007-09-11 19:13:17 -0700185static struct clk pxa3xx_clks[] = {
eric miao2a0d7182007-10-30 08:10:18 +0100186 PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
187 PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL),
eric miao2c8086a2007-09-11 19:13:17 -0700188
eric miao2a0d7182007-10-30 08:10:18 +0100189 PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
190 PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
191 PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
eric miao2c8086a2007-09-11 19:13:17 -0700192
eric miao2a0d7182007-10-30 08:10:18 +0100193 PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev),
194 PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev),
eric miaof92a6292007-12-12 09:32:01 +0800195 PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev),
eric miaod8e0db12007-12-10 17:54:36 +0800196
197 PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
198 PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
199 PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
200 PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev),
Bridge Wufafc9d32007-12-21 19:00:13 +0800201
202 PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev),
Bridge Wu8d33b052007-12-21 19:15:36 +0800203 PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev),
Bridge Wu5a1f21b2007-12-21 19:27:08 +0800204 PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev),
eric miao2c8086a2007-09-11 19:13:17 -0700205};
206
Russell King7b5dea12008-01-07 22:18:30 +0000207#ifdef CONFIG_PM
Russell King7b5dea12008-01-07 22:18:30 +0000208
209#define ISRAM_START 0x5c000000
210#define ISRAM_SIZE SZ_256K
211
212static void __iomem *sram;
213static unsigned long wakeup_src;
214
eric miaoc4d1fb62008-01-28 23:00:02 +0000215#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
216#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
217
218enum { SLEEP_SAVE_START = 0,
219 SLEEP_SAVE_CKENA,
220 SLEEP_SAVE_CKENB,
221 SLEEP_SAVE_ACCR,
222
223 SLEEP_SAVE_SIZE,
224};
225
Russell King7b5dea12008-01-07 22:18:30 +0000226static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
227{
eric miaoc4d1fb62008-01-28 23:00:02 +0000228 SAVE(CKENA);
229 SAVE(CKENB);
230 SAVE(ACCR);
Russell King7b5dea12008-01-07 22:18:30 +0000231}
232
233static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
234{
eric miaoc4d1fb62008-01-28 23:00:02 +0000235 RESTORE(ACCR);
236 RESTORE(CKENA);
237 RESTORE(CKENB);
Russell King7b5dea12008-01-07 22:18:30 +0000238}
239
240/*
241 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
242 * memory controller has to be reinitialised, so we place some code
243 * in the SRAM to perform this function.
244 *
245 * We disable FIQs across the standby - otherwise, we might receive a
246 * FIQ while the SDRAM is unavailable.
247 */
248static void pxa3xx_cpu_standby(unsigned int pwrmode)
249{
250 extern const char pm_enter_standby_start[], pm_enter_standby_end[];
251 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
252
253 memcpy_toio(sram + 0x8000, pm_enter_standby_start,
254 pm_enter_standby_end - pm_enter_standby_start);
255
256 AD2D0SR = ~0;
257 AD2D1SR = ~0;
258 AD2D0ER = wakeup_src;
259 AD2D1ER = 0;
260 ASCR = ASCR;
261 ARSR = ARSR;
262
263 local_fiq_disable();
264 fn(pwrmode);
265 local_fiq_enable();
266
267 AD2D0ER = 0;
268 AD2D1ER = 0;
269
270 printk("PM: AD2D0SR=%08x ASCR=%08x\n", AD2D0SR, ASCR);
271}
272
eric miaoc4d1fb62008-01-28 23:00:02 +0000273/*
274 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with
275 * PXA3xx development kits assumes that the resuming process continues
276 * with the address stored within the first 4 bytes of SDRAM. The PSPR
277 * register is used privately by BootROM and OBM, and _must_ be set to
278 * 0x5c014000 for the moment.
279 */
280static void pxa3xx_cpu_pm_suspend(void)
281{
282 volatile unsigned long *p = (volatile void *)0xc0000000;
283 unsigned long saved_data = *p;
284
285 extern void pxa3xx_cpu_suspend(void);
286 extern void pxa3xx_cpu_resume(void);
287
288 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
289 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
290 CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
291
292 /* clear and setup wakeup source */
293 AD3SR = ~0;
294 AD3ER = wakeup_src;
295 ASCR = ASCR;
296 ARSR = ARSR;
297
298 PCFR |= (1u << 13); /* L1_DIS */
299 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */
300
301 PSPR = 0x5c014000;
302
303 /* overwrite with the resume address */
304 *p = virt_to_phys(pxa3xx_cpu_resume);
305
306 pxa3xx_cpu_suspend();
307
308 *p = saved_data;
309
310 AD3ER = 0;
311}
312
Russell King7b5dea12008-01-07 22:18:30 +0000313static void pxa3xx_cpu_pm_enter(suspend_state_t state)
314{
315 /*
316 * Don't sleep if no wakeup sources are defined
317 */
318 if (wakeup_src == 0)
319 return;
320
321 switch (state) {
322 case PM_SUSPEND_STANDBY:
323 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
324 break;
325
326 case PM_SUSPEND_MEM:
eric miaoc4d1fb62008-01-28 23:00:02 +0000327 pxa3xx_cpu_pm_suspend();
Russell King7b5dea12008-01-07 22:18:30 +0000328 break;
329 }
330}
331
332static int pxa3xx_cpu_pm_valid(suspend_state_t state)
333{
334 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
335}
336
337static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
338 .save_size = SLEEP_SAVE_SIZE,
339 .save = pxa3xx_cpu_pm_save,
340 .restore = pxa3xx_cpu_pm_restore,
341 .valid = pxa3xx_cpu_pm_valid,
342 .enter = pxa3xx_cpu_pm_enter,
343};
344
345static void __init pxa3xx_init_pm(void)
346{
347 sram = ioremap(ISRAM_START, ISRAM_SIZE);
348 if (!sram) {
349 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
350 return;
351 }
352
353 /*
354 * Since we copy wakeup code into the SRAM, we need to ensure
355 * that it is preserved over the low power modes. Note: bit 8
356 * is undocumented in the developer manual, but must be set.
357 */
358 AD1R |= ADXR_L2 | ADXR_R0;
359 AD2R |= ADXR_L2 | ADXR_R0;
360 AD3R |= ADXR_L2 | ADXR_R0;
361
362 /*
363 * Clear the resume enable registers.
364 */
365 AD1D0ER = 0;
366 AD2D0ER = 0;
367 AD2D1ER = 0;
368 AD3ER = 0;
369
370 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
371}
372
373static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
374{
375 unsigned long flags, mask = 0;
376
377 switch (irq) {
378 case IRQ_SSP3:
379 mask = ADXER_MFP_WSSP3;
380 break;
381 case IRQ_MSL:
382 mask = ADXER_WMSL0;
383 break;
384 case IRQ_USBH2:
385 case IRQ_USBH1:
386 mask = ADXER_WUSBH;
387 break;
388 case IRQ_KEYPAD:
389 mask = ADXER_WKP;
390 break;
391 case IRQ_AC97:
392 mask = ADXER_MFP_WAC97;
393 break;
394 case IRQ_USIM:
395 mask = ADXER_WUSIM0;
396 break;
397 case IRQ_SSP2:
398 mask = ADXER_MFP_WSSP2;
399 break;
400 case IRQ_I2C:
401 mask = ADXER_MFP_WI2C;
402 break;
403 case IRQ_STUART:
404 mask = ADXER_MFP_WUART3;
405 break;
406 case IRQ_BTUART:
407 mask = ADXER_MFP_WUART2;
408 break;
409 case IRQ_FFUART:
410 mask = ADXER_MFP_WUART1;
411 break;
412 case IRQ_MMC:
413 mask = ADXER_MFP_WMMC1;
414 break;
415 case IRQ_SSP:
416 mask = ADXER_MFP_WSSP1;
417 break;
418 case IRQ_RTCAlrm:
419 mask = ADXER_WRTC;
420 break;
421 case IRQ_SSP4:
422 mask = ADXER_MFP_WSSP4;
423 break;
424 case IRQ_TSI:
425 mask = ADXER_WTSI;
426 break;
427 case IRQ_USIM2:
428 mask = ADXER_WUSIM1;
429 break;
430 case IRQ_MMC2:
431 mask = ADXER_MFP_WMMC2;
432 break;
433 case IRQ_NAND:
434 mask = ADXER_MFP_WFLASH;
435 break;
436 case IRQ_USB2:
437 mask = ADXER_WUSB2;
438 break;
439 case IRQ_WAKEUP0:
440 mask = ADXER_WEXTWAKE0;
441 break;
442 case IRQ_WAKEUP1:
443 mask = ADXER_WEXTWAKE1;
444 break;
445 case IRQ_MMC3:
446 mask = ADXER_MFP_GEN12;
447 break;
448 }
449
450 local_irq_save(flags);
451 if (on)
452 wakeup_src |= mask;
453 else
454 wakeup_src &= ~mask;
455 local_irq_restore(flags);
456
457 return 0;
458}
459
460static void pxa3xx_init_irq_pm(void)
461{
462 pxa_init_irq_set_wake(pxa3xx_set_wake);
463}
464
465#else
466static inline void pxa3xx_init_pm(void) {}
467static inline void pxa3xx_init_irq_pm(void) {}
468#endif
469
eric miao2c8086a2007-09-11 19:13:17 -0700470void __init pxa3xx_init_irq(void)
471{
472 /* enable CP6 access */
473 u32 value;
474 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
475 value |= (1 << 6);
476 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
477
478 pxa_init_irq_low();
479 pxa_init_irq_high();
480 pxa_init_irq_gpio(128);
Russell King7b5dea12008-01-07 22:18:30 +0000481 pxa3xx_init_irq_pm();
eric miao2c8086a2007-09-11 19:13:17 -0700482}
483
484/*
485 * device registration specific to PXA3xx.
486 */
487
488static struct platform_device *devices[] __initdata = {
eric miao2c8086a2007-09-11 19:13:17 -0700489 &pxa_device_udc,
eric miao2c8086a2007-09-11 19:13:17 -0700490 &pxa_device_ffuart,
491 &pxa_device_btuart,
492 &pxa_device_stuart,
eric miao2c8086a2007-09-11 19:13:17 -0700493 &pxa_device_i2s,
eric miao2c8086a2007-09-11 19:13:17 -0700494 &pxa_device_rtc,
eric miaod8e0db12007-12-10 17:54:36 +0800495 &pxa27x_device_ssp1,
496 &pxa27x_device_ssp2,
497 &pxa27x_device_ssp3,
498 &pxa3xx_device_ssp4,
eric miao2c8086a2007-09-11 19:13:17 -0700499};
500
eric miaoc01655042008-01-28 23:00:02 +0000501static struct sys_device pxa3xx_sysdev[] = {
502 {
503 .id = 0,
504 .cls = &pxa_irq_sysclass,
505 }, {
506 .id = 1,
507 .cls = &pxa_irq_sysclass,
eric miao16dfdbf2008-01-28 23:00:02 +0000508 }, {
509 .cls = &pxa_gpio_sysclass,
eric miaoc01655042008-01-28 23:00:02 +0000510 },
511};
512
eric miao2c8086a2007-09-11 19:13:17 -0700513static int __init pxa3xx_init(void)
514{
eric miaoc01655042008-01-28 23:00:02 +0000515 int i, ret = 0;
eric miao2c8086a2007-09-11 19:13:17 -0700516
517 if (cpu_is_pxa3xx()) {
518 clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));
519
520 if ((ret = pxa_init_dma(32)))
521 return ret;
522
Russell King7b5dea12008-01-07 22:18:30 +0000523 pxa3xx_init_pm();
524
eric miaoc01655042008-01-28 23:00:02 +0000525 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
526 ret = sysdev_register(&pxa3xx_sysdev[i]);
527 if (ret)
528 pr_err("failed to register sysdev[%d]\n", i);
529 }
530
531 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
eric miao2c8086a2007-09-11 19:13:17 -0700532 }
eric miaoc01655042008-01-28 23:00:02 +0000533
534 return ret;
eric miao2c8086a2007-09-11 19:13:17 -0700535}
536
537subsys_initcall(pxa3xx_init);