H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 1 | #ifndef _ASM_X86_MCE_H |
| 2 | #define _ASM_X86_MCE_H |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 3 | |
Jaswinder Singh Rajput | 999b697 | 2009-01-30 22:47:27 +0530 | [diff] [blame] | 4 | #include <linux/types.h> |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 5 | #include <asm/ioctls.h> |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 6 | |
| 7 | /* |
| 8 | * Machine Check support for x86 |
| 9 | */ |
| 10 | |
Thomas Gleixner | 01c6680 | 2009-04-08 12:31:24 +0200 | [diff] [blame] | 11 | #define MCG_BANKCNT_MASK 0xff /* Number of Banks */ |
Borislav Petkov | e487683 | 2009-06-20 23:27:16 -0700 | [diff] [blame] | 12 | #define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */ |
Thomas Gleixner | 01c6680 | 2009-04-08 12:31:24 +0200 | [diff] [blame] | 13 | #define MCG_EXT_P (1ULL<<9) /* Extended registers available */ |
| 14 | #define MCG_CMCI_P (1ULL<<10) /* CMCI supported */ |
| 15 | #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */ |
| 16 | #define MCG_EXT_CNT_SHIFT 16 |
| 17 | #define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT) |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 18 | #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 19 | |
Ingo Molnar | 06b851d | 2009-04-08 12:31:25 +0200 | [diff] [blame] | 20 | #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ |
| 21 | #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ |
| 22 | #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 23 | |
Ingo Molnar | 06b851d | 2009-04-08 12:31:25 +0200 | [diff] [blame] | 24 | #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ |
| 25 | #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ |
| 26 | #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ |
| 27 | #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ |
| 28 | #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ |
| 29 | #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ |
| 30 | #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 31 | #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ |
| 32 | #define MCI_STATUS_AR (1ULL<<55) /* Action required */ |
| 33 | |
| 34 | /* MISC register defines */ |
| 35 | #define MCM_ADDR_SEGOFF 0 /* segment offset */ |
| 36 | #define MCM_ADDR_LINEAR 1 /* linear address */ |
| 37 | #define MCM_ADDR_PHYS 2 /* physical address */ |
| 38 | #define MCM_ADDR_MEM 3 /* memory address */ |
| 39 | #define MCM_ADDR_GENERIC 7 /* generic */ |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 40 | |
Huang Ying | 5b7e88e | 2009-07-31 09:41:40 +0800 | [diff] [blame] | 41 | #define MCJ_CTX_MASK 3 |
| 42 | #define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK) |
| 43 | #define MCJ_CTX_RANDOM 0 /* inject context: random */ |
| 44 | #define MCJ_CTX_PROCESS 1 /* inject context: process */ |
| 45 | #define MCJ_CTX_IRQ 2 /* inject context: IRQ */ |
| 46 | #define MCJ_NMI_BROADCAST 4 /* do NMI broadcasting */ |
Huang Ying | 0dcc668 | 2009-07-31 09:41:41 +0800 | [diff] [blame] | 47 | #define MCJ_EXCEPTION 8 /* raise as exception */ |
Huang Ying | 5b7e88e | 2009-07-31 09:41:40 +0800 | [diff] [blame] | 48 | |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 49 | /* Fields are zero when not available */ |
| 50 | struct mce { |
| 51 | __u64 status; |
| 52 | __u64 misc; |
| 53 | __u64 addr; |
| 54 | __u64 mcgstatus; |
H. Peter Anvin | 65ea5b0 | 2008-01-30 13:30:56 +0100 | [diff] [blame] | 55 | __u64 ip; |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 56 | __u64 tsc; /* cpu time stamp counter */ |
Andi Kleen | 8ee0834 | 2009-05-27 21:56:56 +0200 | [diff] [blame] | 57 | __u64 time; /* wall time_t when error was detected */ |
| 58 | __u8 cpuvendor; /* cpu vendor as encoded in system.h */ |
Huang Ying | 5b7e88e | 2009-07-31 09:41:40 +0800 | [diff] [blame] | 59 | __u8 inject_flags; /* software inject flags */ |
| 60 | __u16 pad; |
Andi Kleen | 8ee0834 | 2009-05-27 21:56:56 +0200 | [diff] [blame] | 61 | __u32 cpuid; /* CPUID 1 EAX */ |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 62 | __u8 cs; /* code segment */ |
| 63 | __u8 bank; /* machine check bank */ |
Andi Kleen | d620c67 | 2009-05-27 21:56:56 +0200 | [diff] [blame] | 64 | __u8 cpu; /* cpu number; obsolete; use extcpu now */ |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 65 | __u8 finished; /* entry is valid */ |
Andi Kleen | d620c67 | 2009-05-27 21:56:56 +0200 | [diff] [blame] | 66 | __u32 extcpu; /* linux cpu number that detected the error */ |
Andi Kleen | 8ee0834 | 2009-05-27 21:56:56 +0200 | [diff] [blame] | 67 | __u32 socketid; /* CPU socket ID */ |
| 68 | __u32 apicid; /* CPU initial apic ID */ |
| 69 | __u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */ |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 70 | }; |
| 71 | |
| 72 | /* |
| 73 | * This structure contains all data related to the MCE log. Also |
| 74 | * carries a signature to make it easier to find from external |
| 75 | * debugging tools. Each entry is only valid when its finished flag |
| 76 | * is set. |
| 77 | */ |
| 78 | |
| 79 | #define MCE_LOG_LEN 32 |
| 80 | |
| 81 | struct mce_log { |
| 82 | char signature[12]; /* "MACHINECHECK" */ |
| 83 | unsigned len; /* = MCE_LOG_LEN */ |
| 84 | unsigned next; |
| 85 | unsigned flags; |
Andi Kleen | f6fb0ac | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 86 | unsigned recordlen; /* length of struct mce */ |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 87 | struct mce entry[MCE_LOG_LEN]; |
| 88 | }; |
| 89 | |
| 90 | #define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */ |
| 91 | |
| 92 | #define MCE_LOG_SIGNATURE "MACHINECHECK" |
| 93 | |
| 94 | #define MCE_GET_RECORD_LEN _IOR('M', 1, int) |
| 95 | #define MCE_GET_LOG_LEN _IOR('M', 2, int) |
| 96 | #define MCE_GETCLEAR_FLAGS _IOR('M', 3, int) |
| 97 | |
| 98 | /* Software defined banks */ |
| 99 | #define MCE_EXTENDED_BANK 128 |
| 100 | #define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0 |
| 101 | |
| 102 | #define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */ |
| 103 | #define K8_MCE_THRESHOLD_BANK_0 (MCE_THRESHOLD_BASE + 0 * 9) |
| 104 | #define K8_MCE_THRESHOLD_BANK_1 (MCE_THRESHOLD_BASE + 1 * 9) |
| 105 | #define K8_MCE_THRESHOLD_BANK_2 (MCE_THRESHOLD_BASE + 2 * 9) |
| 106 | #define K8_MCE_THRESHOLD_BANK_3 (MCE_THRESHOLD_BASE + 3 * 9) |
| 107 | #define K8_MCE_THRESHOLD_BANK_4 (MCE_THRESHOLD_BASE + 4 * 9) |
| 108 | #define K8_MCE_THRESHOLD_BANK_5 (MCE_THRESHOLD_BASE + 5 * 9) |
| 109 | #define K8_MCE_THRESHOLD_DRAM_ECC (MCE_THRESHOLD_BANK_4 + 0) |
| 110 | |
Borislav Petkov | fb25319 | 2009-10-07 13:20:38 +0200 | [diff] [blame] | 111 | |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 112 | #ifdef __KERNEL__ |
| 113 | |
Alan Cox | df39a2e | 2010-01-04 16:17:21 +0000 | [diff] [blame] | 114 | extern struct atomic_notifier_head x86_mce_decoder_chain; |
| 115 | |
Hidetoshi Seto | 9e55e44 | 2009-06-15 17:22:15 +0900 | [diff] [blame] | 116 | #include <linux/percpu.h> |
| 117 | #include <linux/init.h> |
| 118 | #include <asm/atomic.h> |
| 119 | |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 120 | extern int mce_disabled; |
Hidetoshi Seto | c697836 | 2009-06-15 17:22:49 +0900 | [diff] [blame] | 121 | extern int mce_p5_enabled; |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 122 | |
Hidetoshi Seto | 58995d2 | 2009-06-15 17:27:47 +0900 | [diff] [blame] | 123 | #ifdef CONFIG_X86_MCE |
Yong Wang | a2202aa | 2009-11-10 09:38:24 +0800 | [diff] [blame] | 124 | int mcheck_init(void); |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 125 | void mcheck_cpu_init(struct cpuinfo_x86 *c); |
Hidetoshi Seto | 58995d2 | 2009-06-15 17:27:47 +0900 | [diff] [blame] | 126 | #else |
Yong Wang | a2202aa | 2009-11-10 09:38:24 +0800 | [diff] [blame] | 127 | static inline int mcheck_init(void) { return 0; } |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 128 | static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {} |
Hidetoshi Seto | 58995d2 | 2009-06-15 17:27:47 +0900 | [diff] [blame] | 129 | #endif |
| 130 | |
Hidetoshi Seto | 9e55e44 | 2009-06-15 17:22:15 +0900 | [diff] [blame] | 131 | #ifdef CONFIG_X86_ANCIENT_MCE |
| 132 | void intel_p5_mcheck_init(struct cpuinfo_x86 *c); |
| 133 | void winchip_mcheck_init(struct cpuinfo_x86 *c); |
Hidetoshi Seto | c697836 | 2009-06-15 17:22:49 +0900 | [diff] [blame] | 134 | static inline void enable_p5_mce(void) { mce_p5_enabled = 1; } |
Hidetoshi Seto | 9e55e44 | 2009-06-15 17:22:15 +0900 | [diff] [blame] | 135 | #else |
| 136 | static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {} |
| 137 | static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {} |
Hidetoshi Seto | c697836 | 2009-06-15 17:22:49 +0900 | [diff] [blame] | 138 | static inline void enable_p5_mce(void) {} |
Hidetoshi Seto | 9e55e44 | 2009-06-15 17:22:15 +0900 | [diff] [blame] | 139 | #endif |
| 140 | |
Ingo Molnar | f436f8b | 2009-10-01 16:14:32 +0200 | [diff] [blame] | 141 | extern void (*x86_mce_decode_callback)(struct mce *m); |
| 142 | |
Andi Kleen | b5f2fa4 | 2009-02-12 13:43:22 +0100 | [diff] [blame] | 143 | void mce_setup(struct mce *m); |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 144 | void mce_log(struct mce *m); |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 145 | DECLARE_PER_CPU(struct sys_device, mce_dev); |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 146 | |
Andi Kleen | 41fdff3 | 2009-02-12 13:49:30 +0100 | [diff] [blame] | 147 | /* |
Andi Kleen | 3ccdccf | 2009-07-09 00:31:45 +0200 | [diff] [blame] | 148 | * Maximum banks number. |
| 149 | * This is the limit of the current register layout on |
| 150 | * Intel CPUs. |
Andi Kleen | 41fdff3 | 2009-02-12 13:49:30 +0100 | [diff] [blame] | 151 | */ |
Andi Kleen | 3ccdccf | 2009-07-09 00:31:45 +0200 | [diff] [blame] | 152 | #define MAX_NR_BANKS 32 |
Andi Kleen | 41fdff3 | 2009-02-12 13:49:30 +0100 | [diff] [blame] | 153 | |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 154 | #ifdef CONFIG_X86_MCE_INTEL |
Hidetoshi Seto | 62fdac5 | 2009-06-11 16:06:07 +0900 | [diff] [blame] | 155 | extern int mce_cmci_disabled; |
| 156 | extern int mce_ignore_ce; |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 157 | void mce_intel_feature_init(struct cpuinfo_x86 *c); |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 158 | void cmci_clear(void); |
| 159 | void cmci_reenable(void); |
| 160 | void cmci_rediscover(int dying); |
| 161 | void cmci_recheck(void); |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 162 | #else |
| 163 | static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { } |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 164 | static inline void cmci_clear(void) {} |
| 165 | static inline void cmci_reenable(void) {} |
| 166 | static inline void cmci_rediscover(int dying) {} |
| 167 | static inline void cmci_recheck(void) {} |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 168 | #endif |
| 169 | |
| 170 | #ifdef CONFIG_X86_MCE_AMD |
| 171 | void mce_amd_feature_init(struct cpuinfo_x86 *c); |
| 172 | #else |
| 173 | static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } |
| 174 | #endif |
| 175 | |
H. Peter Anvin | 3873607 | 2009-05-28 10:05:33 -0700 | [diff] [blame] | 176 | int mce_available(struct cpuinfo_x86 *c); |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 177 | |
Andi Kleen | 01ca79f | 2009-05-27 21:56:52 +0200 | [diff] [blame] | 178 | DECLARE_PER_CPU(unsigned, mce_exception_count); |
Andi Kleen | ca84f69 | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 179 | DECLARE_PER_CPU(unsigned, mce_poll_count); |
Andi Kleen | 01ca79f | 2009-05-27 21:56:52 +0200 | [diff] [blame] | 180 | |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 181 | extern atomic_t mce_entry; |
| 182 | |
Andi Kleen | ee031c3 | 2009-02-12 13:49:34 +0100 | [diff] [blame] | 183 | typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS); |
| 184 | DECLARE_PER_CPU(mce_banks_t, mce_poll_banks); |
| 185 | |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 186 | enum mcp_flags { |
| 187 | MCP_TIMESTAMP = (1 << 0), /* log time stamp */ |
| 188 | MCP_UC = (1 << 1), /* log uncorrected errors */ |
Andi Kleen | 5679af4 | 2009-04-07 17:06:55 +0200 | [diff] [blame] | 189 | MCP_DONTLOG = (1 << 2), /* only clear, don't log */ |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 190 | }; |
H. Peter Anvin | 3873607 | 2009-05-28 10:05:33 -0700 | [diff] [blame] | 191 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b); |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 192 | |
Andi Kleen | 9ff36ee | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 193 | int mce_notify_irq(void); |
Andi Kleen | 9b1beaf | 2009-05-27 21:56:59 +0200 | [diff] [blame] | 194 | void mce_notify_process(void); |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 195 | |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 196 | DECLARE_PER_CPU(struct mce, injectm); |
| 197 | extern struct file_operations mce_chrdev_ops; |
| 198 | |
Hidetoshi Seto | 58995d2 | 2009-06-15 17:27:47 +0900 | [diff] [blame] | 199 | /* |
| 200 | * Exception handler |
| 201 | */ |
| 202 | |
| 203 | /* Call the installed machine check handler for this CPU setup. */ |
| 204 | extern void (*machine_check_vector)(struct pt_regs *, long error_code); |
| 205 | void do_machine_check(struct pt_regs *, long); |
| 206 | |
| 207 | /* |
| 208 | * Threshold handler |
| 209 | */ |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 210 | |
Andi Kleen | b276268 | 2009-02-12 13:49:31 +0100 | [diff] [blame] | 211 | extern void (*mce_threshold_vector)(void); |
Hidetoshi Seto | 58995d2 | 2009-06-15 17:27:47 +0900 | [diff] [blame] | 212 | extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); |
Andi Kleen | b276268 | 2009-02-12 13:49:31 +0100 | [diff] [blame] | 213 | |
Hidetoshi Seto | e8ce2c5 | 2009-06-15 17:24:40 +0900 | [diff] [blame] | 214 | /* |
| 215 | * Thermal handler |
| 216 | */ |
| 217 | |
Hidetoshi Seto | e8ce2c5 | 2009-06-15 17:24:40 +0900 | [diff] [blame] | 218 | void intel_init_thermal(struct cpuinfo_x86 *c); |
| 219 | |
Hidetoshi Seto | e8ce2c5 | 2009-06-15 17:24:40 +0900 | [diff] [blame] | 220 | void mce_log_therm_throt_event(__u64 status); |
Yong Wang | a2202aa | 2009-11-10 09:38:24 +0800 | [diff] [blame] | 221 | |
| 222 | #ifdef CONFIG_X86_THERMAL_VECTOR |
| 223 | extern void mcheck_intel_therm_init(void); |
| 224 | #else |
| 225 | static inline void mcheck_intel_therm_init(void) { } |
| 226 | #endif |
| 227 | |
Huang Ying | d334a49 | 2010-05-18 14:35:20 +0800 | [diff] [blame] | 228 | /* |
| 229 | * Used by APEI to report memory error via /dev/mcelog |
| 230 | */ |
| 231 | |
| 232 | struct cper_sec_mem_err; |
| 233 | extern void apei_mce_report_mem_error(int corrected, |
| 234 | struct cper_sec_mem_err *mem_err); |
| 235 | |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 236 | #endif /* __KERNEL__ */ |
H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 237 | #endif /* _ASM_X86_MCE_H */ |