H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 1 | #ifndef _ASM_X86_MSR_H |
| 2 | #define _ASM_X86_MSR_H |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 3 | |
| 4 | #include <asm/msr-index.h> |
| 5 | |
Glauber de Oliveira Costa | 8f12dea | 2008-01-30 13:31:06 +0100 | [diff] [blame] | 6 | #ifndef __ASSEMBLY__ |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 7 | |
Jaswinder Singh Rajput | 8fa62ad | 2009-06-17 14:11:10 +0530 | [diff] [blame] | 8 | #include <linux/types.h> |
H. Peter Anvin | ff55df5 | 2009-08-31 14:16:57 -0700 | [diff] [blame] | 9 | #include <linux/ioctl.h> |
| 10 | |
| 11 | #define X86_IOC_RDMSR_REGS _IOWR('c', 0xA0, __u32[8]) |
| 12 | #define X86_IOC_WRMSR_REGS _IOWR('c', 0xA1, __u32[8]) |
| 13 | |
| 14 | #ifdef __KERNEL__ |
| 15 | |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 16 | #include <asm/asm.h> |
| 17 | #include <asm/errno.h> |
Borislav Petkov | 6bc1096 | 2009-05-22 12:12:01 +0200 | [diff] [blame] | 18 | #include <asm/cpumask.h> |
| 19 | |
| 20 | struct msr { |
| 21 | union { |
| 22 | struct { |
| 23 | u32 l; |
| 24 | u32 h; |
| 25 | }; |
| 26 | u64 q; |
| 27 | }; |
| 28 | }; |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 29 | |
Borislav Petkov | 6ede31e | 2009-12-17 00:16:25 +0100 | [diff] [blame] | 30 | struct msr_info { |
| 31 | u32 msr_no; |
| 32 | struct msr reg; |
| 33 | struct msr *msrs; |
| 34 | int err; |
| 35 | }; |
| 36 | |
| 37 | struct msr_regs_info { |
| 38 | u32 *regs; |
| 39 | int err; |
| 40 | }; |
| 41 | |
Andrew Morton | 1e160cc | 2008-01-30 13:31:17 +0100 | [diff] [blame] | 42 | static inline unsigned long long native_read_tscp(unsigned int *aux) |
Glauber de Oliveira Costa | 8f12dea | 2008-01-30 13:31:06 +0100 | [diff] [blame] | 43 | { |
| 44 | unsigned long low, high; |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 45 | asm volatile(".byte 0x0f,0x01,0xf9" |
| 46 | : "=a" (low), "=d" (high), "=c" (*aux)); |
Max Asbock | 41aefdc | 2008-06-25 14:45:28 -0700 | [diff] [blame] | 47 | return low | ((u64)high << 32); |
Glauber de Oliveira Costa | 8f12dea | 2008-01-30 13:31:06 +0100 | [diff] [blame] | 48 | } |
| 49 | |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 50 | /* |
Jike Song | d4f1b10 | 2008-10-17 13:25:07 +0800 | [diff] [blame] | 51 | * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A" |
| 52 | * constraint has different meanings. For i386, "A" means exactly |
| 53 | * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead, |
| 54 | * it means rax *or* rdx. |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 55 | */ |
| 56 | #ifdef CONFIG_X86_64 |
| 57 | #define DECLARE_ARGS(val, low, high) unsigned low, high |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 58 | #define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32)) |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 59 | #define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high) |
| 60 | #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) |
| 61 | #else |
| 62 | #define DECLARE_ARGS(val, low, high) unsigned long long val |
| 63 | #define EAX_EDX_VAL(val, low, high) (val) |
| 64 | #define EAX_EDX_ARGS(val, low, high) "A" (val) |
| 65 | #define EAX_EDX_RET(val, low, high) "=A" (val) |
Glauber de Oliveira Costa | 8f12dea | 2008-01-30 13:31:06 +0100 | [diff] [blame] | 66 | #endif |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 67 | |
| 68 | static inline unsigned long long native_read_msr(unsigned int msr) |
| 69 | { |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 70 | DECLARE_ARGS(val, low, high); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 71 | |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 72 | asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr)); |
| 73 | return EAX_EDX_VAL(val, low, high); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 74 | } |
| 75 | |
| 76 | static inline unsigned long long native_read_msr_safe(unsigned int msr, |
| 77 | int *err) |
| 78 | { |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 79 | DECLARE_ARGS(val, low, high); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 80 | |
H. Peter Anvin | 08970fc | 2008-08-25 22:39:15 -0700 | [diff] [blame] | 81 | asm volatile("2: rdmsr ; xor %[err],%[err]\n" |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 82 | "1:\n\t" |
| 83 | ".section .fixup,\"ax\"\n\t" |
H. Peter Anvin | 08970fc | 2008-08-25 22:39:15 -0700 | [diff] [blame] | 84 | "3: mov %[fault],%[err] ; jmp 1b\n\t" |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 85 | ".previous\n\t" |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 86 | _ASM_EXTABLE(2b, 3b) |
H. Peter Anvin | 08970fc | 2008-08-25 22:39:15 -0700 | [diff] [blame] | 87 | : [err] "=r" (*err), EAX_EDX_RET(val, low, high) |
H. Peter Anvin | 0cc0213 | 2009-08-31 14:23:29 -0700 | [diff] [blame] | 88 | : "c" (msr), [fault] "i" (-EIO)); |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 89 | return EAX_EDX_VAL(val, low, high); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 90 | } |
| 91 | |
Glauber de Oliveira Costa | c9dcda5 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 92 | static inline void native_write_msr(unsigned int msr, |
| 93 | unsigned low, unsigned high) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 94 | { |
Jeremy Fitzhardinge | af2b1c6 | 2008-06-25 00:18:59 -0400 | [diff] [blame] | 95 | asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory"); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 96 | } |
| 97 | |
Frederic Weisbecker | 0ca59dd | 2008-12-24 23:30:02 +0100 | [diff] [blame] | 98 | /* Can be uninlined because referenced by paravirt */ |
| 99 | notrace static inline int native_write_msr_safe(unsigned int msr, |
Glauber de Oliveira Costa | c9dcda5 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 100 | unsigned low, unsigned high) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 101 | { |
| 102 | int err; |
H. Peter Anvin | 08970fc | 2008-08-25 22:39:15 -0700 | [diff] [blame] | 103 | asm volatile("2: wrmsr ; xor %[err],%[err]\n" |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 104 | "1:\n\t" |
| 105 | ".section .fixup,\"ax\"\n\t" |
H. Peter Anvin | 08970fc | 2008-08-25 22:39:15 -0700 | [diff] [blame] | 106 | "3: mov %[fault],%[err] ; jmp 1b\n\t" |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 107 | ".previous\n\t" |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 108 | _ASM_EXTABLE(2b, 3b) |
H. Peter Anvin | 08970fc | 2008-08-25 22:39:15 -0700 | [diff] [blame] | 109 | : [err] "=a" (err) |
Glauber de Oliveira Costa | c9dcda5 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 110 | : "c" (msr), "0" (low), "d" (high), |
H. Peter Anvin | 0cc0213 | 2009-08-31 14:23:29 -0700 | [diff] [blame] | 111 | [fault] "i" (-EIO) |
Jeremy Fitzhardinge | af2b1c6 | 2008-06-25 00:18:59 -0400 | [diff] [blame] | 112 | : "memory"); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 113 | return err; |
| 114 | } |
| 115 | |
Ingo Molnar | cdc7957 | 2008-01-30 13:32:39 +0100 | [diff] [blame] | 116 | extern unsigned long long native_read_tsc(void); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 117 | |
H. Peter Anvin | 8b956bf | 2009-08-31 14:13:48 -0700 | [diff] [blame] | 118 | extern int native_rdmsr_safe_regs(u32 regs[8]); |
| 119 | extern int native_wrmsr_safe_regs(u32 regs[8]); |
Borislav Petkov | 132ec92 | 2009-08-31 09:50:09 +0200 | [diff] [blame] | 120 | |
Ingo Molnar | 92767af | 2008-01-30 13:32:40 +0100 | [diff] [blame] | 121 | static __always_inline unsigned long long __native_read_tsc(void) |
| 122 | { |
| 123 | DECLARE_ARGS(val, low, high); |
| 124 | |
Ingo Molnar | 92767af | 2008-01-30 13:32:40 +0100 | [diff] [blame] | 125 | asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); |
Ingo Molnar | 92767af | 2008-01-30 13:32:40 +0100 | [diff] [blame] | 126 | |
| 127 | return EAX_EDX_VAL(val, low, high); |
| 128 | } |
| 129 | |
Glauber de Oliveira Costa | b8d1fae | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 130 | static inline unsigned long long native_read_pmc(int counter) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 131 | { |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 132 | DECLARE_ARGS(val, low, high); |
| 133 | |
| 134 | asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); |
| 135 | return EAX_EDX_VAL(val, low, high); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | #ifdef CONFIG_PARAVIRT |
| 139 | #include <asm/paravirt.h> |
Thomas Gleixner | 96a388d | 2007-10-11 11:20:03 +0200 | [diff] [blame] | 140 | #else |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 141 | #include <linux/errno.h> |
| 142 | /* |
| 143 | * Access to machine-specific registers (available on 586 and better only) |
| 144 | * Note: the rd* operations modify the parameters directly (without using |
| 145 | * pointer indirection), this allows gcc to optimize better |
| 146 | */ |
| 147 | |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 148 | #define rdmsr(msr, val1, val2) \ |
| 149 | do { \ |
| 150 | u64 __val = native_read_msr((msr)); \ |
| 151 | (val1) = (u32)__val; \ |
| 152 | (val2) = (u32)(__val >> 32); \ |
| 153 | } while (0) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 154 | |
Glauber de Oliveira Costa | c9dcda5 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 155 | static inline void wrmsr(unsigned msr, unsigned low, unsigned high) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 156 | { |
Glauber de Oliveira Costa | c9dcda5 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 157 | native_write_msr(msr, low, high); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 158 | } |
| 159 | |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 160 | #define rdmsrl(msr, val) \ |
| 161 | ((val) = native_read_msr((msr))) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 162 | |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 163 | #define wrmsrl(msr, val) \ |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 164 | native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32)) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 165 | |
| 166 | /* wrmsr with exception handling */ |
Glauber de Oliveira Costa | c9dcda5 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 167 | static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 168 | { |
Glauber de Oliveira Costa | c9dcda5 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 169 | return native_write_msr_safe(msr, low, high); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 170 | } |
| 171 | |
| 172 | /* rdmsr with exception handling */ |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 173 | #define rdmsr_safe(msr, p1, p2) \ |
| 174 | ({ \ |
| 175 | int __err; \ |
| 176 | u64 __val = native_read_msr_safe((msr), &__err); \ |
| 177 | (*p1) = (u32)__val; \ |
| 178 | (*p2) = (u32)(__val >> 32); \ |
| 179 | __err; \ |
| 180 | }) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 181 | |
Andi Kleen | 1de87bd | 2008-03-22 10:59:28 +0100 | [diff] [blame] | 182 | static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) |
| 183 | { |
| 184 | int err; |
| 185 | |
| 186 | *p = native_read_msr_safe(msr, &err); |
| 187 | return err; |
| 188 | } |
Borislav Petkov | 177fed1 | 2009-08-31 09:50:10 +0200 | [diff] [blame] | 189 | |
Yinghai Lu | b05f78f | 2008-08-22 01:32:50 -0700 | [diff] [blame] | 190 | static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) |
| 191 | { |
Borislav Petkov | 177fed1 | 2009-08-31 09:50:10 +0200 | [diff] [blame] | 192 | u32 gprs[8] = { 0 }; |
Yinghai Lu | b05f78f | 2008-08-22 01:32:50 -0700 | [diff] [blame] | 193 | int err; |
| 194 | |
Borislav Petkov | 177fed1 | 2009-08-31 09:50:10 +0200 | [diff] [blame] | 195 | gprs[1] = msr; |
| 196 | gprs[7] = 0x9c5a203a; |
| 197 | |
| 198 | err = native_rdmsr_safe_regs(gprs); |
| 199 | |
| 200 | *p = gprs[0] | ((u64)gprs[2] << 32); |
| 201 | |
Yinghai Lu | b05f78f | 2008-08-22 01:32:50 -0700 | [diff] [blame] | 202 | return err; |
| 203 | } |
Andi Kleen | 1de87bd | 2008-03-22 10:59:28 +0100 | [diff] [blame] | 204 | |
Borislav Petkov | 177fed1 | 2009-08-31 09:50:10 +0200 | [diff] [blame] | 205 | static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) |
| 206 | { |
| 207 | u32 gprs[8] = { 0 }; |
| 208 | |
| 209 | gprs[0] = (u32)val; |
| 210 | gprs[1] = msr; |
| 211 | gprs[2] = val >> 32; |
| 212 | gprs[7] = 0x9c5a203a; |
| 213 | |
| 214 | return native_wrmsr_safe_regs(gprs); |
| 215 | } |
| 216 | |
H. Peter Anvin | 8b956bf | 2009-08-31 14:13:48 -0700 | [diff] [blame] | 217 | static inline int rdmsr_safe_regs(u32 regs[8]) |
Borislav Petkov | 132ec92 | 2009-08-31 09:50:09 +0200 | [diff] [blame] | 218 | { |
| 219 | return native_rdmsr_safe_regs(regs); |
| 220 | } |
| 221 | |
H. Peter Anvin | 8b956bf | 2009-08-31 14:13:48 -0700 | [diff] [blame] | 222 | static inline int wrmsr_safe_regs(u32 regs[8]) |
Borislav Petkov | 132ec92 | 2009-08-31 09:50:09 +0200 | [diff] [blame] | 223 | { |
| 224 | return native_wrmsr_safe_regs(regs); |
| 225 | } |
| 226 | |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 227 | #define rdtscl(low) \ |
Ken Chen | 205516c | 2008-12-16 00:32:21 -0800 | [diff] [blame] | 228 | ((low) = (u32)__native_read_tsc()) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 229 | |
| 230 | #define rdtscll(val) \ |
Ken Chen | 205516c | 2008-12-16 00:32:21 -0800 | [diff] [blame] | 231 | ((val) = __native_read_tsc()) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 232 | |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 233 | #define rdpmc(counter, low, high) \ |
| 234 | do { \ |
| 235 | u64 _l = native_read_pmc((counter)); \ |
| 236 | (low) = (u32)_l; \ |
| 237 | (high) = (u32)(_l >> 32); \ |
| 238 | } while (0) |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 239 | |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 240 | #define rdtscp(low, high, aux) \ |
| 241 | do { \ |
| 242 | unsigned long long _val = native_read_tscp(&(aux)); \ |
| 243 | (low) = (u32)_val; \ |
| 244 | (high) = (u32)(_val >> 32); \ |
| 245 | } while (0) |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 246 | |
| 247 | #define rdtscpll(val, aux) (val) = native_read_tscp(&(aux)) |
| 248 | |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 249 | #endif /* !CONFIG_PARAVIRT */ |
| 250 | |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 251 | |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 252 | #define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val), \ |
| 253 | (u32)((val) >> 32)) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 254 | |
Sheng Yang | 5df9740 | 2009-12-16 13:48:04 +0800 | [diff] [blame] | 255 | #define write_tsc(val1, val2) wrmsr(MSR_IA32_TSC, (val1), (val2)) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 256 | |
Sheng Yang | 5df9740 | 2009-12-16 13:48:04 +0800 | [diff] [blame] | 257 | #define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 258 | |
Borislav Petkov | 5054225 | 2009-12-11 18:14:40 +0100 | [diff] [blame] | 259 | struct msr *msrs_alloc(void); |
| 260 | void msrs_free(struct msr *msrs); |
| 261 | |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 262 | #ifdef CONFIG_SMP |
H. Peter Anvin | c6f3193 | 2008-08-25 17:27:21 -0700 | [diff] [blame] | 263 | int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); |
| 264 | int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); |
Borislav Petkov | b8a4754 | 2009-07-30 11:10:02 +0200 | [diff] [blame] | 265 | void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); |
| 266 | void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 267 | int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); |
| 268 | int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); |
H. Peter Anvin | 8b956bf | 2009-08-31 14:13:48 -0700 | [diff] [blame] | 269 | int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); |
| 270 | int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 271 | #else /* CONFIG_SMP */ |
H. Peter Anvin | c6f3193 | 2008-08-25 17:27:21 -0700 | [diff] [blame] | 272 | static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 273 | { |
| 274 | rdmsr(msr_no, *l, *h); |
H. Peter Anvin | c6f3193 | 2008-08-25 17:27:21 -0700 | [diff] [blame] | 275 | return 0; |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 276 | } |
H. Peter Anvin | c6f3193 | 2008-08-25 17:27:21 -0700 | [diff] [blame] | 277 | static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 278 | { |
| 279 | wrmsr(msr_no, l, h); |
H. Peter Anvin | c6f3193 | 2008-08-25 17:27:21 -0700 | [diff] [blame] | 280 | return 0; |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 281 | } |
Rusty Russell | 0d0fbbd | 2009-11-05 22:45:41 +1030 | [diff] [blame] | 282 | static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, |
Borislav Petkov | b034c19 | 2009-05-22 13:52:19 +0200 | [diff] [blame] | 283 | struct msr *msrs) |
| 284 | { |
| 285 | rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h)); |
| 286 | } |
Rusty Russell | 0d0fbbd | 2009-11-05 22:45:41 +1030 | [diff] [blame] | 287 | static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, |
Borislav Petkov | b034c19 | 2009-05-22 13:52:19 +0200 | [diff] [blame] | 288 | struct msr *msrs) |
| 289 | { |
| 290 | wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h); |
| 291 | } |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 292 | static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, |
| 293 | u32 *l, u32 *h) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 294 | { |
| 295 | return rdmsr_safe(msr_no, l, h); |
| 296 | } |
| 297 | static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) |
| 298 | { |
| 299 | return wrmsr_safe(msr_no, l, h); |
| 300 | } |
H. Peter Anvin | 8b956bf | 2009-08-31 14:13:48 -0700 | [diff] [blame] | 301 | static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) |
| 302 | { |
| 303 | return rdmsr_safe_regs(regs); |
| 304 | } |
| 305 | static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) |
| 306 | { |
| 307 | return wrmsr_safe_regs(regs); |
| 308 | } |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 309 | #endif /* CONFIG_SMP */ |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 310 | #endif /* __KERNEL__ */ |
H. Peter Anvin | ff55df5 | 2009-08-31 14:16:57 -0700 | [diff] [blame] | 311 | #endif /* __ASSEMBLY__ */ |
H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 312 | #endif /* _ASM_X86_MSR_H */ |