Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 1 | Memory Layout on AArch64 Linux |
| 2 | ============================== |
| 3 | |
| 4 | Author: Catalin Marinas <catalin.marinas@arm.com> |
| 5 | Date : 20 February 2012 |
| 6 | |
| 7 | This document describes the virtual memory layout used by the AArch64 |
| 8 | Linux kernel. The architecture allows up to 4 levels of translation |
| 9 | tables with a 4KB page size and up to 3 levels with a 64KB page size. |
| 10 | |
| 11 | AArch64 Linux uses 3 levels of translation tables with the 4KB page |
| 12 | configuration, allowing 39-bit (512GB) virtual addresses for both user |
| 13 | and kernel. With 64KB pages, only 2 levels of translation tables are |
| 14 | used but the memory layout is the same. |
| 15 | |
| 16 | User addresses have bits 63:39 set to 0 while the kernel addresses have |
| 17 | the same bits set to 1. TTBRx selection is given by bit 63 of the |
| 18 | virtual address. The swapper_pg_dir contains only kernel (global) |
| 19 | mappings while the user pgd contains only user (non-global) mappings. |
| 20 | The swapper_pgd_dir address is written to TTBR1 and never written to |
| 21 | TTBR0. |
| 22 | |
| 23 | |
| 24 | AArch64 Linux memory layout: |
| 25 | |
| 26 | Start End Size Use |
| 27 | ----------------------------------------------------------------------- |
| 28 | 0000000000000000 0000007fffffffff 512GB user |
| 29 | |
Catalin Marinas | e3978cd | 2012-10-23 14:51:16 +0100 | [diff] [blame] | 30 | ffffff8000000000 ffffffbbfffeffff ~240GB vmalloc |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 31 | |
Catalin Marinas | e3978cd | 2012-10-23 14:51:16 +0100 | [diff] [blame] | 32 | ffffffbbffff0000 ffffffbbffffffff 64KB [guard page] |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 33 | |
| 34 | ffffffbc00000000 ffffffbdffffffff 8GB vmemmap |
| 35 | |
Catalin Marinas | e3978cd | 2012-10-23 14:51:16 +0100 | [diff] [blame] | 36 | ffffffbe00000000 ffffffbffbbfffff ~8GB [guard, future vmmemap] |
| 37 | |
| 38 | ffffffbffbe00000 ffffffbffbe0ffff 64KB PCI I/O space |
| 39 | |
| 40 | ffffffbbffff0000 ffffffbcffffffff ~2MB [guard] |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 41 | |
| 42 | ffffffbffc000000 ffffffbfffffffff 64MB modules |
| 43 | |
Tekkaman Ninja | 715a711 | 2012-10-28 03:30:20 +0000 | [diff] [blame] | 44 | ffffffc000000000 ffffffffffffffff 256GB kernel logical memory map |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 45 | |
| 46 | |
| 47 | Translation table lookup with 4KB pages: |
| 48 | |
| 49 | +--------+--------+--------+--------+--------+--------+--------+--------+ |
| 50 | |63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0| |
| 51 | +--------+--------+--------+--------+--------+--------+--------+--------+ |
| 52 | | | | | | | |
| 53 | | | | | | v |
| 54 | | | | | | [11:0] in-page offset |
| 55 | | | | | +-> [20:12] L3 index |
| 56 | | | | +-----------> [29:21] L2 index |
| 57 | | | +---------------------> [38:30] L1 index |
| 58 | | +-------------------------------> [47:39] L0 index (not used) |
| 59 | +-------------------------------------------------> [63] TTBR0/1 |
| 60 | |
| 61 | |
| 62 | Translation table lookup with 64KB pages: |
| 63 | |
| 64 | +--------+--------+--------+--------+--------+--------+--------+--------+ |
| 65 | |63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0| |
| 66 | +--------+--------+--------+--------+--------+--------+--------+--------+ |
| 67 | | | | | | |
| 68 | | | | | v |
| 69 | | | | | [15:0] in-page offset |
| 70 | | | | +----------> [28:16] L3 index |
| 71 | | | +--------------------------> [41:29] L2 index (only 38:29 used) |
| 72 | | +-------------------------------> [47:42] L1 index (not used) |
| 73 | +-------------------------------------------------> [63] TTBR0/1 |