Sylwester Nawrocki | 9a761e4 | 2013-03-11 15:14:58 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver |
| 3 | * |
| 4 | * Copyright (C) 2012 - 2013 Samsung Electronics Co., Ltd. |
| 5 | * |
| 6 | * Authors: Younghwan Joo <yhwan.joo@samsung.com> |
| 7 | * Sylwester Nawrocki <s.nawrocki@samsung.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | */ |
| 13 | #include <linux/delay.h> |
| 14 | |
| 15 | #include "fimc-is.h" |
| 16 | #include "fimc-is-command.h" |
| 17 | #include "fimc-is-regs.h" |
| 18 | #include "fimc-is-sensor.h" |
| 19 | |
| 20 | void fimc_is_fw_clear_irq1(struct fimc_is *is, unsigned int nr) |
| 21 | { |
| 22 | mcuctl_write(1UL << nr, is, MCUCTL_REG_INTCR1); |
| 23 | } |
| 24 | |
| 25 | void fimc_is_fw_clear_irq2(struct fimc_is *is) |
| 26 | { |
| 27 | u32 cfg = mcuctl_read(is, MCUCTL_REG_INTSR2); |
| 28 | mcuctl_write(cfg, is, MCUCTL_REG_INTCR2); |
| 29 | } |
| 30 | |
| 31 | void fimc_is_hw_set_intgr0_gd0(struct fimc_is *is) |
| 32 | { |
| 33 | mcuctl_write(INTGR0_INTGD(0), is, MCUCTL_REG_INTGR0); |
| 34 | } |
| 35 | |
| 36 | int fimc_is_hw_wait_intsr0_intsd0(struct fimc_is *is) |
| 37 | { |
| 38 | unsigned int timeout = 2000; |
| 39 | u32 cfg, status; |
| 40 | |
| 41 | cfg = mcuctl_read(is, MCUCTL_REG_INTSR0); |
| 42 | status = INTSR0_GET_INTSD(0, cfg); |
| 43 | |
| 44 | while (status) { |
| 45 | cfg = mcuctl_read(is, MCUCTL_REG_INTSR0); |
| 46 | status = INTSR0_GET_INTSD(0, cfg); |
| 47 | if (timeout == 0) { |
| 48 | dev_warn(&is->pdev->dev, "%s timeout\n", |
| 49 | __func__); |
| 50 | return -ETIME; |
| 51 | } |
| 52 | timeout--; |
| 53 | udelay(1); |
| 54 | } |
| 55 | return 0; |
| 56 | } |
| 57 | |
| 58 | int fimc_is_hw_wait_intmsr0_intmsd0(struct fimc_is *is) |
| 59 | { |
| 60 | unsigned int timeout = 2000; |
| 61 | u32 cfg, status; |
| 62 | |
| 63 | cfg = mcuctl_read(is, MCUCTL_REG_INTMSR0); |
| 64 | status = INTMSR0_GET_INTMSD(0, cfg); |
| 65 | |
| 66 | while (status) { |
| 67 | cfg = mcuctl_read(is, MCUCTL_REG_INTMSR0); |
| 68 | status = INTMSR0_GET_INTMSD(0, cfg); |
| 69 | if (timeout == 0) { |
| 70 | dev_warn(&is->pdev->dev, "%s timeout\n", |
| 71 | __func__); |
| 72 | return -ETIME; |
| 73 | } |
| 74 | timeout--; |
| 75 | udelay(1); |
| 76 | } |
| 77 | return 0; |
| 78 | } |
| 79 | |
| 80 | int fimc_is_hw_set_param(struct fimc_is *is) |
| 81 | { |
Sylwester Nawrocki | 3530ef0 | 2013-04-10 06:24:46 -0300 | [diff] [blame] | 82 | struct chain_config *config = &is->config[is->config_index]; |
Sylwester Nawrocki | a6f5635 | 2013-04-10 06:23:05 -0300 | [diff] [blame] | 83 | unsigned int param_count = __get_pending_param_count(is); |
Sylwester Nawrocki | 9a761e4 | 2013-03-11 15:14:58 -0300 | [diff] [blame] | 84 | |
| 85 | fimc_is_hw_wait_intmsr0_intmsd0(is); |
| 86 | |
| 87 | mcuctl_write(HIC_SET_PARAMETER, is, MCUCTL_REG_ISSR(0)); |
| 88 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); |
Sylwester Nawrocki | 3530ef0 | 2013-04-10 06:24:46 -0300 | [diff] [blame] | 89 | mcuctl_write(is->config_index, is, MCUCTL_REG_ISSR(2)); |
Sylwester Nawrocki | 9a761e4 | 2013-03-11 15:14:58 -0300 | [diff] [blame] | 90 | |
Sylwester Nawrocki | a6f5635 | 2013-04-10 06:23:05 -0300 | [diff] [blame] | 91 | mcuctl_write(param_count, is, MCUCTL_REG_ISSR(3)); |
Sylwester Nawrocki | 3530ef0 | 2013-04-10 06:24:46 -0300 | [diff] [blame] | 92 | mcuctl_write(config->p_region_index1, is, MCUCTL_REG_ISSR(4)); |
| 93 | mcuctl_write(config->p_region_index2, is, MCUCTL_REG_ISSR(5)); |
Sylwester Nawrocki | 9a761e4 | 2013-03-11 15:14:58 -0300 | [diff] [blame] | 94 | |
| 95 | fimc_is_hw_set_intgr0_gd0(is); |
| 96 | return 0; |
| 97 | } |
| 98 | |
| 99 | int fimc_is_hw_set_tune(struct fimc_is *is) |
| 100 | { |
| 101 | fimc_is_hw_wait_intmsr0_intmsd0(is); |
| 102 | |
| 103 | mcuctl_write(HIC_SET_TUNE, is, MCUCTL_REG_ISSR(0)); |
| 104 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); |
| 105 | mcuctl_write(is->h2i_cmd.entry_id, is, MCUCTL_REG_ISSR(2)); |
| 106 | |
| 107 | fimc_is_hw_set_intgr0_gd0(is); |
| 108 | return 0; |
| 109 | } |
| 110 | |
| 111 | #define FIMC_IS_MAX_PARAMS 4 |
| 112 | |
| 113 | int fimc_is_hw_get_params(struct fimc_is *is, unsigned int num_args) |
| 114 | { |
| 115 | int i; |
| 116 | |
| 117 | if (num_args > FIMC_IS_MAX_PARAMS) |
| 118 | return -EINVAL; |
| 119 | |
| 120 | is->i2h_cmd.num_args = num_args; |
| 121 | |
| 122 | for (i = 0; i < FIMC_IS_MAX_PARAMS; i++) { |
| 123 | if (i < num_args) |
| 124 | is->i2h_cmd.args[i] = mcuctl_read(is, |
| 125 | MCUCTL_REG_ISSR(12 + i)); |
| 126 | else |
| 127 | is->i2h_cmd.args[i] = 0; |
| 128 | } |
| 129 | return 0; |
| 130 | } |
| 131 | |
| 132 | void fimc_is_hw_set_sensor_num(struct fimc_is *is) |
| 133 | { |
| 134 | pr_debug("setting sensor index to: %d\n", is->sensor_index); |
| 135 | |
| 136 | mcuctl_write(IH_REPLY_DONE, is, MCUCTL_REG_ISSR(0)); |
| 137 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); |
| 138 | mcuctl_write(IHC_GET_SENSOR_NUM, is, MCUCTL_REG_ISSR(2)); |
| 139 | mcuctl_write(FIMC_IS_SENSOR_NUM, is, MCUCTL_REG_ISSR(3)); |
| 140 | } |
| 141 | |
| 142 | void fimc_is_hw_close_sensor(struct fimc_is *is, unsigned int index) |
| 143 | { |
| 144 | if (is->sensor_index != index) |
| 145 | return; |
| 146 | |
| 147 | fimc_is_hw_wait_intmsr0_intmsd0(is); |
| 148 | mcuctl_write(HIC_CLOSE_SENSOR, is, MCUCTL_REG_ISSR(0)); |
| 149 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); |
| 150 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(2)); |
| 151 | fimc_is_hw_set_intgr0_gd0(is); |
| 152 | } |
| 153 | |
| 154 | void fimc_is_hw_get_setfile_addr(struct fimc_is *is) |
| 155 | { |
| 156 | fimc_is_hw_wait_intmsr0_intmsd0(is); |
| 157 | mcuctl_write(HIC_GET_SET_FILE_ADDR, is, MCUCTL_REG_ISSR(0)); |
| 158 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); |
| 159 | fimc_is_hw_set_intgr0_gd0(is); |
| 160 | } |
| 161 | |
| 162 | void fimc_is_hw_load_setfile(struct fimc_is *is) |
| 163 | { |
| 164 | fimc_is_hw_wait_intmsr0_intmsd0(is); |
| 165 | mcuctl_write(HIC_LOAD_SET_FILE, is, MCUCTL_REG_ISSR(0)); |
| 166 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); |
| 167 | fimc_is_hw_set_intgr0_gd0(is); |
| 168 | } |
| 169 | |
| 170 | int fimc_is_hw_change_mode(struct fimc_is *is) |
| 171 | { |
| 172 | const u8 cmd[] = { |
| 173 | HIC_PREVIEW_STILL, HIC_PREVIEW_VIDEO, |
| 174 | HIC_CAPTURE_STILL, HIC_CAPTURE_VIDEO, |
| 175 | }; |
| 176 | |
Sylwester Nawrocki | 3530ef0 | 2013-04-10 06:24:46 -0300 | [diff] [blame] | 177 | if (WARN_ON(is->config_index > ARRAY_SIZE(cmd))) |
Sylwester Nawrocki | 9a761e4 | 2013-03-11 15:14:58 -0300 | [diff] [blame] | 178 | return -EINVAL; |
| 179 | |
Sylwester Nawrocki | 3530ef0 | 2013-04-10 06:24:46 -0300 | [diff] [blame] | 180 | mcuctl_write(cmd[is->config_index], is, MCUCTL_REG_ISSR(0)); |
Sylwester Nawrocki | 9a761e4 | 2013-03-11 15:14:58 -0300 | [diff] [blame] | 181 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); |
| 182 | mcuctl_write(is->setfile.sub_index, is, MCUCTL_REG_ISSR(2)); |
| 183 | fimc_is_hw_set_intgr0_gd0(is); |
| 184 | return 0; |
| 185 | } |
| 186 | |
| 187 | void fimc_is_hw_stream_on(struct fimc_is *is) |
| 188 | { |
| 189 | fimc_is_hw_wait_intmsr0_intmsd0(is); |
| 190 | mcuctl_write(HIC_STREAM_ON, is, MCUCTL_REG_ISSR(0)); |
| 191 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); |
| 192 | mcuctl_write(0, is, MCUCTL_REG_ISSR(2)); |
| 193 | fimc_is_hw_set_intgr0_gd0(is); |
| 194 | } |
| 195 | |
| 196 | void fimc_is_hw_stream_off(struct fimc_is *is) |
| 197 | { |
| 198 | fimc_is_hw_wait_intmsr0_intmsd0(is); |
| 199 | mcuctl_write(HIC_STREAM_OFF, is, MCUCTL_REG_ISSR(0)); |
| 200 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); |
| 201 | fimc_is_hw_set_intgr0_gd0(is); |
| 202 | } |
| 203 | |
| 204 | void fimc_is_hw_subip_power_off(struct fimc_is *is) |
| 205 | { |
| 206 | fimc_is_hw_wait_intmsr0_intmsd0(is); |
| 207 | mcuctl_write(HIC_POWER_DOWN, is, MCUCTL_REG_ISSR(0)); |
| 208 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); |
| 209 | fimc_is_hw_set_intgr0_gd0(is); |
| 210 | } |
| 211 | |
| 212 | int fimc_is_itf_s_param(struct fimc_is *is, bool update) |
| 213 | { |
| 214 | int ret; |
| 215 | |
| 216 | if (update) |
| 217 | __is_hw_update_params(is); |
| 218 | |
| 219 | fimc_is_mem_barrier(); |
| 220 | |
| 221 | clear_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state); |
| 222 | fimc_is_hw_set_param(is); |
| 223 | ret = fimc_is_wait_event(is, IS_ST_BLOCK_CMD_CLEARED, 1, |
| 224 | FIMC_IS_CONFIG_TIMEOUT); |
| 225 | if (ret < 0) |
| 226 | dev_err(&is->pdev->dev, "%s() timeout\n", __func__); |
| 227 | |
| 228 | return ret; |
| 229 | } |
| 230 | |
| 231 | int fimc_is_itf_mode_change(struct fimc_is *is) |
| 232 | { |
| 233 | int ret; |
| 234 | |
| 235 | clear_bit(IS_ST_CHANGE_MODE, &is->state); |
| 236 | fimc_is_hw_change_mode(is); |
| 237 | ret = fimc_is_wait_event(is, IS_ST_CHANGE_MODE, 1, |
| 238 | FIMC_IS_CONFIG_TIMEOUT); |
| 239 | if (!ret < 0) |
| 240 | dev_err(&is->pdev->dev, "%s(): mode change (%d) timeout\n", |
Sylwester Nawrocki | 3530ef0 | 2013-04-10 06:24:46 -0300 | [diff] [blame] | 241 | __func__, is->config_index); |
Sylwester Nawrocki | 9a761e4 | 2013-03-11 15:14:58 -0300 | [diff] [blame] | 242 | return ret; |
| 243 | } |