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gerrit-public.fairphone.software / kernel / msm-4.9 / c51aa6db2a599b49d53668008f845c670694beb7 / . / arch / arm / boot / dts / imx53.dtsi
blob: 845982eaac22facc6210f699d13f9665edd53319 [file] [log] [blame]
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]13#include "skeleton.dtsi"
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]14#include "imx53-pinfunc.h"
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]15
16/ {
17 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
21 serial3 = &uart4;
22 serial4 = &uart5;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]23 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
27 gpio4 = &gpio5;
28 gpio5 = &gpio6;
29 gpio6 = &gpio7;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]30 };
31
32 tzic: tz-interrupt-controller@0fffc000 {
33 compatible = "fsl,imx53-tzic", "fsl,tzic";
34 interrupt-controller;
35 #interrupt-cells = <1>;
36 reg = <0x0fffc000 0x4000>;
37 };
38
39 clocks {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 ckil {
44 compatible = "fsl,imx-ckil", "fixed-clock";
45 clock-frequency = <32768>;
46 };
47
48 ckih1 {
49 compatible = "fsl,imx-ckih1", "fixed-clock";
50 clock-frequency = <22579200>;
51 };
52
53 ckih2 {
54 compatible = "fsl,imx-ckih2", "fixed-clock";
55 clock-frequency = <0>;
56 };
57
58 osc {
59 compatible = "fsl,imx-osc", "fixed-clock";
60 clock-frequency = <24000000>;
61 };
62 };
63
64 soc {
65 #address-cells = <1>;
66 #size-cells = <1>;
67 compatible = "simple-bus";
68 interrupt-parent = <&tzic>;
69 ranges;
70
Sascha Hauerabed9a62012-06-05 13:52:10 +0200[diff] [blame]71 ipu: ipu@18000000 {
72 #crtc-cells = <1>;
73 compatible = "fsl,imx53-ipu";
74 reg = <0x18000000 0x080000000>;
75 interrupts = <11 10>;
Philipp Zabel4438a6a2013-03-27 18:30:36 +0100[diff] [blame]76 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
77 clock-names = "bus", "di0", "di1";
Philipp Zabel8d84c372013-03-28 17:35:23 +0100[diff] [blame]78 resets = <&src 2>;
Sascha Hauerabed9a62012-06-05 13:52:10 +0200[diff] [blame]79 };
80
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]81 aips@50000000 { /* AIPS1 */
82 compatible = "fsl,aips-bus", "simple-bus";
83 #address-cells = <1>;
84 #size-cells = <1>;
85 reg = <0x50000000 0x10000000>;
86 ranges;
87
88 spba@50000000 {
89 compatible = "fsl,spba-bus", "simple-bus";
90 #address-cells = <1>;
91 #size-cells = <1>;
92 reg = <0x50000000 0x40000>;
93 ranges;
94
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]95 esdhc1: esdhc@50004000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]96 compatible = "fsl,imx53-esdhc";
97 reg = <0x50004000 0x4000>;
98 interrupts = <1>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]99 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
100 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]101 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]102 status = "disabled";
103 };
104
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]105 esdhc2: esdhc@50008000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]106 compatible = "fsl,imx53-esdhc";
107 reg = <0x50008000 0x4000>;
108 interrupts = <2>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]109 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
110 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]111 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]112 status = "disabled";
113 };
114
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]115 uart3: serial@5000c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]116 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
117 reg = <0x5000c000 0x4000>;
118 interrupts = <33>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]119 clocks = <&clks 32>, <&clks 33>;
120 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]121 status = "disabled";
122 };
123
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]124 ecspi1: ecspi@50010000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]125 #address-cells = <1>;
126 #size-cells = <0>;
127 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
128 reg = <0x50010000 0x4000>;
129 interrupts = <36>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]130 clocks = <&clks 51>, <&clks 52>;
131 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]132 status = "disabled";
133 };
134
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]135 ssi2: ssi@50014000 {
136 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
137 reg = <0x50014000 0x4000>;
138 interrupts = <30>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]139 clocks = <&clks 49>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]140 fsl,fifo-depth = <15>;
141 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
142 status = "disabled";
143 };
144
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]145 esdhc3: esdhc@50020000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]146 compatible = "fsl,imx53-esdhc";
147 reg = <0x50020000 0x4000>;
148 interrupts = <3>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]149 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
150 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]151 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]152 status = "disabled";
153 };
154
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]155 esdhc4: esdhc@50024000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]156 compatible = "fsl,imx53-esdhc";
157 reg = <0x50024000 0x4000>;
158 interrupts = <4>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]159 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
160 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]161 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]162 status = "disabled";
163 };
164 };
165
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]166 usbotg: usb@53f80000 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]167 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
168 reg = <0x53f80000 0x0200>;
169 interrupts = <18>;
170 status = "disabled";
171 };
172
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]173 usbh1: usb@53f80200 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]174 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
175 reg = <0x53f80200 0x0200>;
176 interrupts = <14>;
177 status = "disabled";
178 };
179
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]180 usbh2: usb@53f80400 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]181 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
182 reg = <0x53f80400 0x0200>;
183 interrupts = <16>;
184 status = "disabled";
185 };
186
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]187 usbh3: usb@53f80600 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]188 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
189 reg = <0x53f80600 0x0200>;
190 interrupts = <17>;
191 status = "disabled";
192 };
193
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]194 gpio1: gpio@53f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]195 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]196 reg = <0x53f84000 0x4000>;
197 interrupts = <50 51>;
198 gpio-controller;
199 #gpio-cells = <2>;
200 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]201 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]202 };
203
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]204 gpio2: gpio@53f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]205 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]206 reg = <0x53f88000 0x4000>;
207 interrupts = <52 53>;
208 gpio-controller;
209 #gpio-cells = <2>;
210 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]211 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]212 };
213
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]214 gpio3: gpio@53f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]215 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]216 reg = <0x53f8c000 0x4000>;
217 interrupts = <54 55>;
218 gpio-controller;
219 #gpio-cells = <2>;
220 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]221 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]222 };
223
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]224 gpio4: gpio@53f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]225 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]226 reg = <0x53f90000 0x4000>;
227 interrupts = <56 57>;
228 gpio-controller;
229 #gpio-cells = <2>;
230 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]231 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]232 };
233
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]234 wdog1: wdog@53f98000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]235 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
236 reg = <0x53f98000 0x4000>;
237 interrupts = <58>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]238 clocks = <&clks 0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]239 };
240
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]241 wdog2: wdog@53f9c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]242 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
243 reg = <0x53f9c000 0x4000>;
244 interrupts = <59>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]245 clocks = <&clks 0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]246 status = "disabled";
247 };
248
Sascha Hauercc8aae92013-03-14 13:09:00 +0100[diff] [blame]249 gpt: timer@53fa0000 {
250 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
251 reg = <0x53fa0000 0x4000>;
252 interrupts = <39>;
253 clocks = <&clks 36>, <&clks 41>;
254 clock-names = "ipg", "per";
255 };
256
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]257 iomuxc: iomuxc@53fa8000 {
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]258 compatible = "fsl,imx53-iomuxc";
259 reg = <0x53fa8000 0x4000>;
260
261 audmux {
262 pinctrl_audmux_1: audmuxgrp-1 {
263 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]264 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
265 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
266 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
267 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]268 >;
269 };
270 };
271
272 fec {
273 pinctrl_fec_1: fecgrp-1 {
274 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]275 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
276 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
277 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
278 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
279 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
280 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
281 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
282 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
283 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
284 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]285 >;
286 };
287 };
288
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]289 csi {
290 pinctrl_csi_1: csigrp-1 {
291 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]292 MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
293 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
294 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
295 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
296 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
297 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
298 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
299 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
300 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
301 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
302 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
303 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
304 MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5
305 MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5
306 MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5
307 MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5
308 MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5
309 MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5
310 MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5
311 MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5
312 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]313 >;
314 };
315 };
316
317 cspi {
318 pinctrl_cspi_1: cspigrp-1 {
319 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]320 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
321 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
322 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]323 >;
324 };
325 };
326
Shawn Guo327a79c2012-08-12 21:47:36 +0800[diff] [blame]327 ecspi1 {
328 pinctrl_ecspi1_1: ecspi1grp-1 {
329 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]330 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
331 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
332 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
Shawn Guo327a79c2012-08-12 21:47:36 +0800[diff] [blame]333 >;
334 };
335 };
336
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]337 esdhc1 {
338 pinctrl_esdhc1_1: esdhc1grp-1 {
339 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]340 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
341 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
342 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
343 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
344 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
345 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]346 >;
347 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]348
349 pinctrl_esdhc1_2: esdhc1grp-2 {
350 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]351 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
352 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
353 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
354 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
355 MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
356 MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
357 MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
358 MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
359 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
360 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]361 >;
362 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]363 };
364
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]365 esdhc2 {
366 pinctrl_esdhc2_1: esdhc2grp-1 {
367 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]368 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
369 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
370 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
371 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
372 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
373 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]374 >;
375 };
376 };
377
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]378 esdhc3 {
379 pinctrl_esdhc3_1: esdhc3grp-1 {
380 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]381 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
382 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
383 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
384 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
385 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
386 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
387 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
388 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
389 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
390 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]391 >;
392 };
393 };
394
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]395 can1 {
396 pinctrl_can1_1: can1grp-1 {
397 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]398 MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
399 MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]400 >;
401 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]402
403 pinctrl_can1_2: can1grp-2 {
404 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]405 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
406 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]407 >;
408 };
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]409 };
410
411 can2 {
412 pinctrl_can2_1: can2grp-1 {
413 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]414 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
415 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]416 >;
417 };
418 };
419
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]420 i2c1 {
421 pinctrl_i2c1_1: i2c1grp-1 {
422 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]423 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
424 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]425 >;
426 };
427 };
428
429 i2c2 {
430 pinctrl_i2c2_1: i2c2grp-1 {
431 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]432 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
433 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]434 >;
435 };
436 };
437
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]438 i2c3 {
439 pinctrl_i2c3_1: i2c3grp-1 {
440 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]441 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
442 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]443 >;
444 };
445 };
446
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]447 owire {
448 pinctrl_owire_1: owiregrp-1 {
449 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]450 MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]451 >;
452 };
453 };
454
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]455 uart1 {
456 pinctrl_uart1_1: uart1grp-1 {
457 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]458 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5
459 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]460 >;
461 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]462
463 pinctrl_uart1_2: uart1grp-2 {
464 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]465 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1c5
466 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]467 >;
468 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]469 };
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]470
471 uart2 {
472 pinctrl_uart2_1: uart2grp-1 {
473 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]474 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
475 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]476 >;
477 };
478 };
479
480 uart3 {
481 pinctrl_uart3_1: uart3grp-1 {
482 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]483 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
484 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
485 MX53_PAD_PATA_DA_1__UART3_CTS 0x1c5
486 MX53_PAD_PATA_DA_2__UART3_RTS 0x1c5
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]487 >;
488 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]489
490 pinctrl_uart3_2: uart3grp-2 {
491 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]492 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
493 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]494 >;
495 };
496
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]497 };
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]498
499 uart4 {
500 pinctrl_uart4_1: uart4grp-1 {
501 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]502 MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5
503 MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]504 >;
505 };
506 };
507
508 uart5 {
509 pinctrl_uart5_1: uart5grp-1 {
510 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]511 MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5
512 MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]513 >;
514 };
515 };
516
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]517 };
518
Philipp Zabel5af9f142013-03-27 18:30:43 +0100[diff] [blame]519 gpr: iomuxc-gpr@53fa8000 {
520 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
521 reg = <0x53fa8000 0xc>;
522 };
523
Philipp Zabel420714a2013-03-27 18:30:44 +0100[diff] [blame]524 ldb: ldb@53fa8008 {
525 #address-cells = <1>;
526 #size-cells = <0>;
527 compatible = "fsl,imx53-ldb";
528 reg = <0x53fa8008 0x4>;
529 gpr = <&gpr>;
530 clocks = <&clks 122>, <&clks 120>,
531 <&clks 115>, <&clks 116>,
532 <&clks 123>, <&clks 85>;
533 clock-names = "di0_pll", "di1_pll",
534 "di0_sel", "di1_sel",
535 "di0", "di1";
536 status = "disabled";
537
538 lvds-channel@0 {
539 reg = <0>;
540 crtcs = <&ipu 0>;
541 status = "disabled";
542 };
543
544 lvds-channel@1 {
545 reg = <1>;
546 crtcs = <&ipu 1>;
547 status = "disabled";
548 };
549 };
550
Sascha Hauer9ae90af2012-07-04 12:30:37 +0200[diff] [blame]551 pwm1: pwm@53fb4000 {
552 #pwm-cells = <2>;
553 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
554 reg = <0x53fb4000 0x4000>;
555 clocks = <&clks 37>, <&clks 38>;
556 clock-names = "ipg", "per";
557 interrupts = <61>;
558 };
559
560 pwm2: pwm@53fb8000 {
561 #pwm-cells = <2>;
562 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
563 reg = <0x53fb8000 0x4000>;
564 clocks = <&clks 39>, <&clks 40>;
565 clock-names = "ipg", "per";
566 interrupts = <94>;
567 };
568
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]569 uart1: serial@53fbc000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]570 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
571 reg = <0x53fbc000 0x4000>;
572 interrupts = <31>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]573 clocks = <&clks 28>, <&clks 29>;
574 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]575 status = "disabled";
576 };
577
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]578 uart2: serial@53fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]579 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
580 reg = <0x53fc0000 0x4000>;
581 interrupts = <32>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]582 clocks = <&clks 30>, <&clks 31>;
583 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]584 status = "disabled";
585 };
586
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]587 can1: can@53fc8000 {
588 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
589 reg = <0x53fc8000 0x4000>;
590 interrupts = <82>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]591 clocks = <&clks 158>, <&clks 157>;
592 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]593 status = "disabled";
594 };
595
596 can2: can@53fcc000 {
597 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
598 reg = <0x53fcc000 0x4000>;
599 interrupts = <83>;
Marek Vasute37f0d52013-01-07 15:27:00 +0100[diff] [blame]600 clocks = <&clks 87>, <&clks 86>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]601 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]602 status = "disabled";
603 };
604
Philipp Zabel8d84c372013-03-28 17:35:23 +0100[diff] [blame]605 src: src@53fd0000 {
606 compatible = "fsl,imx53-src", "fsl,imx51-src";
607 reg = <0x53fd0000 0x4000>;
608 #reset-cells = <1>;
609 };
610
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]611 clks: ccm@53fd4000{
612 compatible = "fsl,imx53-ccm";
613 reg = <0x53fd4000 0x4000>;
614 interrupts = <0 71 0x04 0 72 0x04>;
615 #clock-cells = <1>;
616 };
617
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]618 gpio5: gpio@53fdc000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]619 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]620 reg = <0x53fdc000 0x4000>;
621 interrupts = <103 104>;
622 gpio-controller;
623 #gpio-cells = <2>;
624 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]625 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]626 };
627
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]628 gpio6: gpio@53fe0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]629 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]630 reg = <0x53fe0000 0x4000>;
631 interrupts = <105 106>;
632 gpio-controller;
633 #gpio-cells = <2>;
634 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]635 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]636 };
637
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]638 gpio7: gpio@53fe4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]639 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]640 reg = <0x53fe4000 0x4000>;
641 interrupts = <107 108>;
642 gpio-controller;
643 #gpio-cells = <2>;
644 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]645 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]646 };
647
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]648 i2c3: i2c@53fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]649 #address-cells = <1>;
650 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]651 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]652 reg = <0x53fec000 0x4000>;
653 interrupts = <64>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]654 clocks = <&clks 88>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]655 status = "disabled";
656 };
657
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]658 uart4: serial@53ff0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]659 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
660 reg = <0x53ff0000 0x4000>;
661 interrupts = <13>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]662 clocks = <&clks 65>, <&clks 66>;
663 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]664 status = "disabled";
665 };
666 };
667
668 aips@60000000 { /* AIPS2 */
669 compatible = "fsl,aips-bus", "simple-bus";
670 #address-cells = <1>;
671 #size-cells = <1>;
672 reg = <0x60000000 0x10000000>;
673 ranges;
674
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]675 uart5: serial@63f90000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]676 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
677 reg = <0x63f90000 0x4000>;
678 interrupts = <86>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]679 clocks = <&clks 67>, <&clks 68>;
680 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]681 status = "disabled";
682 };
683
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]684 owire: owire@63fa4000 {
685 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
686 reg = <0x63fa4000 0x4000>;
687 clocks = <&clks 159>;
688 status = "disabled";
689 };
690
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]691 ecspi2: ecspi@63fac000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]692 #address-cells = <1>;
693 #size-cells = <0>;
694 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
695 reg = <0x63fac000 0x4000>;
696 interrupts = <37>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]697 clocks = <&clks 53>, <&clks 54>;
698 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]699 status = "disabled";
700 };
701
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]702 sdma: sdma@63fb0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]703 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
704 reg = <0x63fb0000 0x4000>;
705 interrupts = <6>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]706 clocks = <&clks 56>, <&clks 56>;
707 clock-names = "ipg", "ahb";
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300[diff] [blame]708 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]709 };
710
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]711 cspi: cspi@63fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]712 #address-cells = <1>;
713 #size-cells = <0>;
714 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
715 reg = <0x63fc0000 0x4000>;
716 interrupts = <38>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]717 clocks = <&clks 55>, <&clks 0>;
718 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]719 status = "disabled";
720 };
721
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]722 i2c2: i2c@63fc4000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]723 #address-cells = <1>;
724 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]725 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]726 reg = <0x63fc4000 0x4000>;
727 interrupts = <63>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]728 clocks = <&clks 35>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]729 status = "disabled";
730 };
731
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]732 i2c1: i2c@63fc8000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]733 #address-cells = <1>;
734 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]735 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]736 reg = <0x63fc8000 0x4000>;
737 interrupts = <62>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]738 clocks = <&clks 34>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]739 status = "disabled";
740 };
741
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]742 ssi1: ssi@63fcc000 {
743 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
744 reg = <0x63fcc000 0x4000>;
745 interrupts = <29>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]746 clocks = <&clks 48>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]747 fsl,fifo-depth = <15>;
748 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
749 status = "disabled";
750 };
751
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]752 audmux: audmux@63fd0000 {
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]753 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
754 reg = <0x63fd0000 0x4000>;
755 status = "disabled";
756 };
757
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]758 nfc: nand@63fdb000 {
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]759 compatible = "fsl,imx53-nand";
760 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
761 interrupts = <8>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]762 clocks = <&clks 60>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]763 status = "disabled";
764 };
765
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]766 ssi3: ssi@63fe8000 {
767 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
768 reg = <0x63fe8000 0x4000>;
769 interrupts = <96>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]770 clocks = <&clks 50>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]771 fsl,fifo-depth = <15>;
772 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
773 status = "disabled";
774 };
775
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]776 fec: ethernet@63fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]777 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
778 reg = <0x63fec000 0x4000>;
779 interrupts = <87>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]780 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
781 clock-names = "ipg", "ahb", "ptp";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]782 status = "disabled";
783 };
784 };
785 };
786};