David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Linux performance counter support for MIPS. |
| 3 | * |
| 4 | * Copyright (C) 2010 MIPS Technologies, Inc. |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 5 | * Copyright (C) 2011 Cavium Networks, Inc. |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 6 | * Author: Deng-Cheng Zhu |
| 7 | * |
| 8 | * This code is based on the implementation for ARM, which is in turn |
| 9 | * based on the sparc64 perf event code and the x86 code. Performance |
| 10 | * counter access is based on the MIPS Oprofile code. And the callchain |
| 11 | * support references the code of MIPS stacktrace.c. |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or modify |
| 14 | * it under the terms of the GNU General Public License version 2 as |
| 15 | * published by the Free Software Foundation. |
| 16 | */ |
| 17 | |
| 18 | #include <linux/cpumask.h> |
| 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/smp.h> |
| 21 | #include <linux/kernel.h> |
| 22 | #include <linux/perf_event.h> |
| 23 | #include <linux/uaccess.h> |
| 24 | |
| 25 | #include <asm/irq.h> |
| 26 | #include <asm/irq_regs.h> |
| 27 | #include <asm/stacktrace.h> |
| 28 | #include <asm/time.h> /* For perf_irq */ |
| 29 | |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 30 | #define MIPS_MAX_HWEVENTS 4 |
| 31 | |
| 32 | struct cpu_hw_events { |
| 33 | /* Array of events on this cpu. */ |
| 34 | struct perf_event *events[MIPS_MAX_HWEVENTS]; |
| 35 | |
| 36 | /* |
| 37 | * Set the bit (indexed by the counter number) when the counter |
| 38 | * is used for an event. |
| 39 | */ |
| 40 | unsigned long used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)]; |
| 41 | |
| 42 | /* |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 43 | * Software copy of the control register for each performance counter. |
| 44 | * MIPS CPUs vary in performance counters. They use this differently, |
| 45 | * and even may not use it. |
| 46 | */ |
| 47 | unsigned int saved_ctrl[MIPS_MAX_HWEVENTS]; |
| 48 | }; |
| 49 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
| 50 | .saved_ctrl = {0}, |
| 51 | }; |
| 52 | |
| 53 | /* The description of MIPS performance events. */ |
| 54 | struct mips_perf_event { |
| 55 | unsigned int event_id; |
| 56 | /* |
| 57 | * MIPS performance counters are indexed starting from 0. |
| 58 | * CNTR_EVEN indicates the indexes of the counters to be used are |
| 59 | * even numbers. |
| 60 | */ |
| 61 | unsigned int cntr_mask; |
| 62 | #define CNTR_EVEN 0x55555555 |
| 63 | #define CNTR_ODD 0xaaaaaaaa |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 64 | #define CNTR_ALL 0xffffffff |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 65 | #ifdef CONFIG_MIPS_MT_SMP |
| 66 | enum { |
| 67 | T = 0, |
| 68 | V = 1, |
| 69 | P = 2, |
| 70 | } range; |
| 71 | #else |
| 72 | #define T |
| 73 | #define V |
| 74 | #define P |
| 75 | #endif |
| 76 | }; |
| 77 | |
| 78 | static struct mips_perf_event raw_event; |
| 79 | static DEFINE_MUTEX(raw_event_mutex); |
| 80 | |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 81 | #define C(x) PERF_COUNT_HW_CACHE_##x |
| 82 | |
| 83 | struct mips_pmu { |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 84 | u64 max_period; |
| 85 | u64 valid_count; |
| 86 | u64 overflow; |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 87 | const char *name; |
| 88 | int irq; |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 89 | u64 (*read_counter)(unsigned int idx); |
| 90 | void (*write_counter)(unsigned int idx, u64 val); |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 91 | const struct mips_perf_event *(*map_raw_event)(u64 config); |
| 92 | const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX]; |
| 93 | const struct mips_perf_event (*cache_event_map) |
| 94 | [PERF_COUNT_HW_CACHE_MAX] |
| 95 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 96 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; |
| 97 | unsigned int num_counters; |
| 98 | }; |
| 99 | |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 100 | static struct mips_pmu mipspmu; |
| 101 | |
| 102 | #define M_CONFIG1_PC (1 << 4) |
| 103 | |
| 104 | #define M_PERFCTL_EXL (1 << 0) |
| 105 | #define M_PERFCTL_KERNEL (1 << 1) |
| 106 | #define M_PERFCTL_SUPERVISOR (1 << 2) |
| 107 | #define M_PERFCTL_USER (1 << 3) |
| 108 | #define M_PERFCTL_INTERRUPT_ENABLE (1 << 4) |
| 109 | #define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5) |
| 110 | #define M_PERFCTL_VPEID(vpe) ((vpe) << 16) |
| 111 | #define M_PERFCTL_MT_EN(filter) ((filter) << 20) |
| 112 | #define M_TC_EN_ALL M_PERFCTL_MT_EN(0) |
| 113 | #define M_TC_EN_VPE M_PERFCTL_MT_EN(1) |
| 114 | #define M_TC_EN_TC M_PERFCTL_MT_EN(2) |
| 115 | #define M_PERFCTL_TCID(tcid) ((tcid) << 22) |
| 116 | #define M_PERFCTL_WIDE (1 << 30) |
| 117 | #define M_PERFCTL_MORE (1 << 31) |
| 118 | |
| 119 | #define M_PERFCTL_COUNT_EVENT_WHENEVER (M_PERFCTL_EXL | \ |
| 120 | M_PERFCTL_KERNEL | \ |
| 121 | M_PERFCTL_USER | \ |
| 122 | M_PERFCTL_SUPERVISOR | \ |
| 123 | M_PERFCTL_INTERRUPT_ENABLE) |
| 124 | |
| 125 | #ifdef CONFIG_MIPS_MT_SMP |
| 126 | #define M_PERFCTL_CONFIG_MASK 0x3fff801f |
| 127 | #else |
| 128 | #define M_PERFCTL_CONFIG_MASK 0x1f |
| 129 | #endif |
| 130 | #define M_PERFCTL_EVENT_MASK 0xfe0 |
| 131 | |
| 132 | |
| 133 | #ifdef CONFIG_MIPS_MT_SMP |
| 134 | static int cpu_has_mipsmt_pertccounters; |
| 135 | |
| 136 | static DEFINE_RWLOCK(pmuint_rwlock); |
| 137 | |
| 138 | /* |
| 139 | * FIXME: For VSMP, vpe_id() is redefined for Perf-events, because |
| 140 | * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs. |
| 141 | */ |
| 142 | #if defined(CONFIG_HW_PERF_EVENTS) |
| 143 | #define vpe_id() (cpu_has_mipsmt_pertccounters ? \ |
| 144 | 0 : smp_processor_id()) |
| 145 | #else |
| 146 | #define vpe_id() (cpu_has_mipsmt_pertccounters ? \ |
| 147 | 0 : cpu_data[smp_processor_id()].vpe_id) |
| 148 | #endif |
| 149 | |
| 150 | /* Copied from op_model_mipsxx.c */ |
| 151 | static unsigned int vpe_shift(void) |
| 152 | { |
| 153 | if (num_possible_cpus() > 1) |
| 154 | return 1; |
| 155 | |
| 156 | return 0; |
| 157 | } |
| 158 | |
| 159 | static unsigned int counters_total_to_per_cpu(unsigned int counters) |
| 160 | { |
| 161 | return counters >> vpe_shift(); |
| 162 | } |
| 163 | |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 164 | #else /* !CONFIG_MIPS_MT_SMP */ |
| 165 | #define vpe_id() 0 |
| 166 | |
| 167 | #endif /* CONFIG_MIPS_MT_SMP */ |
| 168 | |
| 169 | static void resume_local_counters(void); |
| 170 | static void pause_local_counters(void); |
| 171 | static irqreturn_t mipsxx_pmu_handle_irq(int, void *); |
| 172 | static int mipsxx_pmu_handle_shared_irq(void); |
| 173 | |
| 174 | static unsigned int mipsxx_pmu_swizzle_perf_idx(unsigned int idx) |
| 175 | { |
| 176 | if (vpe_id() == 1) |
| 177 | idx = (idx + 2) & 3; |
| 178 | return idx; |
| 179 | } |
| 180 | |
| 181 | static u64 mipsxx_pmu_read_counter(unsigned int idx) |
| 182 | { |
| 183 | idx = mipsxx_pmu_swizzle_perf_idx(idx); |
| 184 | |
| 185 | switch (idx) { |
| 186 | case 0: |
| 187 | /* |
| 188 | * The counters are unsigned, we must cast to truncate |
| 189 | * off the high bits. |
| 190 | */ |
| 191 | return (u32)read_c0_perfcntr0(); |
| 192 | case 1: |
| 193 | return (u32)read_c0_perfcntr1(); |
| 194 | case 2: |
| 195 | return (u32)read_c0_perfcntr2(); |
| 196 | case 3: |
| 197 | return (u32)read_c0_perfcntr3(); |
| 198 | default: |
| 199 | WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); |
| 200 | return 0; |
| 201 | } |
| 202 | } |
| 203 | |
| 204 | static u64 mipsxx_pmu_read_counter_64(unsigned int idx) |
| 205 | { |
| 206 | idx = mipsxx_pmu_swizzle_perf_idx(idx); |
| 207 | |
| 208 | switch (idx) { |
| 209 | case 0: |
| 210 | return read_c0_perfcntr0_64(); |
| 211 | case 1: |
| 212 | return read_c0_perfcntr1_64(); |
| 213 | case 2: |
| 214 | return read_c0_perfcntr2_64(); |
| 215 | case 3: |
| 216 | return read_c0_perfcntr3_64(); |
| 217 | default: |
| 218 | WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); |
| 219 | return 0; |
| 220 | } |
| 221 | } |
| 222 | |
| 223 | static void mipsxx_pmu_write_counter(unsigned int idx, u64 val) |
| 224 | { |
| 225 | idx = mipsxx_pmu_swizzle_perf_idx(idx); |
| 226 | |
| 227 | switch (idx) { |
| 228 | case 0: |
| 229 | write_c0_perfcntr0(val); |
| 230 | return; |
| 231 | case 1: |
| 232 | write_c0_perfcntr1(val); |
| 233 | return; |
| 234 | case 2: |
| 235 | write_c0_perfcntr2(val); |
| 236 | return; |
| 237 | case 3: |
| 238 | write_c0_perfcntr3(val); |
| 239 | return; |
| 240 | } |
| 241 | } |
| 242 | |
| 243 | static void mipsxx_pmu_write_counter_64(unsigned int idx, u64 val) |
| 244 | { |
| 245 | idx = mipsxx_pmu_swizzle_perf_idx(idx); |
| 246 | |
| 247 | switch (idx) { |
| 248 | case 0: |
| 249 | write_c0_perfcntr0_64(val); |
| 250 | return; |
| 251 | case 1: |
| 252 | write_c0_perfcntr1_64(val); |
| 253 | return; |
| 254 | case 2: |
| 255 | write_c0_perfcntr2_64(val); |
| 256 | return; |
| 257 | case 3: |
| 258 | write_c0_perfcntr3_64(val); |
| 259 | return; |
| 260 | } |
| 261 | } |
| 262 | |
| 263 | static unsigned int mipsxx_pmu_read_control(unsigned int idx) |
| 264 | { |
| 265 | idx = mipsxx_pmu_swizzle_perf_idx(idx); |
| 266 | |
| 267 | switch (idx) { |
| 268 | case 0: |
| 269 | return read_c0_perfctrl0(); |
| 270 | case 1: |
| 271 | return read_c0_perfctrl1(); |
| 272 | case 2: |
| 273 | return read_c0_perfctrl2(); |
| 274 | case 3: |
| 275 | return read_c0_perfctrl3(); |
| 276 | default: |
| 277 | WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); |
| 278 | return 0; |
| 279 | } |
| 280 | } |
| 281 | |
| 282 | static void mipsxx_pmu_write_control(unsigned int idx, unsigned int val) |
| 283 | { |
| 284 | idx = mipsxx_pmu_swizzle_perf_idx(idx); |
| 285 | |
| 286 | switch (idx) { |
| 287 | case 0: |
| 288 | write_c0_perfctrl0(val); |
| 289 | return; |
| 290 | case 1: |
| 291 | write_c0_perfctrl1(val); |
| 292 | return; |
| 293 | case 2: |
| 294 | write_c0_perfctrl2(val); |
| 295 | return; |
| 296 | case 3: |
| 297 | write_c0_perfctrl3(val); |
| 298 | return; |
| 299 | } |
| 300 | } |
| 301 | |
| 302 | static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc, |
| 303 | struct hw_perf_event *hwc) |
| 304 | { |
| 305 | int i; |
| 306 | |
| 307 | /* |
| 308 | * We only need to care the counter mask. The range has been |
| 309 | * checked definitely. |
| 310 | */ |
| 311 | unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff; |
| 312 | |
| 313 | for (i = mipspmu.num_counters - 1; i >= 0; i--) { |
| 314 | /* |
| 315 | * Note that some MIPS perf events can be counted by both |
| 316 | * even and odd counters, wheresas many other are only by |
| 317 | * even _or_ odd counters. This introduces an issue that |
| 318 | * when the former kind of event takes the counter the |
| 319 | * latter kind of event wants to use, then the "counter |
| 320 | * allocation" for the latter event will fail. In fact if |
| 321 | * they can be dynamically swapped, they both feel happy. |
| 322 | * But here we leave this issue alone for now. |
| 323 | */ |
| 324 | if (test_bit(i, &cntr_mask) && |
| 325 | !test_and_set_bit(i, cpuc->used_mask)) |
| 326 | return i; |
| 327 | } |
| 328 | |
| 329 | return -EAGAIN; |
| 330 | } |
| 331 | |
| 332 | static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx) |
| 333 | { |
| 334 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 335 | |
| 336 | WARN_ON(idx < 0 || idx >= mipspmu.num_counters); |
| 337 | |
| 338 | cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) | |
| 339 | (evt->config_base & M_PERFCTL_CONFIG_MASK) | |
| 340 | /* Make sure interrupt enabled. */ |
| 341 | M_PERFCTL_INTERRUPT_ENABLE; |
| 342 | /* |
| 343 | * We do not actually let the counter run. Leave it until start(). |
| 344 | */ |
| 345 | } |
| 346 | |
| 347 | static void mipsxx_pmu_disable_event(int idx) |
| 348 | { |
| 349 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 350 | unsigned long flags; |
| 351 | |
| 352 | WARN_ON(idx < 0 || idx >= mipspmu.num_counters); |
| 353 | |
| 354 | local_irq_save(flags); |
| 355 | cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) & |
| 356 | ~M_PERFCTL_COUNT_EVENT_WHENEVER; |
| 357 | mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]); |
| 358 | local_irq_restore(flags); |
| 359 | } |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 360 | |
| 361 | static int mipspmu_event_set_period(struct perf_event *event, |
| 362 | struct hw_perf_event *hwc, |
| 363 | int idx) |
| 364 | { |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 365 | u64 left = local64_read(&hwc->period_left); |
| 366 | u64 period = hwc->sample_period; |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 367 | int ret = 0; |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 368 | |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 369 | if (unlikely((left + period) & (1ULL << 63))) { |
| 370 | /* left underflowed by more than period. */ |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 371 | left = period; |
| 372 | local64_set(&hwc->period_left, left); |
| 373 | hwc->last_period = period; |
| 374 | ret = 1; |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 375 | } else if (unlikely((left + period) <= period)) { |
| 376 | /* left underflowed by less than period. */ |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 377 | left += period; |
| 378 | local64_set(&hwc->period_left, left); |
| 379 | hwc->last_period = period; |
| 380 | ret = 1; |
| 381 | } |
| 382 | |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 383 | if (left > mipspmu.max_period) { |
| 384 | left = mipspmu.max_period; |
| 385 | local64_set(&hwc->period_left, left); |
| 386 | } |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 387 | |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 388 | local64_set(&hwc->prev_count, mipspmu.overflow - left); |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 389 | |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 390 | mipspmu.write_counter(idx, mipspmu.overflow - left); |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 391 | |
| 392 | perf_event_update_userpage(event); |
| 393 | |
| 394 | return ret; |
| 395 | } |
| 396 | |
| 397 | static void mipspmu_event_update(struct perf_event *event, |
| 398 | struct hw_perf_event *hwc, |
| 399 | int idx) |
| 400 | { |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 401 | u64 prev_raw_count, new_raw_count; |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 402 | u64 delta; |
| 403 | |
| 404 | again: |
| 405 | prev_raw_count = local64_read(&hwc->prev_count); |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 406 | new_raw_count = mipspmu.read_counter(idx); |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 407 | |
| 408 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
| 409 | new_raw_count) != prev_raw_count) |
| 410 | goto again; |
| 411 | |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 412 | delta = new_raw_count - prev_raw_count; |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 413 | |
| 414 | local64_add(delta, &event->count); |
| 415 | local64_sub(delta, &hwc->period_left); |
| 416 | } |
| 417 | |
| 418 | static void mipspmu_start(struct perf_event *event, int flags) |
| 419 | { |
| 420 | struct hw_perf_event *hwc = &event->hw; |
| 421 | |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 422 | if (flags & PERF_EF_RELOAD) |
| 423 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); |
| 424 | |
| 425 | hwc->state = 0; |
| 426 | |
| 427 | /* Set the period for the event. */ |
| 428 | mipspmu_event_set_period(event, hwc, hwc->idx); |
| 429 | |
| 430 | /* Enable the event. */ |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 431 | mipsxx_pmu_enable_event(hwc, hwc->idx); |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 432 | } |
| 433 | |
| 434 | static void mipspmu_stop(struct perf_event *event, int flags) |
| 435 | { |
| 436 | struct hw_perf_event *hwc = &event->hw; |
| 437 | |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 438 | if (!(hwc->state & PERF_HES_STOPPED)) { |
| 439 | /* We are working on a local event. */ |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 440 | mipsxx_pmu_disable_event(hwc->idx); |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 441 | barrier(); |
| 442 | mipspmu_event_update(event, hwc, hwc->idx); |
| 443 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
| 444 | } |
| 445 | } |
| 446 | |
| 447 | static int mipspmu_add(struct perf_event *event, int flags) |
| 448 | { |
| 449 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 450 | struct hw_perf_event *hwc = &event->hw; |
| 451 | int idx; |
| 452 | int err = 0; |
| 453 | |
| 454 | perf_pmu_disable(event->pmu); |
| 455 | |
| 456 | /* To look for a free counter for this event. */ |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 457 | idx = mipsxx_pmu_alloc_counter(cpuc, hwc); |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 458 | if (idx < 0) { |
| 459 | err = idx; |
| 460 | goto out; |
| 461 | } |
| 462 | |
| 463 | /* |
| 464 | * If there is an event in the counter we are going to use then |
| 465 | * make sure it is disabled. |
| 466 | */ |
| 467 | event->hw.idx = idx; |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 468 | mipsxx_pmu_disable_event(idx); |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 469 | cpuc->events[idx] = event; |
| 470 | |
| 471 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
| 472 | if (flags & PERF_EF_START) |
| 473 | mipspmu_start(event, PERF_EF_RELOAD); |
| 474 | |
| 475 | /* Propagate our changes to the userspace mapping. */ |
| 476 | perf_event_update_userpage(event); |
| 477 | |
| 478 | out: |
| 479 | perf_pmu_enable(event->pmu); |
| 480 | return err; |
| 481 | } |
| 482 | |
| 483 | static void mipspmu_del(struct perf_event *event, int flags) |
| 484 | { |
| 485 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 486 | struct hw_perf_event *hwc = &event->hw; |
| 487 | int idx = hwc->idx; |
| 488 | |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 489 | WARN_ON(idx < 0 || idx >= mipspmu.num_counters); |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 490 | |
| 491 | mipspmu_stop(event, PERF_EF_UPDATE); |
| 492 | cpuc->events[idx] = NULL; |
| 493 | clear_bit(idx, cpuc->used_mask); |
| 494 | |
| 495 | perf_event_update_userpage(event); |
| 496 | } |
| 497 | |
| 498 | static void mipspmu_read(struct perf_event *event) |
| 499 | { |
| 500 | struct hw_perf_event *hwc = &event->hw; |
| 501 | |
| 502 | /* Don't read disabled counters! */ |
| 503 | if (hwc->idx < 0) |
| 504 | return; |
| 505 | |
| 506 | mipspmu_event_update(event, hwc, hwc->idx); |
| 507 | } |
| 508 | |
| 509 | static void mipspmu_enable(struct pmu *pmu) |
| 510 | { |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 511 | #ifdef CONFIG_MIPS_MT_SMP |
| 512 | write_unlock(&pmuint_rwlock); |
| 513 | #endif |
| 514 | resume_local_counters(); |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 515 | } |
| 516 | |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 517 | /* |
| 518 | * MIPS performance counters can be per-TC. The control registers can |
| 519 | * not be directly accessed accross CPUs. Hence if we want to do global |
| 520 | * control, we need cross CPU calls. on_each_cpu() can help us, but we |
| 521 | * can not make sure this function is called with interrupts enabled. So |
| 522 | * here we pause local counters and then grab a rwlock and leave the |
| 523 | * counters on other CPUs alone. If any counter interrupt raises while |
| 524 | * we own the write lock, simply pause local counters on that CPU and |
| 525 | * spin in the handler. Also we know we won't be switched to another |
| 526 | * CPU after pausing local counters and before grabbing the lock. |
| 527 | */ |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 528 | static void mipspmu_disable(struct pmu *pmu) |
| 529 | { |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 530 | pause_local_counters(); |
| 531 | #ifdef CONFIG_MIPS_MT_SMP |
| 532 | write_lock(&pmuint_rwlock); |
| 533 | #endif |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 534 | } |
| 535 | |
| 536 | static atomic_t active_events = ATOMIC_INIT(0); |
| 537 | static DEFINE_MUTEX(pmu_reserve_mutex); |
| 538 | static int (*save_perf_irq)(void); |
| 539 | |
| 540 | static int mipspmu_get_irq(void) |
| 541 | { |
| 542 | int err; |
| 543 | |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 544 | if (mipspmu.irq >= 0) { |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 545 | /* Request my own irq handler. */ |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 546 | err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq, |
| 547 | IRQF_PERCPU | IRQF_NOBALANCING, |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 548 | "mips_perf_pmu", NULL); |
| 549 | if (err) { |
| 550 | pr_warning("Unable to request IRQ%d for MIPS " |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 551 | "performance counters!\n", mipspmu.irq); |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 552 | } |
| 553 | } else if (cp0_perfcount_irq < 0) { |
| 554 | /* |
| 555 | * We are sharing the irq number with the timer interrupt. |
| 556 | */ |
| 557 | save_perf_irq = perf_irq; |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 558 | perf_irq = mipsxx_pmu_handle_shared_irq; |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 559 | err = 0; |
| 560 | } else { |
| 561 | pr_warning("The platform hasn't properly defined its " |
| 562 | "interrupt controller.\n"); |
| 563 | err = -ENOENT; |
| 564 | } |
| 565 | |
| 566 | return err; |
| 567 | } |
| 568 | |
| 569 | static void mipspmu_free_irq(void) |
| 570 | { |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 571 | if (mipspmu.irq >= 0) |
| 572 | free_irq(mipspmu.irq, NULL); |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 573 | else if (cp0_perfcount_irq < 0) |
| 574 | perf_irq = save_perf_irq; |
| 575 | } |
| 576 | |
| 577 | /* |
| 578 | * mipsxx/rm9000/loongson2 have different performance counters, they have |
| 579 | * specific low-level init routines. |
| 580 | */ |
| 581 | static void reset_counters(void *arg); |
| 582 | static int __hw_perf_event_init(struct perf_event *event); |
| 583 | |
| 584 | static void hw_perf_event_destroy(struct perf_event *event) |
| 585 | { |
| 586 | if (atomic_dec_and_mutex_lock(&active_events, |
| 587 | &pmu_reserve_mutex)) { |
| 588 | /* |
| 589 | * We must not call the destroy function with interrupts |
| 590 | * disabled. |
| 591 | */ |
| 592 | on_each_cpu(reset_counters, |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 593 | (void *)(long)mipspmu.num_counters, 1); |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 594 | mipspmu_free_irq(); |
| 595 | mutex_unlock(&pmu_reserve_mutex); |
| 596 | } |
| 597 | } |
| 598 | |
| 599 | static int mipspmu_event_init(struct perf_event *event) |
| 600 | { |
| 601 | int err = 0; |
| 602 | |
Stephane Eranian | 2481c5f | 2012-02-09 23:20:59 +0100 | [diff] [blame] | 603 | /* does not support taken branch sampling */ |
| 604 | if (has_branch_stack(event)) |
| 605 | return -EOPNOTSUPP; |
| 606 | |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 607 | switch (event->attr.type) { |
| 608 | case PERF_TYPE_RAW: |
| 609 | case PERF_TYPE_HARDWARE: |
| 610 | case PERF_TYPE_HW_CACHE: |
| 611 | break; |
| 612 | |
| 613 | default: |
| 614 | return -ENOENT; |
| 615 | } |
| 616 | |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 617 | if (event->cpu >= nr_cpumask_bits || |
| 618 | (event->cpu >= 0 && !cpu_online(event->cpu))) |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 619 | return -ENODEV; |
| 620 | |
| 621 | if (!atomic_inc_not_zero(&active_events)) { |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 622 | mutex_lock(&pmu_reserve_mutex); |
| 623 | if (atomic_read(&active_events) == 0) |
| 624 | err = mipspmu_get_irq(); |
| 625 | |
| 626 | if (!err) |
| 627 | atomic_inc(&active_events); |
| 628 | mutex_unlock(&pmu_reserve_mutex); |
| 629 | } |
| 630 | |
| 631 | if (err) |
| 632 | return err; |
| 633 | |
Deng-Cheng Zhu | ff5d726 | 2011-11-22 03:28:48 +0800 | [diff] [blame] | 634 | return __hw_perf_event_init(event); |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 635 | } |
| 636 | |
| 637 | static struct pmu pmu = { |
| 638 | .pmu_enable = mipspmu_enable, |
| 639 | .pmu_disable = mipspmu_disable, |
| 640 | .event_init = mipspmu_event_init, |
| 641 | .add = mipspmu_add, |
| 642 | .del = mipspmu_del, |
| 643 | .start = mipspmu_start, |
| 644 | .stop = mipspmu_stop, |
| 645 | .read = mipspmu_read, |
| 646 | }; |
| 647 | |
| 648 | static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev) |
| 649 | { |
| 650 | /* |
| 651 | * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for |
| 652 | * event_id. |
| 653 | */ |
| 654 | #ifdef CONFIG_MIPS_MT_SMP |
| 655 | return ((unsigned int)pev->range << 24) | |
| 656 | (pev->cntr_mask & 0xffff00) | |
| 657 | (pev->event_id & 0xff); |
| 658 | #else |
| 659 | return (pev->cntr_mask & 0xffff00) | |
| 660 | (pev->event_id & 0xff); |
| 661 | #endif |
| 662 | } |
| 663 | |
| 664 | static const struct mips_perf_event *mipspmu_map_general_event(int idx) |
| 665 | { |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 666 | |
Al Cooper | c5600b2 | 2012-07-13 16:44:50 -0400 | [diff] [blame^] | 667 | if ((*mipspmu.general_event_map)[idx].cntr_mask == 0) |
| 668 | return ERR_PTR(-EOPNOTSUPP); |
| 669 | return &(*mipspmu.general_event_map)[idx]; |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 670 | } |
| 671 | |
| 672 | static const struct mips_perf_event *mipspmu_map_cache_event(u64 config) |
| 673 | { |
| 674 | unsigned int cache_type, cache_op, cache_result; |
| 675 | const struct mips_perf_event *pev; |
| 676 | |
| 677 | cache_type = (config >> 0) & 0xff; |
| 678 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) |
| 679 | return ERR_PTR(-EINVAL); |
| 680 | |
| 681 | cache_op = (config >> 8) & 0xff; |
| 682 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) |
| 683 | return ERR_PTR(-EINVAL); |
| 684 | |
| 685 | cache_result = (config >> 16) & 0xff; |
| 686 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) |
| 687 | return ERR_PTR(-EINVAL); |
| 688 | |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 689 | pev = &((*mipspmu.cache_event_map) |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 690 | [cache_type] |
| 691 | [cache_op] |
| 692 | [cache_result]); |
| 693 | |
Al Cooper | c5600b2 | 2012-07-13 16:44:50 -0400 | [diff] [blame^] | 694 | if (pev->cntr_mask == 0) |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 695 | return ERR_PTR(-EOPNOTSUPP); |
| 696 | |
| 697 | return pev; |
| 698 | |
| 699 | } |
| 700 | |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 701 | static int validate_group(struct perf_event *event) |
| 702 | { |
| 703 | struct perf_event *sibling, *leader = event->group_leader; |
| 704 | struct cpu_hw_events fake_cpuc; |
| 705 | |
| 706 | memset(&fake_cpuc, 0, sizeof(fake_cpuc)); |
| 707 | |
Deng-Cheng Zhu | 266623b7 | 2011-11-22 03:28:47 +0800 | [diff] [blame] | 708 | if (mipsxx_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0) |
Peter Zijlstra | aa2bc1a | 2011-11-09 17:56:37 +0100 | [diff] [blame] | 709 | return -EINVAL; |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 710 | |
| 711 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { |
Deng-Cheng Zhu | 266623b7 | 2011-11-22 03:28:47 +0800 | [diff] [blame] | 712 | if (mipsxx_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0) |
Peter Zijlstra | aa2bc1a | 2011-11-09 17:56:37 +0100 | [diff] [blame] | 713 | return -EINVAL; |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 714 | } |
| 715 | |
Deng-Cheng Zhu | 266623b7 | 2011-11-22 03:28:47 +0800 | [diff] [blame] | 716 | if (mipsxx_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0) |
Peter Zijlstra | aa2bc1a | 2011-11-09 17:56:37 +0100 | [diff] [blame] | 717 | return -EINVAL; |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 718 | |
| 719 | return 0; |
| 720 | } |
| 721 | |
| 722 | /* This is needed by specific irq handlers in perf_event_*.c */ |
| 723 | static void handle_associated_event(struct cpu_hw_events *cpuc, |
| 724 | int idx, struct perf_sample_data *data, |
| 725 | struct pt_regs *regs) |
| 726 | { |
| 727 | struct perf_event *event = cpuc->events[idx]; |
| 728 | struct hw_perf_event *hwc = &event->hw; |
| 729 | |
| 730 | mipspmu_event_update(event, hwc, idx); |
| 731 | data->period = event->hw.last_period; |
| 732 | if (!mipspmu_event_set_period(event, hwc, idx)) |
| 733 | return; |
| 734 | |
| 735 | if (perf_event_overflow(event, data, regs)) |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 736 | mipsxx_pmu_disable_event(idx); |
David Daney | e5dcb58 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 737 | } |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 738 | |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 739 | |
David Daney | 4409af3 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 740 | static int __n_counters(void) |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 741 | { |
| 742 | if (!(read_c0_config1() & M_CONFIG1_PC)) |
| 743 | return 0; |
| 744 | if (!(read_c0_perfctrl0() & M_PERFCTL_MORE)) |
| 745 | return 1; |
| 746 | if (!(read_c0_perfctrl1() & M_PERFCTL_MORE)) |
| 747 | return 2; |
| 748 | if (!(read_c0_perfctrl2() & M_PERFCTL_MORE)) |
| 749 | return 3; |
| 750 | |
| 751 | return 4; |
| 752 | } |
| 753 | |
David Daney | 4409af3 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 754 | static int n_counters(void) |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 755 | { |
| 756 | int counters; |
| 757 | |
| 758 | switch (current_cpu_type()) { |
| 759 | case CPU_R10000: |
| 760 | counters = 2; |
| 761 | break; |
| 762 | |
| 763 | case CPU_R12000: |
| 764 | case CPU_R14000: |
| 765 | counters = 4; |
| 766 | break; |
| 767 | |
| 768 | default: |
| 769 | counters = __n_counters(); |
| 770 | } |
| 771 | |
| 772 | return counters; |
| 773 | } |
| 774 | |
| 775 | static void reset_counters(void *arg) |
| 776 | { |
| 777 | int counters = (int)(long)arg; |
| 778 | switch (counters) { |
| 779 | case 4: |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 780 | mipsxx_pmu_write_control(3, 0); |
| 781 | mipspmu.write_counter(3, 0); |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 782 | case 3: |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 783 | mipsxx_pmu_write_control(2, 0); |
| 784 | mipspmu.write_counter(2, 0); |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 785 | case 2: |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 786 | mipsxx_pmu_write_control(1, 0); |
| 787 | mipspmu.write_counter(1, 0); |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 788 | case 1: |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 789 | mipsxx_pmu_write_control(0, 0); |
| 790 | mipspmu.write_counter(0, 0); |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 791 | } |
| 792 | } |
| 793 | |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 794 | /* 24K/34K/1004K cores can share the same event map. */ |
| 795 | static const struct mips_perf_event mipsxxcore_event_map |
| 796 | [PERF_COUNT_HW_MAX] = { |
| 797 | [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, |
| 798 | [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 799 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T }, |
| 800 | [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T }, |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 801 | }; |
| 802 | |
| 803 | /* 74K core has different branch event code. */ |
| 804 | static const struct mips_perf_event mipsxx74Kcore_event_map |
| 805 | [PERF_COUNT_HW_MAX] = { |
| 806 | [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, |
| 807 | [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 808 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T }, |
| 809 | [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T }, |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 810 | }; |
| 811 | |
David Daney | 939991c | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 812 | static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = { |
| 813 | [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL }, |
| 814 | [PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL }, |
| 815 | [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x2b, CNTR_ALL }, |
| 816 | [PERF_COUNT_HW_CACHE_MISSES] = { 0x2e, CNTR_ALL }, |
| 817 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x08, CNTR_ALL }, |
| 818 | [PERF_COUNT_HW_BRANCH_MISSES] = { 0x09, CNTR_ALL }, |
| 819 | [PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL }, |
| 820 | }; |
| 821 | |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 822 | /* 24K/34K/1004K cores can share the same cache event map. */ |
| 823 | static const struct mips_perf_event mipsxxcore_cache_map |
| 824 | [PERF_COUNT_HW_CACHE_MAX] |
| 825 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 826 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { |
| 827 | [C(L1D)] = { |
| 828 | /* |
| 829 | * Like some other architectures (e.g. ARM), the performance |
| 830 | * counters don't differentiate between read and write |
| 831 | * accesses/misses, so this isn't strictly correct, but it's the |
| 832 | * best we can do. Writes and reads get combined. |
| 833 | */ |
| 834 | [C(OP_READ)] = { |
| 835 | [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T }, |
| 836 | [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T }, |
| 837 | }, |
| 838 | [C(OP_WRITE)] = { |
| 839 | [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T }, |
| 840 | [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T }, |
| 841 | }, |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 842 | }, |
| 843 | [C(L1I)] = { |
| 844 | [C(OP_READ)] = { |
| 845 | [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T }, |
| 846 | [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T }, |
| 847 | }, |
| 848 | [C(OP_WRITE)] = { |
| 849 | [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T }, |
| 850 | [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T }, |
| 851 | }, |
| 852 | [C(OP_PREFETCH)] = { |
| 853 | [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T }, |
| 854 | /* |
| 855 | * Note that MIPS has only "hit" events countable for |
| 856 | * the prefetch operation. |
| 857 | */ |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 858 | }, |
| 859 | }, |
| 860 | [C(LL)] = { |
| 861 | [C(OP_READ)] = { |
| 862 | [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P }, |
| 863 | [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P }, |
| 864 | }, |
| 865 | [C(OP_WRITE)] = { |
| 866 | [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P }, |
| 867 | [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P }, |
| 868 | }, |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 869 | }, |
| 870 | [C(DTLB)] = { |
| 871 | [C(OP_READ)] = { |
| 872 | [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, |
| 873 | [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, |
| 874 | }, |
| 875 | [C(OP_WRITE)] = { |
| 876 | [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, |
| 877 | [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, |
| 878 | }, |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 879 | }, |
| 880 | [C(ITLB)] = { |
| 881 | [C(OP_READ)] = { |
| 882 | [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T }, |
| 883 | [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T }, |
| 884 | }, |
| 885 | [C(OP_WRITE)] = { |
| 886 | [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T }, |
| 887 | [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T }, |
| 888 | }, |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 889 | }, |
| 890 | [C(BPU)] = { |
| 891 | /* Using the same code for *HW_BRANCH* */ |
| 892 | [C(OP_READ)] = { |
| 893 | [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T }, |
| 894 | [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, |
| 895 | }, |
| 896 | [C(OP_WRITE)] = { |
| 897 | [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T }, |
| 898 | [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, |
| 899 | }, |
Peter Zijlstra | 89d6c0b | 2011-04-22 23:37:06 +0200 | [diff] [blame] | 900 | }, |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 901 | }; |
| 902 | |
| 903 | /* 74K core has completely different cache event map. */ |
| 904 | static const struct mips_perf_event mipsxx74Kcore_cache_map |
| 905 | [PERF_COUNT_HW_CACHE_MAX] |
| 906 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 907 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { |
| 908 | [C(L1D)] = { |
| 909 | /* |
| 910 | * Like some other architectures (e.g. ARM), the performance |
| 911 | * counters don't differentiate between read and write |
| 912 | * accesses/misses, so this isn't strictly correct, but it's the |
| 913 | * best we can do. Writes and reads get combined. |
| 914 | */ |
| 915 | [C(OP_READ)] = { |
| 916 | [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T }, |
| 917 | [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T }, |
| 918 | }, |
| 919 | [C(OP_WRITE)] = { |
| 920 | [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T }, |
| 921 | [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T }, |
| 922 | }, |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 923 | }, |
| 924 | [C(L1I)] = { |
| 925 | [C(OP_READ)] = { |
| 926 | [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, |
| 927 | [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, |
| 928 | }, |
| 929 | [C(OP_WRITE)] = { |
| 930 | [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, |
| 931 | [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, |
| 932 | }, |
| 933 | [C(OP_PREFETCH)] = { |
| 934 | [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T }, |
| 935 | /* |
| 936 | * Note that MIPS has only "hit" events countable for |
| 937 | * the prefetch operation. |
| 938 | */ |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 939 | }, |
| 940 | }, |
| 941 | [C(LL)] = { |
| 942 | [C(OP_READ)] = { |
| 943 | [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, |
| 944 | [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P }, |
| 945 | }, |
| 946 | [C(OP_WRITE)] = { |
| 947 | [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, |
| 948 | [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P }, |
| 949 | }, |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 950 | }, |
| 951 | [C(ITLB)] = { |
| 952 | [C(OP_READ)] = { |
| 953 | [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T }, |
| 954 | [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T }, |
| 955 | }, |
| 956 | [C(OP_WRITE)] = { |
| 957 | [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T }, |
| 958 | [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T }, |
| 959 | }, |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 960 | }, |
| 961 | [C(BPU)] = { |
| 962 | /* Using the same code for *HW_BRANCH* */ |
| 963 | [C(OP_READ)] = { |
| 964 | [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T }, |
| 965 | [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T }, |
| 966 | }, |
| 967 | [C(OP_WRITE)] = { |
| 968 | [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T }, |
| 969 | [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T }, |
| 970 | }, |
Peter Zijlstra | 89d6c0b | 2011-04-22 23:37:06 +0200 | [diff] [blame] | 971 | }, |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 972 | }; |
| 973 | |
David Daney | 939991c | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 974 | |
| 975 | static const struct mips_perf_event octeon_cache_map |
| 976 | [PERF_COUNT_HW_CACHE_MAX] |
| 977 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 978 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { |
| 979 | [C(L1D)] = { |
| 980 | [C(OP_READ)] = { |
| 981 | [C(RESULT_ACCESS)] = { 0x2b, CNTR_ALL }, |
| 982 | [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, |
| 983 | }, |
| 984 | [C(OP_WRITE)] = { |
| 985 | [C(RESULT_ACCESS)] = { 0x30, CNTR_ALL }, |
David Daney | 939991c | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 986 | }, |
| 987 | }, |
| 988 | [C(L1I)] = { |
| 989 | [C(OP_READ)] = { |
| 990 | [C(RESULT_ACCESS)] = { 0x18, CNTR_ALL }, |
David Daney | 939991c | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 991 | }, |
| 992 | [C(OP_PREFETCH)] = { |
| 993 | [C(RESULT_ACCESS)] = { 0x19, CNTR_ALL }, |
David Daney | 939991c | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 994 | }, |
| 995 | }, |
| 996 | [C(DTLB)] = { |
| 997 | /* |
| 998 | * Only general DTLB misses are counted use the same event for |
| 999 | * read and write. |
| 1000 | */ |
| 1001 | [C(OP_READ)] = { |
David Daney | 939991c | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1002 | [C(RESULT_MISS)] = { 0x35, CNTR_ALL }, |
| 1003 | }, |
| 1004 | [C(OP_WRITE)] = { |
David Daney | 939991c | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1005 | [C(RESULT_MISS)] = { 0x35, CNTR_ALL }, |
| 1006 | }, |
David Daney | 939991c | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1007 | }, |
| 1008 | [C(ITLB)] = { |
| 1009 | [C(OP_READ)] = { |
David Daney | 939991c | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1010 | [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, |
| 1011 | }, |
David Daney | 939991c | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1012 | }, |
| 1013 | }; |
| 1014 | |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1015 | #ifdef CONFIG_MIPS_MT_SMP |
David Daney | 4409af3 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1016 | static void check_and_calc_range(struct perf_event *event, |
| 1017 | const struct mips_perf_event *pev) |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1018 | { |
| 1019 | struct hw_perf_event *hwc = &event->hw; |
| 1020 | |
| 1021 | if (event->cpu >= 0) { |
| 1022 | if (pev->range > V) { |
| 1023 | /* |
| 1024 | * The user selected an event that is processor |
| 1025 | * wide, while expecting it to be VPE wide. |
| 1026 | */ |
| 1027 | hwc->config_base |= M_TC_EN_ALL; |
| 1028 | } else { |
| 1029 | /* |
| 1030 | * FIXME: cpu_data[event->cpu].vpe_id reports 0 |
| 1031 | * for both CPUs. |
| 1032 | */ |
| 1033 | hwc->config_base |= M_PERFCTL_VPEID(event->cpu); |
| 1034 | hwc->config_base |= M_TC_EN_VPE; |
| 1035 | } |
| 1036 | } else |
| 1037 | hwc->config_base |= M_TC_EN_ALL; |
| 1038 | } |
| 1039 | #else |
David Daney | 4409af3 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1040 | static void check_and_calc_range(struct perf_event *event, |
| 1041 | const struct mips_perf_event *pev) |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1042 | { |
| 1043 | } |
| 1044 | #endif |
| 1045 | |
| 1046 | static int __hw_perf_event_init(struct perf_event *event) |
| 1047 | { |
| 1048 | struct perf_event_attr *attr = &event->attr; |
| 1049 | struct hw_perf_event *hwc = &event->hw; |
| 1050 | const struct mips_perf_event *pev; |
| 1051 | int err; |
| 1052 | |
| 1053 | /* Returning MIPS event descriptor for generic perf event. */ |
| 1054 | if (PERF_TYPE_HARDWARE == event->attr.type) { |
| 1055 | if (event->attr.config >= PERF_COUNT_HW_MAX) |
| 1056 | return -EINVAL; |
| 1057 | pev = mipspmu_map_general_event(event->attr.config); |
| 1058 | } else if (PERF_TYPE_HW_CACHE == event->attr.type) { |
| 1059 | pev = mipspmu_map_cache_event(event->attr.config); |
| 1060 | } else if (PERF_TYPE_RAW == event->attr.type) { |
| 1061 | /* We are working on the global raw event. */ |
| 1062 | mutex_lock(&raw_event_mutex); |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1063 | pev = mipspmu.map_raw_event(event->attr.config); |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1064 | } else { |
| 1065 | /* The event type is not (yet) supported. */ |
| 1066 | return -EOPNOTSUPP; |
| 1067 | } |
| 1068 | |
| 1069 | if (IS_ERR(pev)) { |
| 1070 | if (PERF_TYPE_RAW == event->attr.type) |
| 1071 | mutex_unlock(&raw_event_mutex); |
| 1072 | return PTR_ERR(pev); |
| 1073 | } |
| 1074 | |
| 1075 | /* |
| 1076 | * We allow max flexibility on how each individual counter shared |
| 1077 | * by the single CPU operates (the mode exclusion and the range). |
| 1078 | */ |
| 1079 | hwc->config_base = M_PERFCTL_INTERRUPT_ENABLE; |
| 1080 | |
| 1081 | /* Calculate range bits and validate it. */ |
| 1082 | if (num_possible_cpus() > 1) |
| 1083 | check_and_calc_range(event, pev); |
| 1084 | |
| 1085 | hwc->event_base = mipspmu_perf_event_encode(pev); |
| 1086 | if (PERF_TYPE_RAW == event->attr.type) |
| 1087 | mutex_unlock(&raw_event_mutex); |
| 1088 | |
| 1089 | if (!attr->exclude_user) |
| 1090 | hwc->config_base |= M_PERFCTL_USER; |
| 1091 | if (!attr->exclude_kernel) { |
| 1092 | hwc->config_base |= M_PERFCTL_KERNEL; |
| 1093 | /* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */ |
| 1094 | hwc->config_base |= M_PERFCTL_EXL; |
| 1095 | } |
| 1096 | if (!attr->exclude_hv) |
| 1097 | hwc->config_base |= M_PERFCTL_SUPERVISOR; |
| 1098 | |
| 1099 | hwc->config_base &= M_PERFCTL_CONFIG_MASK; |
| 1100 | /* |
| 1101 | * The event can belong to another cpu. We do not assign a local |
| 1102 | * counter for it for now. |
| 1103 | */ |
| 1104 | hwc->idx = -1; |
| 1105 | hwc->config = 0; |
| 1106 | |
| 1107 | if (!hwc->sample_period) { |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1108 | hwc->sample_period = mipspmu.max_period; |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1109 | hwc->last_period = hwc->sample_period; |
| 1110 | local64_set(&hwc->period_left, hwc->sample_period); |
| 1111 | } |
| 1112 | |
| 1113 | err = 0; |
Deng-Cheng Zhu | ff5d726 | 2011-11-22 03:28:48 +0800 | [diff] [blame] | 1114 | if (event->group_leader != event) |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1115 | err = validate_group(event); |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1116 | |
| 1117 | event->destroy = hw_perf_event_destroy; |
Deng-Cheng Zhu | ff5d726 | 2011-11-22 03:28:48 +0800 | [diff] [blame] | 1118 | |
| 1119 | if (err) |
| 1120 | event->destroy(event); |
| 1121 | |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1122 | return err; |
| 1123 | } |
| 1124 | |
| 1125 | static void pause_local_counters(void) |
| 1126 | { |
| 1127 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1128 | int ctr = mipspmu.num_counters; |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1129 | unsigned long flags; |
| 1130 | |
| 1131 | local_irq_save(flags); |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1132 | do { |
| 1133 | ctr--; |
| 1134 | cpuc->saved_ctrl[ctr] = mipsxx_pmu_read_control(ctr); |
| 1135 | mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr] & |
| 1136 | ~M_PERFCTL_COUNT_EVENT_WHENEVER); |
| 1137 | } while (ctr > 0); |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1138 | local_irq_restore(flags); |
| 1139 | } |
| 1140 | |
| 1141 | static void resume_local_counters(void) |
| 1142 | { |
| 1143 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1144 | int ctr = mipspmu.num_counters; |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1145 | |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1146 | do { |
| 1147 | ctr--; |
| 1148 | mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr]); |
| 1149 | } while (ctr > 0); |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1150 | } |
| 1151 | |
| 1152 | static int mipsxx_pmu_handle_shared_irq(void) |
| 1153 | { |
| 1154 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 1155 | struct perf_sample_data data; |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1156 | unsigned int counters = mipspmu.num_counters; |
| 1157 | u64 counter; |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1158 | int handled = IRQ_NONE; |
| 1159 | struct pt_regs *regs; |
| 1160 | |
| 1161 | if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26))) |
| 1162 | return handled; |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1163 | /* |
| 1164 | * First we pause the local counters, so that when we are locked |
| 1165 | * here, the counters are all paused. When it gets locked due to |
| 1166 | * perf_disable(), the timer interrupt handler will be delayed. |
| 1167 | * |
| 1168 | * See also mipsxx_pmu_start(). |
| 1169 | */ |
| 1170 | pause_local_counters(); |
| 1171 | #ifdef CONFIG_MIPS_MT_SMP |
| 1172 | read_lock(&pmuint_rwlock); |
| 1173 | #endif |
| 1174 | |
| 1175 | regs = get_irq_regs(); |
| 1176 | |
Robert Richter | fd0d000 | 2012-04-02 20:19:08 +0200 | [diff] [blame] | 1177 | perf_sample_data_init(&data, 0, 0); |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1178 | |
| 1179 | switch (counters) { |
| 1180 | #define HANDLE_COUNTER(n) \ |
| 1181 | case n + 1: \ |
| 1182 | if (test_bit(n, cpuc->used_mask)) { \ |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1183 | counter = mipspmu.read_counter(n); \ |
| 1184 | if (counter & mipspmu.overflow) { \ |
| 1185 | handle_associated_event(cpuc, n, &data, regs); \ |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1186 | handled = IRQ_HANDLED; \ |
| 1187 | } \ |
| 1188 | } |
| 1189 | HANDLE_COUNTER(3) |
| 1190 | HANDLE_COUNTER(2) |
| 1191 | HANDLE_COUNTER(1) |
| 1192 | HANDLE_COUNTER(0) |
| 1193 | } |
| 1194 | |
| 1195 | /* |
| 1196 | * Do all the work for the pending perf events. We can do this |
| 1197 | * in here because the performance counter interrupt is a regular |
| 1198 | * interrupt, not NMI. |
| 1199 | */ |
| 1200 | if (handled == IRQ_HANDLED) |
Deng-Cheng Zhu | 91f0173 | 2011-01-21 16:19:17 +0800 | [diff] [blame] | 1201 | irq_work_run(); |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1202 | |
| 1203 | #ifdef CONFIG_MIPS_MT_SMP |
| 1204 | read_unlock(&pmuint_rwlock); |
| 1205 | #endif |
| 1206 | resume_local_counters(); |
| 1207 | return handled; |
| 1208 | } |
| 1209 | |
David Daney | 4409af3 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1210 | static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev) |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1211 | { |
| 1212 | return mipsxx_pmu_handle_shared_irq(); |
| 1213 | } |
| 1214 | |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1215 | /* 24K */ |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1216 | #define IS_BOTH_COUNTERS_24K_EVENT(b) \ |
| 1217 | ((b) == 0 || (b) == 1 || (b) == 11) |
| 1218 | |
| 1219 | /* 34K */ |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1220 | #define IS_BOTH_COUNTERS_34K_EVENT(b) \ |
| 1221 | ((b) == 0 || (b) == 1 || (b) == 11) |
| 1222 | #ifdef CONFIG_MIPS_MT_SMP |
| 1223 | #define IS_RANGE_P_34K_EVENT(r, b) \ |
| 1224 | ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \ |
| 1225 | (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 || \ |
| 1226 | (r) == 176 || ((b) >= 50 && (b) <= 55) || \ |
| 1227 | ((b) >= 64 && (b) <= 67)) |
| 1228 | #define IS_RANGE_V_34K_EVENT(r) ((r) == 47) |
| 1229 | #endif |
| 1230 | |
| 1231 | /* 74K */ |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1232 | #define IS_BOTH_COUNTERS_74K_EVENT(b) \ |
| 1233 | ((b) == 0 || (b) == 1) |
| 1234 | |
| 1235 | /* 1004K */ |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1236 | #define IS_BOTH_COUNTERS_1004K_EVENT(b) \ |
| 1237 | ((b) == 0 || (b) == 1 || (b) == 11) |
| 1238 | #ifdef CONFIG_MIPS_MT_SMP |
| 1239 | #define IS_RANGE_P_1004K_EVENT(r, b) \ |
| 1240 | ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \ |
| 1241 | (b) == 25 || (b) == 36 || (b) == 39 || (r) == 44 || \ |
| 1242 | (r) == 174 || (r) == 176 || ((b) >= 50 && (b) <= 59) || \ |
| 1243 | (r) == 188 || (b) == 61 || (b) == 62 || \ |
| 1244 | ((b) >= 64 && (b) <= 67)) |
| 1245 | #define IS_RANGE_V_1004K_EVENT(r) ((r) == 47) |
| 1246 | #endif |
| 1247 | |
| 1248 | /* |
| 1249 | * User can use 0-255 raw events, where 0-127 for the events of even |
| 1250 | * counters, and 128-255 for odd counters. Note that bit 7 is used to |
| 1251 | * indicate the parity. So, for example, when user wants to take the |
| 1252 | * Event Num of 15 for odd counters (by referring to the user manual), |
| 1253 | * then 128 needs to be added to 15 as the input for the event config, |
| 1254 | * i.e., 143 (0x8F) to be used. |
| 1255 | */ |
David Daney | 4409af3 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1256 | static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config) |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1257 | { |
| 1258 | unsigned int raw_id = config & 0xff; |
| 1259 | unsigned int base_id = raw_id & 0x7f; |
| 1260 | |
Deng-Cheng Zhu | 2c1b54d | 2011-11-22 03:28:45 +0800 | [diff] [blame] | 1261 | raw_event.event_id = base_id; |
| 1262 | |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1263 | switch (current_cpu_type()) { |
| 1264 | case CPU_24K: |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1265 | if (IS_BOTH_COUNTERS_24K_EVENT(base_id)) |
| 1266 | raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; |
| 1267 | else |
| 1268 | raw_event.cntr_mask = |
| 1269 | raw_id > 127 ? CNTR_ODD : CNTR_EVEN; |
| 1270 | #ifdef CONFIG_MIPS_MT_SMP |
| 1271 | /* |
| 1272 | * This is actually doing nothing. Non-multithreading |
| 1273 | * CPUs will not check and calculate the range. |
| 1274 | */ |
| 1275 | raw_event.range = P; |
| 1276 | #endif |
| 1277 | break; |
| 1278 | case CPU_34K: |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1279 | if (IS_BOTH_COUNTERS_34K_EVENT(base_id)) |
| 1280 | raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; |
| 1281 | else |
| 1282 | raw_event.cntr_mask = |
| 1283 | raw_id > 127 ? CNTR_ODD : CNTR_EVEN; |
| 1284 | #ifdef CONFIG_MIPS_MT_SMP |
| 1285 | if (IS_RANGE_P_34K_EVENT(raw_id, base_id)) |
| 1286 | raw_event.range = P; |
| 1287 | else if (unlikely(IS_RANGE_V_34K_EVENT(raw_id))) |
| 1288 | raw_event.range = V; |
| 1289 | else |
| 1290 | raw_event.range = T; |
| 1291 | #endif |
| 1292 | break; |
| 1293 | case CPU_74K: |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1294 | if (IS_BOTH_COUNTERS_74K_EVENT(base_id)) |
| 1295 | raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; |
| 1296 | else |
| 1297 | raw_event.cntr_mask = |
| 1298 | raw_id > 127 ? CNTR_ODD : CNTR_EVEN; |
| 1299 | #ifdef CONFIG_MIPS_MT_SMP |
| 1300 | raw_event.range = P; |
| 1301 | #endif |
| 1302 | break; |
| 1303 | case CPU_1004K: |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1304 | if (IS_BOTH_COUNTERS_1004K_EVENT(base_id)) |
| 1305 | raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; |
| 1306 | else |
| 1307 | raw_event.cntr_mask = |
| 1308 | raw_id > 127 ? CNTR_ODD : CNTR_EVEN; |
| 1309 | #ifdef CONFIG_MIPS_MT_SMP |
| 1310 | if (IS_RANGE_P_1004K_EVENT(raw_id, base_id)) |
| 1311 | raw_event.range = P; |
| 1312 | else if (unlikely(IS_RANGE_V_1004K_EVENT(raw_id))) |
| 1313 | raw_event.range = V; |
| 1314 | else |
| 1315 | raw_event.range = T; |
| 1316 | #endif |
| 1317 | break; |
| 1318 | } |
| 1319 | |
| 1320 | return &raw_event; |
| 1321 | } |
| 1322 | |
David Daney | 939991c | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1323 | static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config) |
| 1324 | { |
| 1325 | unsigned int raw_id = config & 0xff; |
| 1326 | unsigned int base_id = raw_id & 0x7f; |
| 1327 | |
| 1328 | |
| 1329 | raw_event.cntr_mask = CNTR_ALL; |
| 1330 | raw_event.event_id = base_id; |
| 1331 | |
| 1332 | if (current_cpu_type() == CPU_CAVIUM_OCTEON2) { |
| 1333 | if (base_id > 0x42) |
| 1334 | return ERR_PTR(-EOPNOTSUPP); |
| 1335 | } else { |
| 1336 | if (base_id > 0x3a) |
| 1337 | return ERR_PTR(-EOPNOTSUPP); |
| 1338 | } |
| 1339 | |
| 1340 | switch (base_id) { |
| 1341 | case 0x00: |
| 1342 | case 0x0f: |
| 1343 | case 0x1e: |
| 1344 | case 0x1f: |
| 1345 | case 0x2f: |
| 1346 | case 0x34: |
| 1347 | case 0x3b ... 0x3f: |
| 1348 | return ERR_PTR(-EOPNOTSUPP); |
| 1349 | default: |
| 1350 | break; |
| 1351 | } |
| 1352 | |
| 1353 | return &raw_event; |
| 1354 | } |
| 1355 | |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1356 | static int __init |
| 1357 | init_hw_perf_events(void) |
| 1358 | { |
| 1359 | int counters, irq; |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1360 | int counter_bits; |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1361 | |
| 1362 | pr_info("Performance counters: "); |
| 1363 | |
| 1364 | counters = n_counters(); |
| 1365 | if (counters == 0) { |
| 1366 | pr_cont("No available PMU.\n"); |
| 1367 | return -ENODEV; |
| 1368 | } |
| 1369 | |
| 1370 | #ifdef CONFIG_MIPS_MT_SMP |
| 1371 | cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19); |
| 1372 | if (!cpu_has_mipsmt_pertccounters) |
| 1373 | counters = counters_total_to_per_cpu(counters); |
| 1374 | #endif |
| 1375 | |
| 1376 | #ifdef MSC01E_INT_BASE |
| 1377 | if (cpu_has_veic) { |
| 1378 | /* |
| 1379 | * Using platform specific interrupt controller defines. |
| 1380 | */ |
| 1381 | irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; |
| 1382 | } else { |
| 1383 | #endif |
Felix Fietkau | 3572a2c | 2012-05-02 17:33:04 +0200 | [diff] [blame] | 1384 | if ((cp0_perfcount_irq >= 0) && |
| 1385 | (cp0_compare_irq != cp0_perfcount_irq)) |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1386 | irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; |
| 1387 | else |
| 1388 | irq = -1; |
| 1389 | #ifdef MSC01E_INT_BASE |
| 1390 | } |
| 1391 | #endif |
| 1392 | |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1393 | mipspmu.map_raw_event = mipsxx_pmu_map_raw_event; |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1394 | |
| 1395 | switch (current_cpu_type()) { |
| 1396 | case CPU_24K: |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1397 | mipspmu.name = "mips/24K"; |
| 1398 | mipspmu.general_event_map = &mipsxxcore_event_map; |
| 1399 | mipspmu.cache_event_map = &mipsxxcore_cache_map; |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1400 | break; |
| 1401 | case CPU_34K: |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1402 | mipspmu.name = "mips/34K"; |
| 1403 | mipspmu.general_event_map = &mipsxxcore_event_map; |
| 1404 | mipspmu.cache_event_map = &mipsxxcore_cache_map; |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1405 | break; |
| 1406 | case CPU_74K: |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1407 | mipspmu.name = "mips/74K"; |
| 1408 | mipspmu.general_event_map = &mipsxx74Kcore_event_map; |
| 1409 | mipspmu.cache_event_map = &mipsxx74Kcore_cache_map; |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1410 | break; |
| 1411 | case CPU_1004K: |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1412 | mipspmu.name = "mips/1004K"; |
| 1413 | mipspmu.general_event_map = &mipsxxcore_event_map; |
| 1414 | mipspmu.cache_event_map = &mipsxxcore_cache_map; |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1415 | break; |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 1416 | case CPU_LOONGSON1: |
| 1417 | mipspmu.name = "mips/loongson1"; |
| 1418 | mipspmu.general_event_map = &mipsxxcore_event_map; |
| 1419 | mipspmu.cache_event_map = &mipsxxcore_cache_map; |
| 1420 | break; |
David Daney | 939991c | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1421 | case CPU_CAVIUM_OCTEON: |
| 1422 | case CPU_CAVIUM_OCTEON_PLUS: |
| 1423 | case CPU_CAVIUM_OCTEON2: |
| 1424 | mipspmu.name = "octeon"; |
| 1425 | mipspmu.general_event_map = &octeon_event_map; |
| 1426 | mipspmu.cache_event_map = &octeon_cache_map; |
| 1427 | mipspmu.map_raw_event = octeon_pmu_map_raw_event; |
| 1428 | break; |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1429 | default: |
| 1430 | pr_cont("Either hardware does not support performance " |
| 1431 | "counters, or not yet implemented.\n"); |
| 1432 | return -ENODEV; |
| 1433 | } |
| 1434 | |
David Daney | 8209156 | 2011-09-24 02:29:55 +0200 | [diff] [blame] | 1435 | mipspmu.num_counters = counters; |
| 1436 | mipspmu.irq = irq; |
| 1437 | |
| 1438 | if (read_c0_perfctrl0() & M_PERFCTL_WIDE) { |
| 1439 | mipspmu.max_period = (1ULL << 63) - 1; |
| 1440 | mipspmu.valid_count = (1ULL << 63) - 1; |
| 1441 | mipspmu.overflow = 1ULL << 63; |
| 1442 | mipspmu.read_counter = mipsxx_pmu_read_counter_64; |
| 1443 | mipspmu.write_counter = mipsxx_pmu_write_counter_64; |
| 1444 | counter_bits = 64; |
| 1445 | } else { |
| 1446 | mipspmu.max_period = (1ULL << 31) - 1; |
| 1447 | mipspmu.valid_count = (1ULL << 31) - 1; |
| 1448 | mipspmu.overflow = 1ULL << 31; |
| 1449 | mipspmu.read_counter = mipsxx_pmu_read_counter; |
| 1450 | mipspmu.write_counter = mipsxx_pmu_write_counter; |
| 1451 | counter_bits = 32; |
| 1452 | } |
| 1453 | |
| 1454 | on_each_cpu(reset_counters, (void *)(long)counters, 1); |
| 1455 | |
| 1456 | pr_cont("%s PMU enabled, %d %d-bit counters available to each " |
| 1457 | "CPU, irq %d%s\n", mipspmu.name, counters, counter_bits, irq, |
| 1458 | irq < 0 ? " (share with timer interrupt)" : ""); |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1459 | |
Deng-Cheng Zhu | 404ff63 | 2011-01-21 16:19:18 +0800 | [diff] [blame] | 1460 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
| 1461 | |
Deng-Cheng Zhu | 3a9ab99 | 2010-10-12 19:37:24 +0800 | [diff] [blame] | 1462 | return 0; |
| 1463 | } |
Peter Zijlstra | 004417a | 2010-11-25 18:38:29 +0100 | [diff] [blame] | 1464 | early_initcall(init_hw_perf_events); |